bx50v3.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2015 Timesys Corporation
  4. * Copyright 2015 General Electric Company
  5. * Copyright 2012 Freescale Semiconductor, Inc.
  6. */
  7. #include <asm/arch/clock.h>
  8. #include <asm/arch/imx-regs.h>
  9. #include <asm/arch/iomux.h>
  10. #include <asm/arch/mx6-pins.h>
  11. #include <env.h>
  12. #include <linux/errno.h>
  13. #include <linux/libfdt.h>
  14. #include <asm/gpio.h>
  15. #include <asm/mach-imx/mxc_i2c.h>
  16. #include <asm/mach-imx/iomux-v3.h>
  17. #include <asm/mach-imx/boot_mode.h>
  18. #include <asm/mach-imx/video.h>
  19. #include <mmc.h>
  20. #include <fsl_esdhc_imx.h>
  21. #include <miiphy.h>
  22. #include <net.h>
  23. #include <netdev.h>
  24. #include <asm/arch/mxc_hdmi.h>
  25. #include <asm/arch/crm_regs.h>
  26. #include <asm/io.h>
  27. #include <asm/arch/sys_proto.h>
  28. #include <i2c.h>
  29. #include <input.h>
  30. #include <pwm.h>
  31. #include <version.h>
  32. #include <stdlib.h>
  33. #include "../common/ge_common.h"
  34. #include "../common/vpd_reader.h"
  35. #include "../../../drivers/net/e1000.h"
  36. DECLARE_GLOBAL_DATA_PTR;
  37. static int confidx = 3; /* Default to b850v3. */
  38. static struct vpd_cache vpd;
  39. #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  40. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  41. PAD_CTL_HYS)
  42. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  43. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  44. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  45. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  46. PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
  47. #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
  48. PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
  49. #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  50. PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
  51. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  52. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  53. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  54. #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  55. int dram_init(void)
  56. {
  57. gd->ram_size = imx_ddr_size();
  58. return 0;
  59. }
  60. static iomux_v3_cfg_t const uart3_pads[] = {
  61. MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  62. MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  63. MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  64. MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  65. };
  66. static iomux_v3_cfg_t const uart4_pads[] = {
  67. MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  68. MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  69. };
  70. static iomux_v3_cfg_t const enet_pads[] = {
  71. MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  72. MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  73. MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  74. MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  75. MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  76. MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  77. MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  78. MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  79. MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
  80. MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  81. MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  82. MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  83. MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  84. MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  85. MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  86. /* AR8033 PHY Reset */
  87. MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
  88. };
  89. static void setup_iomux_enet(void)
  90. {
  91. imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
  92. /* Reset AR8033 PHY */
  93. gpio_request(IMX_GPIO_NR(1, 28), "fec_rst");
  94. gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
  95. mdelay(10);
  96. gpio_set_value(IMX_GPIO_NR(1, 28), 1);
  97. mdelay(1);
  98. }
  99. static struct i2c_pads_info i2c_pad_info1 = {
  100. .scl = {
  101. .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
  102. .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
  103. .gp = IMX_GPIO_NR(5, 27)
  104. },
  105. .sda = {
  106. .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
  107. .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
  108. .gp = IMX_GPIO_NR(5, 26)
  109. }
  110. };
  111. static struct i2c_pads_info i2c_pad_info2 = {
  112. .scl = {
  113. .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
  114. .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
  115. .gp = IMX_GPIO_NR(4, 12)
  116. },
  117. .sda = {
  118. .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
  119. .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
  120. .gp = IMX_GPIO_NR(4, 13)
  121. }
  122. };
  123. static struct i2c_pads_info i2c_pad_info3 = {
  124. .scl = {
  125. .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
  126. .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
  127. .gp = IMX_GPIO_NR(1, 3)
  128. },
  129. .sda = {
  130. .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
  131. .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
  132. .gp = IMX_GPIO_NR(1, 6)
  133. }
  134. };
  135. static iomux_v3_cfg_t const pcie_pads[] = {
  136. MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
  137. MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
  138. };
  139. static void setup_pcie(void)
  140. {
  141. imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
  142. }
  143. static void setup_iomux_uart(void)
  144. {
  145. imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
  146. imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
  147. }
  148. static int mx6_rgmii_rework(struct phy_device *phydev)
  149. {
  150. /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
  151. /* set device address 0x7 */
  152. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  153. /* offset 0x8016: CLK_25M Clock Select */
  154. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
  155. /* enable register write, no post increment, address 0x7 */
  156. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
  157. /* set to 125 MHz from local PLL source */
  158. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
  159. /* rgmii tx clock delay enable */
  160. /* set debug port address: SerDes Test and System Mode Control */
  161. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
  162. /* enable rgmii tx clock delay */
  163. /* set the reserved bits to avoid board specific voltage peak issue*/
  164. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
  165. return 0;
  166. }
  167. int board_phy_config(struct phy_device *phydev)
  168. {
  169. mx6_rgmii_rework(phydev);
  170. if (phydev->drv->config)
  171. phydev->drv->config(phydev);
  172. return 0;
  173. }
  174. #if defined(CONFIG_VIDEO_IPUV3)
  175. static iomux_v3_cfg_t const backlight_pads[] = {
  176. /* Power for LVDS Display */
  177. MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
  178. #define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
  179. /* Backlight enable for LVDS display */
  180. MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
  181. #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
  182. /* backlight PWM brightness control */
  183. MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
  184. };
  185. static void do_enable_hdmi(struct display_info_t const *dev)
  186. {
  187. imx_enable_hdmi_phy();
  188. }
  189. int board_cfb_skip(void)
  190. {
  191. gpio_direction_output(LVDS_POWER_GP, 1);
  192. return 0;
  193. }
  194. static int is_b850v3(void)
  195. {
  196. return confidx == 3;
  197. }
  198. static int detect_lcd(struct display_info_t const *dev)
  199. {
  200. return !is_b850v3();
  201. }
  202. struct display_info_t const displays[] = {{
  203. .bus = -1,
  204. .addr = -1,
  205. .pixfmt = IPU_PIX_FMT_RGB24,
  206. .detect = detect_lcd,
  207. .enable = NULL,
  208. .mode = {
  209. .name = "G121X1-L03",
  210. .refresh = 60,
  211. .xres = 1024,
  212. .yres = 768,
  213. .pixclock = 15385,
  214. .left_margin = 20,
  215. .right_margin = 300,
  216. .upper_margin = 30,
  217. .lower_margin = 8,
  218. .hsync_len = 1,
  219. .vsync_len = 1,
  220. .sync = FB_SYNC_EXT,
  221. .vmode = FB_VMODE_NONINTERLACED
  222. } }, {
  223. .bus = -1,
  224. .addr = 3,
  225. .pixfmt = IPU_PIX_FMT_RGB24,
  226. .detect = detect_hdmi,
  227. .enable = do_enable_hdmi,
  228. .mode = {
  229. .name = "HDMI",
  230. .refresh = 60,
  231. .xres = 1024,
  232. .yres = 768,
  233. .pixclock = 15385,
  234. .left_margin = 220,
  235. .right_margin = 40,
  236. .upper_margin = 21,
  237. .lower_margin = 7,
  238. .hsync_len = 60,
  239. .vsync_len = 10,
  240. .sync = FB_SYNC_EXT,
  241. .vmode = FB_VMODE_NONINTERLACED
  242. } } };
  243. size_t display_count = ARRAY_SIZE(displays);
  244. static void enable_videopll(void)
  245. {
  246. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  247. s32 timeout = 100000;
  248. setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
  249. /* PLL_VIDEO 455MHz (24MHz * (37+11/12) / 2)
  250. * |
  251. * PLL5
  252. * |
  253. * CS2CDR[LDB_DI0_CLK_SEL]
  254. * |
  255. * +----> LDB_DI0_SERIAL_CLK_ROOT
  256. * |
  257. * +--> CSCMR2[LDB_DI0_IPU_DIV] --> LDB_DI0_IPU 455 / 7 = 65 MHz
  258. */
  259. clrsetbits_le32(&ccm->analog_pll_video,
  260. BM_ANADIG_PLL_VIDEO_DIV_SELECT |
  261. BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
  262. BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
  263. BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
  264. writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
  265. writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
  266. clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
  267. while (timeout--)
  268. if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
  269. break;
  270. if (timeout < 0)
  271. printf("Warning: video pll lock timeout!\n");
  272. clrsetbits_le32(&ccm->analog_pll_video,
  273. BM_ANADIG_PLL_VIDEO_BYPASS,
  274. BM_ANADIG_PLL_VIDEO_ENABLE);
  275. }
  276. static void setup_display_b850v3(void)
  277. {
  278. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  279. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  280. enable_videopll();
  281. /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
  282. setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
  283. imx_setup_hdmi();
  284. /* Set LDB_DI0 as clock source for IPU_DI0 */
  285. clrsetbits_le32(&mxc_ccm->chsccdr,
  286. MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
  287. (CHSCCDR_CLK_SEL_LDB_DI0 <<
  288. MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
  289. /* Turn on IPU LDB DI0 clocks */
  290. setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
  291. enable_ipu_clock();
  292. writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
  293. IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
  294. IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
  295. IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
  296. IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
  297. IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
  298. IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
  299. IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
  300. IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
  301. IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
  302. &iomux->gpr[2]);
  303. clrbits_le32(&iomux->gpr[3],
  304. IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
  305. IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
  306. IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
  307. }
  308. static void setup_display_bx50v3(void)
  309. {
  310. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  311. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  312. enable_videopll();
  313. /* When a reset/reboot is performed the display power needs to be turned
  314. * off for atleast 500ms. The boot time is ~300ms, we need to wait for
  315. * an additional 200ms here. Unfortunately we use external PMIC for
  316. * doing the reset, so can not differentiate between POR vs soft reset
  317. */
  318. mdelay(200);
  319. /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
  320. setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
  321. /* Set LDB_DI0 as clock source for IPU_DI0 */
  322. clrsetbits_le32(&mxc_ccm->chsccdr,
  323. MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
  324. (CHSCCDR_CLK_SEL_LDB_DI0 <<
  325. MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
  326. /* Turn on IPU LDB DI0 clocks */
  327. setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
  328. enable_ipu_clock();
  329. writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
  330. IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
  331. IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
  332. IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
  333. IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
  334. &iomux->gpr[2]);
  335. clrsetbits_le32(&iomux->gpr[3],
  336. IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
  337. (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
  338. IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
  339. /* backlights off until needed */
  340. imx_iomux_v3_setup_multiple_pads(backlight_pads,
  341. ARRAY_SIZE(backlight_pads));
  342. gpio_request(LVDS_POWER_GP, "lvds_power");
  343. gpio_direction_input(LVDS_POWER_GP);
  344. }
  345. #endif /* CONFIG_VIDEO_IPUV3 */
  346. /*
  347. * Do not overwrite the console
  348. * Use always serial for U-Boot console
  349. */
  350. int overwrite_console(void)
  351. {
  352. return 1;
  353. }
  354. #define VPD_TYPE_INVALID 0x00
  355. #define VPD_BLOCK_NETWORK 0x20
  356. #define VPD_BLOCK_HWID 0x44
  357. #define VPD_PRODUCT_B850 1
  358. #define VPD_PRODUCT_B650 2
  359. #define VPD_PRODUCT_B450 3
  360. #define VPD_HAS_MAC1 0x1
  361. #define VPD_HAS_MAC2 0x2
  362. #define VPD_MAC_ADDRESS_LENGTH 6
  363. struct vpd_cache {
  364. bool is_read;
  365. u8 product_id;
  366. u8 has;
  367. unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
  368. unsigned char mac2[VPD_MAC_ADDRESS_LENGTH];
  369. };
  370. /*
  371. * Extracts MAC and product information from the VPD.
  372. */
  373. static int vpd_callback(struct vpd_cache *vpd, u8 id, u8 version, u8 type,
  374. size_t size, u8 const *data)
  375. {
  376. if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
  377. size >= 1) {
  378. vpd->product_id = data[0];
  379. } else if (id == VPD_BLOCK_NETWORK && version == 1 &&
  380. type != VPD_TYPE_INVALID) {
  381. if (size >= 6) {
  382. vpd->has |= VPD_HAS_MAC1;
  383. memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
  384. }
  385. if (size >= 12) {
  386. vpd->has |= VPD_HAS_MAC2;
  387. memcpy(vpd->mac2, data + 6, VPD_MAC_ADDRESS_LENGTH);
  388. }
  389. }
  390. return 0;
  391. }
  392. static void process_vpd(struct vpd_cache *vpd)
  393. {
  394. int fec_index = -1;
  395. int i210_index = -1;
  396. if (!vpd->is_read) {
  397. printf("VPD wasn't read");
  398. return;
  399. }
  400. switch (vpd->product_id) {
  401. case VPD_PRODUCT_B450:
  402. env_set("confidx", "1");
  403. i210_index = 0;
  404. fec_index = 1;
  405. break;
  406. case VPD_PRODUCT_B650:
  407. env_set("confidx", "2");
  408. i210_index = 0;
  409. fec_index = 1;
  410. break;
  411. case VPD_PRODUCT_B850:
  412. env_set("confidx", "3");
  413. i210_index = 1;
  414. fec_index = 2;
  415. break;
  416. }
  417. if (fec_index >= 0 && (vpd->has & VPD_HAS_MAC1))
  418. eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1);
  419. if (i210_index >= 0 && (vpd->has & VPD_HAS_MAC2))
  420. eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2);
  421. }
  422. int board_eth_init(bd_t *bis)
  423. {
  424. setup_iomux_enet();
  425. setup_pcie();
  426. e1000_initialize(bis);
  427. return cpu_eth_init(bis);
  428. }
  429. static iomux_v3_cfg_t const misc_pads[] = {
  430. MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
  431. MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NC_PAD_CTRL),
  432. MX6_PAD_EIM_CS0__GPIO2_IO23 | MUX_PAD_CTRL(NC_PAD_CTRL),
  433. MX6_PAD_EIM_CS1__GPIO2_IO24 | MUX_PAD_CTRL(NC_PAD_CTRL),
  434. MX6_PAD_EIM_OE__GPIO2_IO25 | MUX_PAD_CTRL(NC_PAD_CTRL),
  435. MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NC_PAD_CTRL),
  436. MX6_PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NC_PAD_CTRL),
  437. MX6_PAD_GPIO_9__WDOG1_B | MUX_PAD_CTRL(NC_PAD_CTRL),
  438. };
  439. #define SUS_S3_OUT IMX_GPIO_NR(4, 11)
  440. #define WIFI_EN IMX_GPIO_NR(6, 14)
  441. int board_early_init_f(void)
  442. {
  443. imx_iomux_v3_setup_multiple_pads(misc_pads,
  444. ARRAY_SIZE(misc_pads));
  445. setup_iomux_uart();
  446. #if defined(CONFIG_VIDEO_IPUV3)
  447. /* Set LDB clock to Video PLL */
  448. select_ldb_di_clock_source(MXC_PLL5_CLK);
  449. #endif
  450. return 0;
  451. }
  452. static void set_confidx(const struct vpd_cache* vpd)
  453. {
  454. switch (vpd->product_id) {
  455. case VPD_PRODUCT_B450:
  456. confidx = 1;
  457. break;
  458. case VPD_PRODUCT_B650:
  459. confidx = 2;
  460. break;
  461. case VPD_PRODUCT_B850:
  462. confidx = 3;
  463. break;
  464. }
  465. }
  466. int board_init(void)
  467. {
  468. setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  469. setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
  470. setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
  471. if (!read_vpd(&vpd, vpd_callback)) {
  472. vpd.is_read = true;
  473. set_confidx(&vpd);
  474. }
  475. gpio_request(SUS_S3_OUT, "sus_s3_out");
  476. gpio_direction_output(SUS_S3_OUT, 1);
  477. gpio_request(WIFI_EN, "wifi_en");
  478. gpio_direction_output(WIFI_EN, 1);
  479. #if defined(CONFIG_VIDEO_IPUV3)
  480. if (is_b850v3())
  481. setup_display_b850v3();
  482. else
  483. setup_display_bx50v3();
  484. gpio_request(LVDS_BACKLIGHT_GP, "lvds_backlight");
  485. gpio_direction_input(LVDS_BACKLIGHT_GP);
  486. #endif
  487. /* address of boot parameters */
  488. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  489. return 0;
  490. }
  491. #ifdef CONFIG_CMD_BMODE
  492. static const struct boot_mode board_boot_modes[] = {
  493. /* 4 bit bus width */
  494. {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  495. {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  496. {NULL, 0},
  497. };
  498. #endif
  499. void pmic_init(void)
  500. {
  501. #define I2C_PMIC 0x2
  502. #define DA9063_I2C_ADDR 0x58
  503. #define DA9063_REG_BCORE2_CFG 0x9D
  504. #define DA9063_REG_BCORE1_CFG 0x9E
  505. #define DA9063_REG_BPRO_CFG 0x9F
  506. #define DA9063_REG_BIO_CFG 0xA0
  507. #define DA9063_REG_BMEM_CFG 0xA1
  508. #define DA9063_REG_BPERI_CFG 0xA2
  509. #define DA9063_BUCK_MODE_MASK 0xC0
  510. #define DA9063_BUCK_MODE_MANUAL 0x00
  511. #define DA9063_BUCK_MODE_SLEEP 0x40
  512. #define DA9063_BUCK_MODE_SYNC 0x80
  513. #define DA9063_BUCK_MODE_AUTO 0xC0
  514. uchar val;
  515. i2c_set_bus_num(I2C_PMIC);
  516. i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
  517. val &= ~DA9063_BUCK_MODE_MASK;
  518. val |= DA9063_BUCK_MODE_SYNC;
  519. i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
  520. i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
  521. val &= ~DA9063_BUCK_MODE_MASK;
  522. val |= DA9063_BUCK_MODE_SYNC;
  523. i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
  524. i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
  525. val &= ~DA9063_BUCK_MODE_MASK;
  526. val |= DA9063_BUCK_MODE_SYNC;
  527. i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
  528. i2c_read(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
  529. val &= ~DA9063_BUCK_MODE_MASK;
  530. val |= DA9063_BUCK_MODE_SYNC;
  531. i2c_write(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
  532. i2c_read(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
  533. val &= ~DA9063_BUCK_MODE_MASK;
  534. val |= DA9063_BUCK_MODE_SYNC;
  535. i2c_write(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
  536. i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
  537. val &= ~DA9063_BUCK_MODE_MASK;
  538. val |= DA9063_BUCK_MODE_SYNC;
  539. i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
  540. }
  541. int board_late_init(void)
  542. {
  543. process_vpd(&vpd);
  544. #ifdef CONFIG_CMD_BMODE
  545. add_board_boot_modes(board_boot_modes);
  546. #endif
  547. if (is_b850v3())
  548. env_set("videoargs", "video=DP-1:1024x768@60 video=HDMI-A-1:1024x768@60");
  549. else
  550. env_set("videoargs", "video=LVDS-1:1024x768@65");
  551. /* board specific pmic init */
  552. pmic_init();
  553. check_time();
  554. return 0;
  555. }
  556. /*
  557. * Removes the 'eth[0-9]*addr' environment variable with the given index
  558. *
  559. * @param index [in] the index of the eth_device whose variable is to be removed
  560. */
  561. static void remove_ethaddr_env_var(int index)
  562. {
  563. char env_var_name[9];
  564. sprintf(env_var_name, index == 0 ? "ethaddr" : "eth%daddr", index);
  565. env_set(env_var_name, NULL);
  566. }
  567. int last_stage_init(void)
  568. {
  569. int i;
  570. /*
  571. * Remove first three ethaddr which may have been created by
  572. * function process_vpd().
  573. */
  574. for (i = 0; i < 3; ++i)
  575. remove_ethaddr_env_var(i);
  576. return 0;
  577. }
  578. int checkboard(void)
  579. {
  580. printf("BOARD: %s\n", CONFIG_BOARD_NAME);
  581. return 0;
  582. }
  583. #ifdef CONFIG_OF_BOARD_SETUP
  584. int ft_board_setup(void *blob, bd_t *bd)
  585. {
  586. fdt_setprop(blob, 0, "ge,boot-ver", version_string,
  587. strlen(version_string) + 1);
  588. return 0;
  589. }
  590. #endif
  591. static int do_backlight_enable(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  592. {
  593. #ifdef CONFIG_VIDEO_IPUV3
  594. /* We need at least 200ms between power on and backlight on
  595. * as per specifications from CHI MEI */
  596. mdelay(250);
  597. /* enable backlight PWM 1 */
  598. pwm_init(0, 0, 0);
  599. /* duty cycle 5000000ns, period: 5000000ns */
  600. pwm_config(0, 5000000, 5000000);
  601. /* Backlight Power */
  602. gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
  603. pwm_enable(0);
  604. #endif
  605. return 0;
  606. }
  607. U_BOOT_CMD(
  608. bx50_backlight_enable, 1, 1, do_backlight_enable,
  609. "enable Bx50 backlight",
  610. ""
  611. );