gw_ventana.c 36 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013 Gateworks Corporation
  4. *
  5. * Author: Tim Harvey <tharvey@gateworks.com>
  6. */
  7. #include <common.h>
  8. #include <asm/arch/clock.h>
  9. #include <asm/arch/crm_regs.h>
  10. #include <asm/arch/iomux.h>
  11. #include <asm/arch/mx6-pins.h>
  12. #include <asm/arch/mxc_hdmi.h>
  13. #include <asm/arch/sys_proto.h>
  14. #include <asm/gpio.h>
  15. #include <asm/mach-imx/boot_mode.h>
  16. #include <asm/mach-imx/sata.h>
  17. #include <asm/mach-imx/spi.h>
  18. #include <asm/mach-imx/video.h>
  19. #include <asm/io.h>
  20. #include <asm/setup.h>
  21. #include <dm.h>
  22. #include <dm/platform_data/serial_mxc.h>
  23. #include <env.h>
  24. #include <environment.h>
  25. #include <hwconfig.h>
  26. #include <i2c.h>
  27. #include <fdt_support.h>
  28. #include <fsl_esdhc_imx.h>
  29. #include <jffs2/load_kernel.h>
  30. #include <linux/ctype.h>
  31. #include <miiphy.h>
  32. #include <mtd_node.h>
  33. #include <netdev.h>
  34. #include <pci.h>
  35. #include <power/pmic.h>
  36. #include <power/ltc3676_pmic.h>
  37. #include <power/pfuze100_pmic.h>
  38. #include <fdt_support.h>
  39. #include <jffs2/load_kernel.h>
  40. #include <spi_flash.h>
  41. #include "gsc.h"
  42. #include "common.h"
  43. DECLARE_GLOBAL_DATA_PTR;
  44. /*
  45. * EEPROM board info struct populated by read_eeprom so that we only have to
  46. * read it once.
  47. */
  48. struct ventana_board_info ventana_info;
  49. static int board_type;
  50. /* ENET */
  51. static iomux_v3_cfg_t const enet_pads[] = {
  52. IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  53. IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  54. IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  55. IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  56. IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  57. IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  58. IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  59. IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
  60. MUX_PAD_CTRL(ENET_PAD_CTRL)),
  61. IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
  62. MUX_PAD_CTRL(ENET_PAD_CTRL)),
  63. IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  64. IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  65. IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  66. IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  67. IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  68. IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
  69. MUX_PAD_CTRL(ENET_PAD_CTRL)),
  70. /* PHY nRST */
  71. IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
  72. };
  73. #ifdef CONFIG_CMD_NAND
  74. static iomux_v3_cfg_t const nfc_pads[] = {
  75. IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
  76. IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
  77. IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  78. IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  79. IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  80. IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  81. IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  82. IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  83. IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  84. IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  85. IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  86. IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  87. IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  88. IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  89. IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  90. };
  91. static void setup_gpmi_nand(void)
  92. {
  93. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  94. /* config gpmi nand iomux */
  95. SETUP_IOMUX_PADS(nfc_pads);
  96. /* config gpmi and bch clock to 100 MHz */
  97. clrsetbits_le32(&mxc_ccm->cs2cdr,
  98. MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
  99. MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
  100. MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
  101. MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
  102. MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
  103. MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
  104. /* enable gpmi and bch clock gating */
  105. setbits_le32(&mxc_ccm->CCGR4,
  106. MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  107. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  108. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  109. MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  110. MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
  111. /* enable apbh clock gating */
  112. setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  113. }
  114. #endif
  115. static void setup_iomux_enet(int gpio)
  116. {
  117. SETUP_IOMUX_PADS(enet_pads);
  118. /* toggle PHY_RST# */
  119. gpio_request(gpio, "phy_rst#");
  120. gpio_direction_output(gpio, 0);
  121. mdelay(10);
  122. gpio_set_value(gpio, 1);
  123. mdelay(100);
  124. }
  125. #ifdef CONFIG_USB_EHCI_MX6
  126. static iomux_v3_cfg_t const usb_pads[] = {
  127. IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG),
  128. IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
  129. /* OTG PWR */
  130. IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | DIO_PAD_CFG),
  131. };
  132. int board_ehci_hcd_init(int port)
  133. {
  134. int gpio;
  135. SETUP_IOMUX_PADS(usb_pads);
  136. /* Reset USB HUB */
  137. switch (board_type) {
  138. case GW53xx:
  139. case GW552x:
  140. case GW5906:
  141. gpio = (IMX_GPIO_NR(1, 9));
  142. break;
  143. case GW54proto:
  144. case GW54xx:
  145. gpio = (IMX_GPIO_NR(1, 16));
  146. break;
  147. default:
  148. return 0;
  149. }
  150. /* request and toggle hub rst */
  151. gpio_request(gpio, "usb_hub_rst#");
  152. gpio_direction_output(gpio, 0);
  153. mdelay(2);
  154. gpio_set_value(gpio, 1);
  155. return 0;
  156. }
  157. int board_ehci_power(int port, int on)
  158. {
  159. /* enable OTG VBUS */
  160. if (!port && board_type < GW_UNKNOWN) {
  161. if (gpio_cfg[board_type].otgpwr_en)
  162. gpio_set_value(gpio_cfg[board_type].otgpwr_en, on);
  163. }
  164. return 0;
  165. }
  166. #endif /* CONFIG_USB_EHCI_MX6 */
  167. #ifdef CONFIG_MXC_SPI
  168. iomux_v3_cfg_t const ecspi1_pads[] = {
  169. /* SS1 */
  170. IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  171. IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  172. IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  173. IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  174. };
  175. int board_spi_cs_gpio(unsigned bus, unsigned cs)
  176. {
  177. return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
  178. }
  179. static void setup_spi(void)
  180. {
  181. gpio_request(IMX_GPIO_NR(3, 19), "spi_cs");
  182. gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
  183. SETUP_IOMUX_PADS(ecspi1_pads);
  184. }
  185. #endif
  186. /* configure eth0 PHY board-specific LED behavior */
  187. int board_phy_config(struct phy_device *phydev)
  188. {
  189. unsigned short val;
  190. /* Marvel 88E1510 */
  191. if (phydev->phy_id == 0x1410dd1) {
  192. /*
  193. * Page 3, Register 16: LED[2:0] Function Control Register
  194. * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
  195. * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
  196. */
  197. phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
  198. val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
  199. val &= 0xff00;
  200. val |= 0x0017;
  201. phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
  202. phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
  203. }
  204. /* TI DP83867 */
  205. else if (phydev->phy_id == 0x2000a231) {
  206. /* configure register 0x170 for ref CLKOUT */
  207. phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x001f);
  208. phy_write(phydev, MDIO_DEVAD_NONE, 14, 0x0170);
  209. phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x401f);
  210. val = phy_read(phydev, MDIO_DEVAD_NONE, 14);
  211. val &= ~0x1f00;
  212. val |= 0x0b00; /* chD tx clock*/
  213. phy_write(phydev, MDIO_DEVAD_NONE, 14, val);
  214. }
  215. if (phydev->drv->config)
  216. phydev->drv->config(phydev);
  217. return 0;
  218. }
  219. #ifdef CONFIG_MV88E61XX_SWITCH
  220. int mv88e61xx_hw_reset(struct phy_device *phydev)
  221. {
  222. struct mii_dev *bus = phydev->bus;
  223. /* GPIO[0] output, CLK125 */
  224. debug("enabling RGMII_REFCLK\n");
  225. bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
  226. 0x1a /*MV_SCRATCH_MISC*/,
  227. (1 << 15) | (0x62 /*MV_GPIO_DIR*/ << 8) | 0xfe);
  228. bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
  229. 0x1a /*MV_SCRATCH_MISC*/,
  230. (1 << 15) | (0x68 /*MV_GPIO01_CNTL*/ << 8) | 7);
  231. /* RGMII delay - Physical Control register bit[15:14] */
  232. debug("setting port%d RGMII rx/tx delay\n", CONFIG_MV88E61XX_CPU_PORT);
  233. /* forced 1000mbps full-duplex link */
  234. bus->write(bus, 0x10 + CONFIG_MV88E61XX_CPU_PORT, 0, 1, 0xc0fe);
  235. phydev->autoneg = AUTONEG_DISABLE;
  236. phydev->speed = SPEED_1000;
  237. phydev->duplex = DUPLEX_FULL;
  238. /* LED configuration: 7:4-green (8=Activity) 3:0 amber (8=Link) */
  239. bus->write(bus, 0x10, 0, 0x16, 0x8088);
  240. bus->write(bus, 0x11, 0, 0x16, 0x8088);
  241. bus->write(bus, 0x12, 0, 0x16, 0x8088);
  242. bus->write(bus, 0x13, 0, 0x16, 0x8088);
  243. return 0;
  244. }
  245. #endif // CONFIG_MV88E61XX_SWITCH
  246. int board_eth_init(bd_t *bis)
  247. {
  248. #ifdef CONFIG_FEC_MXC
  249. struct ventana_board_info *info = &ventana_info;
  250. if (test_bit(EECONFIG_ETH0, info->config)) {
  251. setup_iomux_enet(GP_PHY_RST);
  252. cpu_eth_init(bis);
  253. }
  254. #endif
  255. #ifdef CONFIG_E1000
  256. e1000_initialize(bis);
  257. #endif
  258. #ifdef CONFIG_CI_UDC
  259. /* For otg ethernet*/
  260. usb_eth_initialize(bis);
  261. #endif
  262. /* default to the first detected enet dev */
  263. if (!env_get("ethprime")) {
  264. struct eth_device *dev = eth_get_dev_by_index(0);
  265. if (dev) {
  266. env_set("ethprime", dev->name);
  267. printf("set ethprime to %s\n", env_get("ethprime"));
  268. }
  269. }
  270. return 0;
  271. }
  272. #if defined(CONFIG_VIDEO_IPUV3)
  273. static void enable_hdmi(struct display_info_t const *dev)
  274. {
  275. imx_enable_hdmi_phy();
  276. }
  277. static int detect_i2c(struct display_info_t const *dev)
  278. {
  279. return i2c_set_bus_num(dev->bus) == 0 &&
  280. i2c_probe(dev->addr) == 0;
  281. }
  282. static void enable_lvds(struct display_info_t const *dev)
  283. {
  284. struct iomuxc *iomux = (struct iomuxc *)
  285. IOMUXC_BASE_ADDR;
  286. /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
  287. u32 reg = readl(&iomux->gpr[2]);
  288. reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
  289. writel(reg, &iomux->gpr[2]);
  290. /* Enable Backlight */
  291. gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
  292. gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
  293. gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
  294. SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
  295. gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
  296. }
  297. struct display_info_t const displays[] = {{
  298. /* HDMI Output */
  299. .bus = -1,
  300. .addr = 0,
  301. .pixfmt = IPU_PIX_FMT_RGB24,
  302. .detect = detect_hdmi,
  303. .enable = enable_hdmi,
  304. .mode = {
  305. .name = "HDMI",
  306. .refresh = 60,
  307. .xres = 1024,
  308. .yres = 768,
  309. .pixclock = 15385,
  310. .left_margin = 220,
  311. .right_margin = 40,
  312. .upper_margin = 21,
  313. .lower_margin = 7,
  314. .hsync_len = 60,
  315. .vsync_len = 10,
  316. .sync = FB_SYNC_EXT,
  317. .vmode = FB_VMODE_NONINTERLACED
  318. } }, {
  319. /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
  320. .bus = 2,
  321. .addr = 0x4,
  322. .pixfmt = IPU_PIX_FMT_LVDS666,
  323. .detect = detect_i2c,
  324. .enable = enable_lvds,
  325. .mode = {
  326. .name = "Hannstar-XGA",
  327. .refresh = 60,
  328. .xres = 1024,
  329. .yres = 768,
  330. .pixclock = 15385,
  331. .left_margin = 220,
  332. .right_margin = 40,
  333. .upper_margin = 21,
  334. .lower_margin = 7,
  335. .hsync_len = 60,
  336. .vsync_len = 10,
  337. .sync = FB_SYNC_EXT,
  338. .vmode = FB_VMODE_NONINTERLACED
  339. } }, {
  340. /* DLC700JMG-T-4 */
  341. .bus = 2,
  342. .addr = 0x38,
  343. .detect = NULL,
  344. .enable = enable_lvds,
  345. .pixfmt = IPU_PIX_FMT_LVDS666,
  346. .mode = {
  347. .name = "DLC700JMGT4",
  348. .refresh = 60,
  349. .xres = 1024, /* 1024x600active pixels */
  350. .yres = 600,
  351. .pixclock = 15385, /* 64MHz */
  352. .left_margin = 220,
  353. .right_margin = 40,
  354. .upper_margin = 21,
  355. .lower_margin = 7,
  356. .hsync_len = 60,
  357. .vsync_len = 10,
  358. .sync = FB_SYNC_EXT,
  359. .vmode = FB_VMODE_NONINTERLACED
  360. } }, {
  361. /* DLC800FIG-T-3 */
  362. .bus = 2,
  363. .addr = 0x14,
  364. .detect = NULL,
  365. .enable = enable_lvds,
  366. .pixfmt = IPU_PIX_FMT_LVDS666,
  367. .mode = {
  368. .name = "DLC800FIGT3",
  369. .refresh = 60,
  370. .xres = 1024, /* 1024x768 active pixels */
  371. .yres = 768,
  372. .pixclock = 15385, /* 64MHz */
  373. .left_margin = 220,
  374. .right_margin = 40,
  375. .upper_margin = 21,
  376. .lower_margin = 7,
  377. .hsync_len = 60,
  378. .vsync_len = 10,
  379. .sync = FB_SYNC_EXT,
  380. .vmode = FB_VMODE_NONINTERLACED
  381. } }, {
  382. .bus = 2,
  383. .addr = 0x5d,
  384. .detect = detect_i2c,
  385. .enable = enable_lvds,
  386. .pixfmt = IPU_PIX_FMT_LVDS666,
  387. .mode = {
  388. .name = "Z101WX01",
  389. .refresh = 60,
  390. .xres = 1280,
  391. .yres = 800,
  392. .pixclock = 15385, /* 64MHz */
  393. .left_margin = 220,
  394. .right_margin = 40,
  395. .upper_margin = 21,
  396. .lower_margin = 7,
  397. .hsync_len = 60,
  398. .vsync_len = 10,
  399. .sync = FB_SYNC_EXT,
  400. .vmode = FB_VMODE_NONINTERLACED
  401. }
  402. },
  403. };
  404. size_t display_count = ARRAY_SIZE(displays);
  405. static void setup_display(void)
  406. {
  407. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  408. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  409. int reg;
  410. enable_ipu_clock();
  411. imx_setup_hdmi();
  412. /* Turn on LDB0,IPU,IPU DI0 clocks */
  413. reg = __raw_readl(&mxc_ccm->CCGR3);
  414. reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
  415. writel(reg, &mxc_ccm->CCGR3);
  416. /* set LDB0, LDB1 clk select to 011/011 */
  417. reg = readl(&mxc_ccm->cs2cdr);
  418. reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
  419. |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
  420. reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
  421. |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
  422. writel(reg, &mxc_ccm->cs2cdr);
  423. reg = readl(&mxc_ccm->cscmr2);
  424. reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
  425. writel(reg, &mxc_ccm->cscmr2);
  426. reg = readl(&mxc_ccm->chsccdr);
  427. reg |= (CHSCCDR_CLK_SEL_LDB_DI0
  428. <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  429. writel(reg, &mxc_ccm->chsccdr);
  430. reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
  431. |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
  432. |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
  433. |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
  434. |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
  435. |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
  436. |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
  437. |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
  438. |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
  439. writel(reg, &iomux->gpr[2]);
  440. reg = readl(&iomux->gpr[3]);
  441. reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
  442. | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
  443. <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
  444. writel(reg, &iomux->gpr[3]);
  445. /* LVDS Backlight GPIO on LVDS connector - output low */
  446. SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
  447. gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
  448. }
  449. #endif /* CONFIG_VIDEO_IPUV3 */
  450. /* setup board specific PMIC */
  451. int power_init_board(void)
  452. {
  453. setup_pmic();
  454. return 0;
  455. }
  456. #if defined(CONFIG_CMD_PCI)
  457. int imx6_pcie_toggle_reset(void)
  458. {
  459. if (board_type < GW_UNKNOWN) {
  460. uint pin = gpio_cfg[board_type].pcie_rst;
  461. gpio_request(pin, "pci_rst#");
  462. gpio_direction_output(pin, 0);
  463. mdelay(50);
  464. gpio_direction_output(pin, 1);
  465. }
  466. return 0;
  467. }
  468. /*
  469. * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
  470. * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
  471. * properly and assert reset for 100ms.
  472. */
  473. #define MAX_PCI_DEVS 32
  474. struct pci_dev {
  475. pci_dev_t devfn;
  476. unsigned short vendor;
  477. unsigned short device;
  478. unsigned short class;
  479. unsigned short busno; /* subbordinate busno */
  480. struct pci_dev *ppar;
  481. };
  482. struct pci_dev pci_devs[MAX_PCI_DEVS];
  483. int pci_devno;
  484. int pci_bridgeno;
  485. void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
  486. unsigned short vendor, unsigned short device,
  487. unsigned short class)
  488. {
  489. int i;
  490. u32 dw;
  491. struct pci_dev *pdev = &pci_devs[pci_devno++];
  492. debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
  493. PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
  494. /* store array of devs for later use in device-tree fixup */
  495. pdev->devfn = dev;
  496. pdev->vendor = vendor;
  497. pdev->device = device;
  498. pdev->class = class;
  499. pdev->ppar = NULL;
  500. if (class == PCI_CLASS_BRIDGE_PCI)
  501. pdev->busno = ++pci_bridgeno;
  502. else
  503. pdev->busno = 0;
  504. /* fixup RC - it should be 00:00.0 not 00:01.0 */
  505. if (PCI_BUS(dev) == 0)
  506. pdev->devfn = 0;
  507. /* find dev's parent */
  508. for (i = 0; i < pci_devno; i++) {
  509. if (pci_devs[i].busno == PCI_BUS(pdev->devfn)) {
  510. pdev->ppar = &pci_devs[i];
  511. break;
  512. }
  513. }
  514. /* assert downstream PERST# */
  515. if (vendor == PCI_VENDOR_ID_PLX &&
  516. (device & 0xfff0) == 0x8600 &&
  517. PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
  518. debug("configuring PLX 860X downstream PERST#\n");
  519. pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
  520. dw |= 0xaaa8; /* GPIO1-7 outputs */
  521. pci_hose_write_config_dword(hose, dev, 0x62c, dw);
  522. pci_hose_read_config_dword(hose, dev, 0x644, &dw);
  523. dw |= 0xfe; /* GPIO1-7 output high */
  524. pci_hose_write_config_dword(hose, dev, 0x644, dw);
  525. mdelay(100);
  526. }
  527. }
  528. #endif /* CONFIG_CMD_PCI */
  529. #ifdef CONFIG_SERIAL_TAG
  530. /*
  531. * called when setting up ATAGS before booting kernel
  532. * populate serialnum from the following (in order of priority):
  533. * serial# env var
  534. * eeprom
  535. */
  536. void get_board_serial(struct tag_serialnr *serialnr)
  537. {
  538. char *serial = env_get("serial#");
  539. if (serial) {
  540. serialnr->high = 0;
  541. serialnr->low = simple_strtoul(serial, NULL, 10);
  542. } else if (ventana_info.model[0]) {
  543. serialnr->high = 0;
  544. serialnr->low = ventana_info.serial;
  545. } else {
  546. serialnr->high = 0;
  547. serialnr->low = 0;
  548. }
  549. }
  550. #endif
  551. /*
  552. * Board Support
  553. */
  554. int board_early_init_f(void)
  555. {
  556. setup_iomux_uart();
  557. #if defined(CONFIG_VIDEO_IPUV3)
  558. setup_display();
  559. #endif
  560. return 0;
  561. }
  562. int dram_init(void)
  563. {
  564. gd->ram_size = imx_ddr_size();
  565. return 0;
  566. }
  567. int board_init(void)
  568. {
  569. struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  570. clrsetbits_le32(&iomuxc_regs->gpr[1],
  571. IOMUXC_GPR1_OTG_ID_MASK,
  572. IOMUXC_GPR1_OTG_ID_GPIO1);
  573. /* address of linux boot parameters */
  574. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  575. /* read Gateworks EEPROM into global struct (used later) */
  576. setup_ventana_i2c(0);
  577. board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
  578. #ifdef CONFIG_CMD_NAND
  579. if (gpio_cfg[board_type].nand)
  580. setup_gpmi_nand();
  581. #endif
  582. #ifdef CONFIG_MXC_SPI
  583. setup_spi();
  584. #endif
  585. setup_ventana_i2c(1);
  586. setup_ventana_i2c(2);
  587. #ifdef CONFIG_SATA
  588. setup_sata();
  589. #endif
  590. setup_iomux_gpio(board_type, &ventana_info);
  591. return 0;
  592. }
  593. #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
  594. /*
  595. * called during late init (after relocation and after board_init())
  596. * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
  597. * EEPROM read.
  598. */
  599. int checkboard(void)
  600. {
  601. struct ventana_board_info *info = &ventana_info;
  602. unsigned char buf[4];
  603. const char *p;
  604. int quiet; /* Quiet or minimal output mode */
  605. quiet = 0;
  606. p = env_get("quiet");
  607. if (p)
  608. quiet = simple_strtol(p, NULL, 10);
  609. else
  610. env_set("quiet", "0");
  611. puts("\nGateworks Corporation Copyright 2014\n");
  612. if (info->model[0]) {
  613. printf("Model: %s\n", info->model);
  614. printf("MFGDate: %02x-%02x-%02x%02x\n",
  615. info->mfgdate[0], info->mfgdate[1],
  616. info->mfgdate[2], info->mfgdate[3]);
  617. printf("Serial:%d\n", info->serial);
  618. } else {
  619. puts("Invalid EEPROM - board will not function fully\n");
  620. }
  621. if (quiet)
  622. return 0;
  623. /* Display GSC firmware revision/CRC/status */
  624. gsc_info(0);
  625. /* Display RTC */
  626. if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
  627. printf("RTC: %d\n",
  628. buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
  629. }
  630. return 0;
  631. }
  632. #endif
  633. #ifdef CONFIG_CMD_BMODE
  634. /*
  635. * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
  636. * see Table 8-11 and Table 5-9
  637. * BOOT_CFG1[7] = 1 (boot from NAND)
  638. * BOOT_CFG1[5] = 0 - raw NAND
  639. * BOOT_CFG1[4] = 0 - default pad settings
  640. * BOOT_CFG1[3:2] = 00 - devices = 1
  641. * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
  642. * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
  643. * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
  644. * BOOT_CFG2[0] = 0 - Reset time 12ms
  645. */
  646. static const struct boot_mode board_boot_modes[] = {
  647. /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
  648. { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
  649. { "emmc2", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00) }, /* GW5600 */
  650. { "emmc3", MAKE_CFGVAL(0x60, 0x50, 0x00, 0x00) }, /* GW5903/4/5 */
  651. { NULL, 0 },
  652. };
  653. #endif
  654. /* late init */
  655. int misc_init_r(void)
  656. {
  657. struct ventana_board_info *info = &ventana_info;
  658. char buf[256];
  659. int i;
  660. /* set env vars based on EEPROM data */
  661. if (ventana_info.model[0]) {
  662. char str[16], fdt[36];
  663. char *p;
  664. const char *cputype = "";
  665. /*
  666. * FDT name will be prefixed with CPU type. Three versions
  667. * will be created each increasingly generic and bootloader
  668. * env scripts will try loading each from most specific to
  669. * least.
  670. */
  671. if (is_cpu_type(MXC_CPU_MX6Q) ||
  672. is_cpu_type(MXC_CPU_MX6D))
  673. cputype = "imx6q";
  674. else if (is_cpu_type(MXC_CPU_MX6DL) ||
  675. is_cpu_type(MXC_CPU_MX6SOLO))
  676. cputype = "imx6dl";
  677. env_set("soctype", cputype);
  678. if (8 << (ventana_info.nand_flash_size-1) >= 2048)
  679. env_set("flash_layout", "large");
  680. else
  681. env_set("flash_layout", "normal");
  682. memset(str, 0, sizeof(str));
  683. for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
  684. str[i] = tolower(info->model[i]);
  685. env_set("model", str);
  686. if (!env_get("fdt_file")) {
  687. sprintf(fdt, "%s-%s.dtb", cputype, str);
  688. env_set("fdt_file", fdt);
  689. }
  690. p = strchr(str, '-');
  691. if (p) {
  692. *p++ = 0;
  693. env_set("model_base", str);
  694. sprintf(fdt, "%s-%s.dtb", cputype, str);
  695. env_set("fdt_file1", fdt);
  696. if (board_type != GW551x &&
  697. board_type != GW552x &&
  698. board_type != GW553x &&
  699. board_type != GW560x)
  700. str[4] = 'x';
  701. str[5] = 'x';
  702. str[6] = 0;
  703. sprintf(fdt, "%s-%s.dtb", cputype, str);
  704. env_set("fdt_file2", fdt);
  705. }
  706. /* initialize env from EEPROM */
  707. if (test_bit(EECONFIG_ETH0, info->config) &&
  708. !env_get("ethaddr")) {
  709. eth_env_set_enetaddr("ethaddr", info->mac0);
  710. }
  711. if (test_bit(EECONFIG_ETH1, info->config) &&
  712. !env_get("eth1addr")) {
  713. eth_env_set_enetaddr("eth1addr", info->mac1);
  714. }
  715. /* board serial-number */
  716. sprintf(str, "%6d", info->serial);
  717. env_set("serial#", str);
  718. /* memory MB */
  719. sprintf(str, "%d", (int) (gd->ram_size >> 20));
  720. env_set("mem_mb", str);
  721. }
  722. /* Set a non-initialized hwconfig based on board configuration */
  723. if (!strcmp(env_get("hwconfig"), "_UNKNOWN_")) {
  724. buf[0] = 0;
  725. if (gpio_cfg[board_type].rs232_en)
  726. strcat(buf, "rs232;");
  727. for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
  728. char buf1[32];
  729. sprintf(buf1, "dio%d:mode=gpio;", i);
  730. if (strlen(buf) + strlen(buf1) < sizeof(buf))
  731. strcat(buf, buf1);
  732. }
  733. env_set("hwconfig", buf);
  734. }
  735. /* setup baseboard specific GPIO based on board and env */
  736. setup_board_gpio(board_type, info);
  737. #ifdef CONFIG_CMD_BMODE
  738. add_board_boot_modes(board_boot_modes);
  739. #endif
  740. /* disable boot watchdog */
  741. gsc_boot_wd_disable();
  742. return 0;
  743. }
  744. #ifdef CONFIG_OF_BOARD_SETUP
  745. static int ft_sethdmiinfmt(void *blob, char *mode)
  746. {
  747. int off;
  748. if (!mode)
  749. return -EINVAL;
  750. off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x");
  751. if (off < 0)
  752. return off;
  753. if (0 == strcasecmp(mode, "yuv422bt656")) {
  754. u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00,
  755. 0x00, 0x00, 0x00 };
  756. mode = "422_ccir";
  757. fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
  758. fdt_setprop_u32(blob, off, "vidout_trc", 1);
  759. fdt_setprop_u32(blob, off, "vidout_blc", 1);
  760. fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
  761. printf(" set HDMI input mode to %s\n", mode);
  762. } else if (0 == strcasecmp(mode, "yuv422smp")) {
  763. u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00,
  764. 0x82, 0x81, 0x00 };
  765. mode = "422_smp";
  766. fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
  767. fdt_setprop_u32(blob, off, "vidout_trc", 0);
  768. fdt_setprop_u32(blob, off, "vidout_blc", 0);
  769. fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
  770. printf(" set HDMI input mode to %s\n", mode);
  771. } else {
  772. return -EINVAL;
  773. }
  774. return 0;
  775. }
  776. #if defined(CONFIG_CMD_PCI)
  777. #define PCI_ID(x) ( \
  778. (PCI_BUS(x->devfn)<<16)| \
  779. (PCI_DEV(x->devfn)<<11)| \
  780. (PCI_FUNC(x->devfn)<<8) \
  781. )
  782. int fdt_add_pci_node(void *blob, int par, struct pci_dev *dev)
  783. {
  784. uint32_t reg[5];
  785. char node[32];
  786. int np;
  787. sprintf(node, "pcie@%d,%d,%d", PCI_BUS(dev->devfn),
  788. PCI_DEV(dev->devfn), PCI_FUNC(dev->devfn));
  789. np = fdt_subnode_offset(blob, par, node);
  790. if (np >= 0)
  791. return np;
  792. np = fdt_add_subnode(blob, par, node);
  793. if (np < 0) {
  794. printf(" %s failed: no space\n", __func__);
  795. return np;
  796. }
  797. memset(reg, 0, sizeof(reg));
  798. reg[0] = cpu_to_fdt32(PCI_ID(dev));
  799. fdt_setprop(blob, np, "reg", reg, sizeof(reg));
  800. return np;
  801. }
  802. /* build a path of nested PCI devs for all bridges passed through */
  803. int fdt_add_pci_path(void *blob, struct pci_dev *dev)
  804. {
  805. struct pci_dev *bridges[MAX_PCI_DEVS];
  806. int k, np;
  807. /* build list of parents */
  808. np = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
  809. if (np < 0)
  810. return np;
  811. k = 0;
  812. while (dev) {
  813. bridges[k++] = dev;
  814. dev = dev->ppar;
  815. };
  816. /* now add them the to DT in reverse order */
  817. while (k--) {
  818. np = fdt_add_pci_node(blob, np, bridges[k]);
  819. if (np < 0)
  820. break;
  821. }
  822. return np;
  823. }
  824. /*
  825. * The GW16082 has a hardware errata errata such that it's
  826. * INTA/B/C/D are mis-mapped to its four slots (slot12-15). Because
  827. * of this normal PCI interrupt swizzling will not work so we will
  828. * provide an irq-map via device-tree.
  829. */
  830. int fdt_fixup_gw16082(void *blob, int np, struct pci_dev *dev)
  831. {
  832. int len;
  833. int host;
  834. uint32_t imap_new[8*4*4];
  835. const uint32_t *imap;
  836. uint32_t irq[4];
  837. uint32_t reg[4];
  838. int i;
  839. /* build irq-map based on host controllers map */
  840. host = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
  841. if (host < 0) {
  842. printf(" %s failed: missing host\n", __func__);
  843. return host;
  844. }
  845. /* use interrupt data from root complex's node */
  846. imap = fdt_getprop(blob, host, "interrupt-map", &len);
  847. if (!imap || len != 128) {
  848. printf(" %s failed: invalid interrupt-map\n",
  849. __func__);
  850. return -FDT_ERR_NOTFOUND;
  851. }
  852. /* obtain irq's of host controller in pin order */
  853. for (i = 0; i < 4; i++)
  854. irq[(fdt32_to_cpu(imap[(i*8)+3])-1)%4] = imap[(i*8)+6];
  855. /*
  856. * determine number of swizzles necessary:
  857. * For each bridge we pass through we need to swizzle
  858. * the number of the slot we are on.
  859. */
  860. struct pci_dev *d;
  861. int b;
  862. b = 0;
  863. d = dev->ppar;
  864. while(d && d->ppar) {
  865. b += PCI_DEV(d->devfn);
  866. d = d->ppar;
  867. }
  868. /* create new irq mappings for slots12-15
  869. * <skt> <idsel> <slot> <skt-inta> <skt-intb>
  870. * J3 AD28 12 INTD INTA
  871. * J4 AD29 13 INTC INTD
  872. * J5 AD30 14 INTB INTC
  873. * J2 AD31 15 INTA INTB
  874. */
  875. for (i = 0; i < 4; i++) {
  876. /* addr matches bus:dev:func */
  877. u32 addr = dev->busno << 16 | (12+i) << 11;
  878. /* default cells from root complex */
  879. memcpy(&imap_new[i*32], imap, 128);
  880. /* first cell is PCI device address (BDF) */
  881. imap_new[(i*32)+(0*8)+0] = cpu_to_fdt32(addr);
  882. imap_new[(i*32)+(1*8)+0] = cpu_to_fdt32(addr);
  883. imap_new[(i*32)+(2*8)+0] = cpu_to_fdt32(addr);
  884. imap_new[(i*32)+(3*8)+0] = cpu_to_fdt32(addr);
  885. /* third cell is pin */
  886. imap_new[(i*32)+(0*8)+3] = cpu_to_fdt32(1);
  887. imap_new[(i*32)+(1*8)+3] = cpu_to_fdt32(2);
  888. imap_new[(i*32)+(2*8)+3] = cpu_to_fdt32(3);
  889. imap_new[(i*32)+(3*8)+3] = cpu_to_fdt32(4);
  890. /* sixth cell is relative interrupt */
  891. imap_new[(i*32)+(0*8)+6] = irq[(15-(12+i)+b+0)%4];
  892. imap_new[(i*32)+(1*8)+6] = irq[(15-(12+i)+b+1)%4];
  893. imap_new[(i*32)+(2*8)+6] = irq[(15-(12+i)+b+2)%4];
  894. imap_new[(i*32)+(3*8)+6] = irq[(15-(12+i)+b+3)%4];
  895. }
  896. fdt_setprop(blob, np, "interrupt-map", imap_new,
  897. sizeof(imap_new));
  898. reg[0] = cpu_to_fdt32(0xfff00);
  899. reg[1] = 0;
  900. reg[2] = 0;
  901. reg[3] = cpu_to_fdt32(0x7);
  902. fdt_setprop(blob, np, "interrupt-map-mask", reg, sizeof(reg));
  903. fdt_setprop_cell(blob, np, "#interrupt-cells", 1);
  904. fdt_setprop_string(blob, np, "device_type", "pci");
  905. fdt_setprop_cell(blob, np, "#address-cells", 3);
  906. fdt_setprop_cell(blob, np, "#size-cells", 2);
  907. printf(" Added custom interrupt-map for GW16082\n");
  908. return 0;
  909. }
  910. /* The sky2 GigE MAC obtains it's MAC addr from device-tree by default */
  911. int fdt_fixup_sky2(void *blob, int np, struct pci_dev *dev)
  912. {
  913. char *tmp, *end;
  914. char mac[16];
  915. unsigned char mac_addr[6];
  916. int j;
  917. sprintf(mac, "eth1addr");
  918. tmp = env_get(mac);
  919. if (tmp) {
  920. for (j = 0; j < 6; j++) {
  921. mac_addr[j] = tmp ?
  922. simple_strtoul(tmp, &end,16) : 0;
  923. if (tmp)
  924. tmp = (*end) ? end+1 : end;
  925. }
  926. fdt_setprop(blob, np, "local-mac-address", mac_addr,
  927. sizeof(mac_addr));
  928. printf(" Added mac addr for eth1\n");
  929. return 0;
  930. }
  931. return -1;
  932. }
  933. /*
  934. * PCI DT nodes must be nested therefore if we need to apply a DT fixup
  935. * we will walk the PCI bus and add bridge nodes up to the device receiving
  936. * the fixup.
  937. */
  938. void ft_board_pci_fixup(void *blob, bd_t *bd)
  939. {
  940. int i, np;
  941. struct pci_dev *dev;
  942. for (i = 0; i < pci_devno; i++) {
  943. dev = &pci_devs[i];
  944. /*
  945. * The GW16082 consists of a TI XIO2001 PCIe-to-PCI bridge and
  946. * an EEPROM at i2c1-0x50.
  947. */
  948. if ((dev->vendor == PCI_VENDOR_ID_TI) &&
  949. (dev->device == 0x8240) &&
  950. (i2c_set_bus_num(1) == 0) &&
  951. (i2c_probe(0x50) == 0))
  952. {
  953. np = fdt_add_pci_path(blob, dev);
  954. if (np > 0)
  955. fdt_fixup_gw16082(blob, np, dev);
  956. }
  957. /* ethernet1 mac address */
  958. else if ((dev->vendor == PCI_VENDOR_ID_MARVELL) &&
  959. (dev->device == 0x4380))
  960. {
  961. np = fdt_add_pci_path(blob, dev);
  962. if (np > 0)
  963. fdt_fixup_sky2(blob, np, dev);
  964. }
  965. }
  966. }
  967. #endif /* if defined(CONFIG_CMD_PCI) */
  968. void ft_board_wdog_fixup(void *blob, phys_addr_t addr)
  969. {
  970. int off = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt", addr);
  971. if (off) {
  972. fdt_delprop(blob, off, "ext-reset-output");
  973. fdt_delprop(blob, off, "fsl,ext-reset-output");
  974. }
  975. }
  976. /*
  977. * called prior to booting kernel or by 'fdt boardsetup' command
  978. *
  979. * unless 'fdt_noauto' env var is set we will update the following in the DTB:
  980. * - mtd partitions based on mtdparts/mtdids env
  981. * - system-serial (board serial num from EEPROM)
  982. * - board (full model from EEPROM)
  983. * - peripherals removed from DTB if not loaded on board (per EEPROM config)
  984. */
  985. #define WDOG1_ADDR 0x20bc000
  986. #define WDOG2_ADDR 0x20c0000
  987. #define GPIO3_ADDR 0x20a4000
  988. #define USDHC3_ADDR 0x2198000
  989. #define PWM0_ADDR 0x2080000
  990. int ft_board_setup(void *blob, bd_t *bd)
  991. {
  992. struct ventana_board_info *info = &ventana_info;
  993. struct ventana_eeprom_config *cfg;
  994. static const struct node_info nodes[] = {
  995. { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */
  996. { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
  997. };
  998. const char *model = env_get("model");
  999. const char *display = env_get("display");
  1000. int i;
  1001. char rev = 0;
  1002. /* determine board revision */
  1003. for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
  1004. if (ventana_info.model[i] >= 'A') {
  1005. rev = ventana_info.model[i];
  1006. break;
  1007. }
  1008. }
  1009. if (env_get("fdt_noauto")) {
  1010. puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
  1011. return 0;
  1012. }
  1013. if (test_bit(EECONFIG_NAND, info->config)) {
  1014. /* Update partition nodes using info from mtdparts env var */
  1015. puts(" Updating MTD partitions...\n");
  1016. fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
  1017. }
  1018. /* Update display timings from display env var */
  1019. if (display) {
  1020. if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
  1021. display) >= 0)
  1022. printf(" Set display timings for %s...\n", display);
  1023. }
  1024. printf(" Adjusting FDT per EEPROM for %s...\n", model);
  1025. /* board serial number */
  1026. fdt_setprop(blob, 0, "system-serial", env_get("serial#"),
  1027. strlen(env_get("serial#")) + 1);
  1028. /* board (model contains model from device-tree) */
  1029. fdt_setprop(blob, 0, "board", info->model,
  1030. strlen((const char *)info->model) + 1);
  1031. /* set desired digital video capture format */
  1032. ft_sethdmiinfmt(blob, env_get("hdmiinfmt"));
  1033. /*
  1034. * Board model specific fixups
  1035. */
  1036. switch (board_type) {
  1037. case GW51xx:
  1038. /*
  1039. * disable wdog node for GW51xx-A/B to work around
  1040. * errata causing wdog timer to be unreliable.
  1041. */
  1042. if (rev >= 'A' && rev < 'C') {
  1043. i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt",
  1044. WDOG1_ADDR);
  1045. if (i)
  1046. fdt_status_disabled(blob, i);
  1047. }
  1048. /* GW51xx-E adds WDOG1_B external reset */
  1049. if (rev < 'E')
  1050. ft_board_wdog_fixup(blob, WDOG1_ADDR);
  1051. break;
  1052. case GW52xx:
  1053. /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
  1054. if (info->model[4] == '2') {
  1055. u32 handle = 0;
  1056. u32 *range = NULL;
  1057. i = fdt_node_offset_by_compatible(blob, -1,
  1058. "fsl,imx6q-pcie");
  1059. if (i)
  1060. range = (u32 *)fdt_getprop(blob, i,
  1061. "reset-gpio", NULL);
  1062. if (range) {
  1063. i = fdt_node_offset_by_compat_reg(blob,
  1064. "fsl,imx6q-gpio", GPIO3_ADDR);
  1065. if (i)
  1066. handle = fdt_get_phandle(blob, i);
  1067. if (handle) {
  1068. range[0] = cpu_to_fdt32(handle);
  1069. range[1] = cpu_to_fdt32(23);
  1070. }
  1071. }
  1072. /* these have broken usd_vsel */
  1073. if (strstr((const char *)info->model, "SP318-B") ||
  1074. strstr((const char *)info->model, "SP331-B"))
  1075. gpio_cfg[board_type].usd_vsel = 0;
  1076. /* GW522x-B adds WDOG1_B external reset */
  1077. if (rev < 'B')
  1078. ft_board_wdog_fixup(blob, WDOG1_ADDR);
  1079. }
  1080. /* GW520x-E adds WDOG1_B external reset */
  1081. else if (info->model[4] == '0' && rev < 'E')
  1082. ft_board_wdog_fixup(blob, WDOG1_ADDR);
  1083. break;
  1084. case GW53xx:
  1085. /* GW53xx-E adds WDOG1_B external reset */
  1086. if (rev < 'E')
  1087. ft_board_wdog_fixup(blob, WDOG1_ADDR);
  1088. break;
  1089. case GW54xx:
  1090. /*
  1091. * disable serial2 node for GW54xx for compatibility with older
  1092. * 3.10.x kernel that improperly had this node enabled in the DT
  1093. */
  1094. fdt_set_status_by_alias(blob, "serial2", FDT_STATUS_DISABLED,
  1095. 0);
  1096. /* GW54xx-E adds WDOG2_B external reset */
  1097. if (rev < 'E')
  1098. ft_board_wdog_fixup(blob, WDOG2_ADDR);
  1099. break;
  1100. case GW551x:
  1101. /*
  1102. * isolate CSI0_DATA_EN for GW551x-A to work around errata
  1103. * causing non functional digital video in (it is not hooked up)
  1104. */
  1105. if (rev == 'A') {
  1106. u32 *range = NULL;
  1107. int len;
  1108. const u32 *handle = NULL;
  1109. i = fdt_node_offset_by_compatible(blob, -1,
  1110. "fsl,imx-tda1997x-video");
  1111. if (i)
  1112. handle = fdt_getprop(blob, i, "pinctrl-0",
  1113. NULL);
  1114. if (handle)
  1115. i = fdt_node_offset_by_phandle(blob,
  1116. fdt32_to_cpu(*handle));
  1117. if (i)
  1118. range = (u32 *)fdt_getprop(blob, i, "fsl,pins",
  1119. &len);
  1120. if (range) {
  1121. len /= sizeof(u32);
  1122. for (i = 0; i < len; i += 6) {
  1123. u32 mux_reg = fdt32_to_cpu(range[i+0]);
  1124. u32 conf_reg = fdt32_to_cpu(range[i+1]);
  1125. /* mux PAD_CSI0_DATA_EN to GPIO */
  1126. if (is_cpu_type(MXC_CPU_MX6Q) &&
  1127. mux_reg == 0x260 &&
  1128. conf_reg == 0x630)
  1129. range[i+3] = cpu_to_fdt32(0x5);
  1130. else if (!is_cpu_type(MXC_CPU_MX6Q) &&
  1131. mux_reg == 0x08c &&
  1132. conf_reg == 0x3a0)
  1133. range[i+3] = cpu_to_fdt32(0x5);
  1134. }
  1135. fdt_setprop_inplace(blob, i, "fsl,pins", range,
  1136. len);
  1137. }
  1138. /* set BT656 video format */
  1139. ft_sethdmiinfmt(blob, "yuv422bt656");
  1140. }
  1141. /* GW551x-C adds WDOG1_B external reset */
  1142. if (rev < 'C')
  1143. ft_board_wdog_fixup(blob, WDOG1_ADDR);
  1144. break;
  1145. case GW5901:
  1146. case GW5902:
  1147. /* GW5901/GW5901 revB adds WDOG1_B as an external reset */
  1148. if (rev < 'B')
  1149. ft_board_wdog_fixup(blob, WDOG1_ADDR);
  1150. break;
  1151. }
  1152. /* Configure DIO */
  1153. for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
  1154. struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i];
  1155. char arg[10];
  1156. sprintf(arg, "dio%d", i);
  1157. if (!hwconfig(arg))
  1158. continue;
  1159. if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param)
  1160. {
  1161. phys_addr_t addr;
  1162. int off;
  1163. printf(" Enabling pwm%d for DIO%d\n",
  1164. cfg->pwm_param, i);
  1165. addr = PWM0_ADDR + (0x4000 * (cfg->pwm_param - 1));
  1166. off = fdt_node_offset_by_compat_reg(blob,
  1167. "fsl,imx6q-pwm",
  1168. addr);
  1169. if (off)
  1170. fdt_status_okay(blob, off);
  1171. }
  1172. }
  1173. /* remove no-1-8-v if UHS-I support is present */
  1174. if (gpio_cfg[board_type].usd_vsel) {
  1175. debug("Enabling UHS-I support\n");
  1176. i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-usdhc",
  1177. USDHC3_ADDR);
  1178. if (i)
  1179. fdt_delprop(blob, i, "no-1-8-v");
  1180. }
  1181. #if defined(CONFIG_CMD_PCI)
  1182. if (!env_get("nopcifixup"))
  1183. ft_board_pci_fixup(blob, bd);
  1184. #endif
  1185. /*
  1186. * Peripheral Config:
  1187. * remove nodes by alias path if EEPROM config tells us the
  1188. * peripheral is not loaded on the board.
  1189. */
  1190. if (env_get("fdt_noconfig")) {
  1191. puts(" Skiping periperhal config (fdt_noconfig defined)\n");
  1192. return 0;
  1193. }
  1194. cfg = econfig;
  1195. while (cfg->name) {
  1196. if (!test_bit(cfg->bit, info->config)) {
  1197. fdt_del_node_and_alias(blob, cfg->dtalias ?
  1198. cfg->dtalias : cfg->name);
  1199. }
  1200. cfg++;
  1201. }
  1202. return 0;
  1203. }
  1204. #endif /* CONFIG_OF_BOARD_SETUP */
  1205. static struct mxc_serial_platdata ventana_mxc_serial_plat = {
  1206. .reg = (struct mxc_uart *)UART2_BASE,
  1207. };
  1208. U_BOOT_DEVICE(ventana_serial) = {
  1209. .name = "serial_mxc",
  1210. .platdata = &ventana_mxc_serial_plat,
  1211. };