mx6ul_14x14_evk.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Freescale Semiconductor, Inc.
  4. */
  5. #include <asm/arch/clock.h>
  6. #include <asm/arch/iomux.h>
  7. #include <asm/arch/imx-regs.h>
  8. #include <asm/arch/crm_regs.h>
  9. #include <asm/arch/mx6ul_pins.h>
  10. #include <asm/arch/mx6-pins.h>
  11. #include <asm/arch/sys_proto.h>
  12. #include <asm/gpio.h>
  13. #include <asm/mach-imx/iomux-v3.h>
  14. #include <asm/mach-imx/boot_mode.h>
  15. #include <asm/mach-imx/mxc_i2c.h>
  16. #include <asm/io.h>
  17. #include <common.h>
  18. #include <env.h>
  19. #include <fsl_esdhc_imx.h>
  20. #include <i2c.h>
  21. #include <miiphy.h>
  22. #include <linux/sizes.h>
  23. #include <mmc.h>
  24. #include <netdev.h>
  25. #include <power/pmic.h>
  26. #include <power/pfuze3000_pmic.h>
  27. #include "../common/pfuze.h"
  28. #include <usb.h>
  29. #include <usb/ehci-ci.h>
  30. DECLARE_GLOBAL_DATA_PTR;
  31. #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  32. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  33. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  34. #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  35. PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
  36. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  37. #define USDHC_DAT3_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  38. PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \
  39. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  40. #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  41. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  42. PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  43. PAD_CTL_ODE)
  44. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  45. PAD_CTL_SPEED_HIGH | \
  46. PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
  47. #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  48. PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
  49. #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  50. PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
  51. #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  52. #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  53. PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
  54. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  55. #ifdef CONFIG_DM_PMIC
  56. int power_init_board(void)
  57. {
  58. struct udevice *dev;
  59. int ret, dev_id, rev_id;
  60. unsigned int reg;
  61. ret = pmic_get("pfuze3000", &dev);
  62. if (ret == -ENODEV)
  63. return 0;
  64. if (ret != 0)
  65. return ret;
  66. dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
  67. rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
  68. printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
  69. /* disable Low Power Mode during standby mode */
  70. reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL);
  71. reg |= 0x1;
  72. pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg);
  73. /* SW1B step ramp up time from 2us to 4us/25mV */
  74. pmic_reg_write(dev, PFUZE3000_SW1BCONF, 0x40);
  75. /* SW1B mode to APS/PFM */
  76. pmic_reg_write(dev, PFUZE3000_SW1BMODE, 0xc);
  77. /* SW1B standby voltage set to 0.975V */
  78. pmic_reg_write(dev, PFUZE3000_SW1BSTBY, 0xb);
  79. return 0;
  80. }
  81. #endif
  82. int dram_init(void)
  83. {
  84. gd->ram_size = imx_ddr_size();
  85. return 0;
  86. }
  87. static iomux_v3_cfg_t const uart1_pads[] = {
  88. MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  89. MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  90. };
  91. #ifndef CONFIG_SPL_BUILD
  92. static iomux_v3_cfg_t const usdhc1_pads[] = {
  93. MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  94. MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  95. MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  96. MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  97. MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  98. MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  99. /* VSELECT */
  100. MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  101. /* CD */
  102. MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
  103. /* RST_B */
  104. MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
  105. };
  106. #endif
  107. /*
  108. * mx6ul_14x14_evk board default supports sd card. If want to use
  109. * EMMC, need to do board rework for sd2.
  110. * Introduce CONFIG_MX6UL_14X14_EVK_EMMC_REWORK, if sd2 reworked to support
  111. * emmc, need to define this macro.
  112. */
  113. #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
  114. static iomux_v3_cfg_t const usdhc2_emmc_pads[] = {
  115. MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  116. MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  117. MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  118. MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  119. MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  120. MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  121. MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  122. MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  123. MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  124. MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  125. /*
  126. * RST_B
  127. */
  128. MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
  129. };
  130. #else
  131. static iomux_v3_cfg_t const usdhc2_pads[] = {
  132. MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  133. MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  134. MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  135. MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  136. MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  137. MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  138. };
  139. /*
  140. * The evk board uses DAT3 to detect CD card plugin,
  141. * in u-boot we mux the pin to GPIO when doing board_mmc_getcd.
  142. */
  143. static iomux_v3_cfg_t const usdhc2_cd_pad =
  144. MX6_PAD_NAND_DATA03__GPIO4_IO05 | MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL);
  145. static iomux_v3_cfg_t const usdhc2_dat3_pad =
  146. MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
  147. MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL);
  148. #endif
  149. static void setup_iomux_uart(void)
  150. {
  151. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  152. }
  153. #ifdef CONFIG_FSL_QSPI
  154. static int board_qspi_init(void)
  155. {
  156. /* Set the clock */
  157. enable_qspi_clk(0);
  158. return 0;
  159. }
  160. #endif
  161. #ifdef CONFIG_FSL_ESDHC_IMX
  162. static struct fsl_esdhc_cfg usdhc_cfg[2] = {
  163. {USDHC1_BASE_ADDR, 0, 4},
  164. #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
  165. {USDHC2_BASE_ADDR, 0, 8},
  166. #else
  167. {USDHC2_BASE_ADDR, 0, 4},
  168. #endif
  169. };
  170. #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
  171. #define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9)
  172. #define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5)
  173. #define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10)
  174. int board_mmc_getcd(struct mmc *mmc)
  175. {
  176. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  177. int ret = 0;
  178. switch (cfg->esdhc_base) {
  179. case USDHC1_BASE_ADDR:
  180. ret = !gpio_get_value(USDHC1_CD_GPIO);
  181. break;
  182. case USDHC2_BASE_ADDR:
  183. #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
  184. ret = 1;
  185. #else
  186. imx_iomux_v3_setup_pad(usdhc2_cd_pad);
  187. gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
  188. gpio_direction_input(USDHC2_CD_GPIO);
  189. /*
  190. * Since it is the DAT3 pin, this pin is pulled to
  191. * low voltage if no card
  192. */
  193. ret = gpio_get_value(USDHC2_CD_GPIO);
  194. imx_iomux_v3_setup_pad(usdhc2_dat3_pad);
  195. #endif
  196. break;
  197. }
  198. return ret;
  199. }
  200. int board_mmc_init(bd_t *bis)
  201. {
  202. #ifdef CONFIG_SPL_BUILD
  203. #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
  204. imx_iomux_v3_setup_multiple_pads(usdhc2_emmc_pads,
  205. ARRAY_SIZE(usdhc2_emmc_pads));
  206. #else
  207. imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
  208. #endif
  209. gpio_direction_output(USDHC2_PWR_GPIO, 0);
  210. udelay(500);
  211. gpio_direction_output(USDHC2_PWR_GPIO, 1);
  212. usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  213. return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
  214. #else
  215. int i, ret;
  216. /*
  217. * According to the board_mmc_init() the following map is done:
  218. * (U-Boot device node) (Physical Port)
  219. * mmc0 USDHC1
  220. * mmc1 USDHC2
  221. */
  222. for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  223. switch (i) {
  224. case 0:
  225. imx_iomux_v3_setup_multiple_pads(
  226. usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
  227. gpio_request(USDHC1_CD_GPIO, "usdhc1 cd");
  228. gpio_direction_input(USDHC1_CD_GPIO);
  229. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  230. gpio_direction_output(USDHC1_PWR_GPIO, 0);
  231. udelay(500);
  232. gpio_direction_output(USDHC1_PWR_GPIO, 1);
  233. break;
  234. case 1:
  235. #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
  236. imx_iomux_v3_setup_multiple_pads(
  237. usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads));
  238. #else
  239. imx_iomux_v3_setup_multiple_pads(
  240. usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
  241. #endif
  242. gpio_request(USDHC2_PWR_GPIO, "usdhc2 pwr");
  243. gpio_direction_output(USDHC2_PWR_GPIO, 0);
  244. udelay(500);
  245. gpio_direction_output(USDHC2_PWR_GPIO, 1);
  246. usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  247. break;
  248. default:
  249. printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1);
  250. return -EINVAL;
  251. }
  252. ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  253. if (ret) {
  254. printf("Warning: failed to initialize mmc dev %d\n", i);
  255. return ret;
  256. }
  257. }
  258. #endif
  259. return 0;
  260. }
  261. #endif
  262. #ifdef CONFIG_USB_EHCI_MX6
  263. #ifndef CONFIG_DM_USB
  264. #define USB_OTHERREGS_OFFSET 0x800
  265. #define UCTRL_PWR_POL (1 << 9)
  266. static iomux_v3_cfg_t const usb_otg_pads[] = {
  267. MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
  268. };
  269. /* At default the 3v3 enables the MIC2026 for VBUS power */
  270. static void setup_usb(void)
  271. {
  272. imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
  273. ARRAY_SIZE(usb_otg_pads));
  274. }
  275. int board_usb_phy_mode(int port)
  276. {
  277. if (port == 1)
  278. return USB_INIT_HOST;
  279. else
  280. return usb_phy_mode(port);
  281. }
  282. int board_ehci_hcd_init(int port)
  283. {
  284. u32 *usbnc_usb_ctrl;
  285. if (port > 1)
  286. return -EINVAL;
  287. usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
  288. port * 4);
  289. /* Set Power polarity */
  290. setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
  291. return 0;
  292. }
  293. #endif
  294. #endif
  295. #ifdef CONFIG_FEC_MXC
  296. /*
  297. * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
  298. * be used for ENET1 or ENET2, cannot be used for both.
  299. */
  300. static iomux_v3_cfg_t const fec1_pads[] = {
  301. MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
  302. MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  303. MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  304. MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  305. MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  306. MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
  307. MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  308. MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  309. MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
  310. MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  311. };
  312. static iomux_v3_cfg_t const fec2_pads[] = {
  313. MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
  314. MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  315. MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  316. MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  317. MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
  318. MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  319. MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  320. MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  321. MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  322. MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
  323. };
  324. static void setup_iomux_fec(int fec_id)
  325. {
  326. if (fec_id == 0)
  327. imx_iomux_v3_setup_multiple_pads(fec1_pads,
  328. ARRAY_SIZE(fec1_pads));
  329. else
  330. imx_iomux_v3_setup_multiple_pads(fec2_pads,
  331. ARRAY_SIZE(fec2_pads));
  332. }
  333. int board_eth_init(bd_t *bis)
  334. {
  335. setup_iomux_fec(CONFIG_FEC_ENET_DEV);
  336. return fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
  337. CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
  338. }
  339. static int setup_fec(int fec_id)
  340. {
  341. struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  342. int ret;
  343. if (fec_id == 0) {
  344. /*
  345. * Use 50M anatop loopback REF_CLK1 for ENET1,
  346. * clear gpr1[13], set gpr1[17].
  347. */
  348. clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
  349. IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
  350. } else {
  351. /*
  352. * Use 50M anatop loopback REF_CLK2 for ENET2,
  353. * clear gpr1[14], set gpr1[18].
  354. */
  355. clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
  356. IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
  357. }
  358. ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
  359. if (ret)
  360. return ret;
  361. enable_enet_clk(1);
  362. return 0;
  363. }
  364. int board_phy_config(struct phy_device *phydev)
  365. {
  366. phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
  367. if (phydev->drv->config)
  368. phydev->drv->config(phydev);
  369. return 0;
  370. }
  371. #endif
  372. #ifdef CONFIG_VIDEO_MXS
  373. static iomux_v3_cfg_t const lcd_pads[] = {
  374. MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
  375. MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
  376. MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
  377. MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
  378. MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  379. MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  380. MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  381. MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  382. MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  383. MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  384. MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  385. MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  386. MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  387. MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  388. MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  389. MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  390. MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  391. MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  392. MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  393. MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  394. MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  395. MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  396. MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  397. MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  398. MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  399. MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  400. MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  401. MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  402. /* LCD_RST */
  403. MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
  404. /* Use GPIO for Brightness adjustment, duty cycle = period. */
  405. MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
  406. };
  407. static int setup_lcd(void)
  408. {
  409. enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
  410. imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
  411. /* Reset the LCD */
  412. gpio_request(IMX_GPIO_NR(5, 9), "lcd reset");
  413. gpio_direction_output(IMX_GPIO_NR(5, 9) , 0);
  414. udelay(500);
  415. gpio_direction_output(IMX_GPIO_NR(5, 9) , 1);
  416. /* Set Brightness to high */
  417. gpio_request(IMX_GPIO_NR(1, 8), "backlight");
  418. gpio_direction_output(IMX_GPIO_NR(1, 8) , 1);
  419. return 0;
  420. }
  421. #endif
  422. int board_early_init_f(void)
  423. {
  424. setup_iomux_uart();
  425. return 0;
  426. }
  427. int board_init(void)
  428. {
  429. /* Address of boot parameters */
  430. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  431. #ifdef CONFIG_FEC_MXC
  432. setup_fec(CONFIG_FEC_ENET_DEV);
  433. #endif
  434. #ifdef CONFIG_USB_EHCI_MX6
  435. #ifndef CONFIG_DM_USB
  436. setup_usb();
  437. #endif
  438. #endif
  439. #ifdef CONFIG_FSL_QSPI
  440. board_qspi_init();
  441. #endif
  442. #ifdef CONFIG_VIDEO_MXS
  443. setup_lcd();
  444. #endif
  445. return 0;
  446. }
  447. #ifdef CONFIG_CMD_BMODE
  448. static const struct boot_mode board_boot_modes[] = {
  449. /* 4 bit bus width */
  450. {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
  451. {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  452. {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
  453. {NULL, 0},
  454. };
  455. #endif
  456. int board_late_init(void)
  457. {
  458. #ifdef CONFIG_CMD_BMODE
  459. add_board_boot_modes(board_boot_modes);
  460. #endif
  461. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  462. env_set("board_name", "EVK");
  463. if (is_mx6ul_9x9_evk())
  464. env_set("board_rev", "9X9");
  465. else
  466. env_set("board_rev", "14X14");
  467. #endif
  468. return 0;
  469. }
  470. int checkboard(void)
  471. {
  472. if (is_mx6ul_9x9_evk())
  473. puts("Board: MX6UL 9x9 EVK\n");
  474. else
  475. puts("Board: MX6UL 14x14 EVK\n");
  476. return 0;
  477. }
  478. #ifdef CONFIG_SPL_BUILD
  479. #include <linux/libfdt.h>
  480. #include <spl.h>
  481. #include <asm/arch/mx6-ddr.h>
  482. static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
  483. .grp_addds = 0x00000030,
  484. .grp_ddrmode_ctl = 0x00020000,
  485. .grp_b0ds = 0x00000030,
  486. .grp_ctlds = 0x00000030,
  487. .grp_b1ds = 0x00000030,
  488. .grp_ddrpke = 0x00000000,
  489. .grp_ddrmode = 0x00020000,
  490. #ifdef CONFIG_TARGET_MX6UL_9X9_EVK
  491. .grp_ddr_type = 0x00080000,
  492. #else
  493. .grp_ddr_type = 0x000c0000,
  494. #endif
  495. };
  496. #ifdef CONFIG_TARGET_MX6UL_9X9_EVK
  497. static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
  498. .dram_dqm0 = 0x00000030,
  499. .dram_dqm1 = 0x00000030,
  500. .dram_ras = 0x00000030,
  501. .dram_cas = 0x00000030,
  502. .dram_odt0 = 0x00000000,
  503. .dram_odt1 = 0x00000000,
  504. .dram_sdba2 = 0x00000000,
  505. .dram_sdclk_0 = 0x00000030,
  506. .dram_sdqs0 = 0x00003030,
  507. .dram_sdqs1 = 0x00003030,
  508. .dram_reset = 0x00000030,
  509. };
  510. static struct mx6_mmdc_calibration mx6_mmcd_calib = {
  511. .p0_mpwldectrl0 = 0x00000000,
  512. .p0_mpdgctrl0 = 0x20000000,
  513. .p0_mprddlctl = 0x4040484f,
  514. .p0_mpwrdlctl = 0x40405247,
  515. .mpzqlp2ctl = 0x1b4700c7,
  516. };
  517. static struct mx6_lpddr2_cfg mem_ddr = {
  518. .mem_speed = 800,
  519. .density = 2,
  520. .width = 16,
  521. .banks = 4,
  522. .rowaddr = 14,
  523. .coladdr = 10,
  524. .trcd_lp = 1500,
  525. .trppb_lp = 1500,
  526. .trpab_lp = 2000,
  527. .trasmin = 4250,
  528. };
  529. struct mx6_ddr_sysinfo ddr_sysinfo = {
  530. .dsize = 0,
  531. .cs_density = 18,
  532. .ncs = 1,
  533. .cs1_mirror = 0,
  534. .walat = 0,
  535. .ralat = 5,
  536. .mif3_mode = 3,
  537. .bi_on = 1,
  538. .rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */
  539. .rtt_nom = 0,
  540. .sde_to_rst = 0, /* LPDDR2 does not need this field */
  541. .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
  542. .ddr_type = DDR_TYPE_LPDDR2,
  543. .refsel = 0, /* Refresh cycles at 64KHz */
  544. .refr = 3, /* 4 refresh commands per refresh cycle */
  545. };
  546. #else
  547. static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
  548. .dram_dqm0 = 0x00000030,
  549. .dram_dqm1 = 0x00000030,
  550. .dram_ras = 0x00000030,
  551. .dram_cas = 0x00000030,
  552. .dram_odt0 = 0x00000030,
  553. .dram_odt1 = 0x00000030,
  554. .dram_sdba2 = 0x00000000,
  555. .dram_sdclk_0 = 0x00000030,
  556. .dram_sdqs0 = 0x00000030,
  557. .dram_sdqs1 = 0x00000030,
  558. .dram_reset = 0x00000030,
  559. };
  560. static struct mx6_mmdc_calibration mx6_mmcd_calib = {
  561. .p0_mpwldectrl0 = 0x00000000,
  562. .p0_mpdgctrl0 = 0x41570155,
  563. .p0_mprddlctl = 0x4040474A,
  564. .p0_mpwrdlctl = 0x40405550,
  565. };
  566. struct mx6_ddr_sysinfo ddr_sysinfo = {
  567. .dsize = 0,
  568. .cs_density = 20,
  569. .ncs = 1,
  570. .cs1_mirror = 0,
  571. .rtt_wr = 2,
  572. .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
  573. .walat = 0, /* Write additional latency */
  574. .ralat = 5, /* Read additional latency */
  575. .mif3_mode = 3, /* Command prediction working mode */
  576. .bi_on = 1, /* Bank interleaving enabled */
  577. .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
  578. .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
  579. .ddr_type = DDR_TYPE_DDR3,
  580. .refsel = 0, /* Refresh cycles at 64KHz */
  581. .refr = 1, /* 2 refresh commands per refresh cycle */
  582. };
  583. static struct mx6_ddr3_cfg mem_ddr = {
  584. .mem_speed = 800,
  585. .density = 4,
  586. .width = 16,
  587. .banks = 8,
  588. .rowaddr = 15,
  589. .coladdr = 10,
  590. .pagesz = 2,
  591. .trcd = 1375,
  592. .trcmin = 4875,
  593. .trasmin = 3500,
  594. };
  595. #endif
  596. static void ccgr_init(void)
  597. {
  598. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  599. writel(0xFFFFFFFF, &ccm->CCGR0);
  600. writel(0xFFFFFFFF, &ccm->CCGR1);
  601. writel(0xFFFFFFFF, &ccm->CCGR2);
  602. writel(0xFFFFFFFF, &ccm->CCGR3);
  603. writel(0xFFFFFFFF, &ccm->CCGR4);
  604. writel(0xFFFFFFFF, &ccm->CCGR5);
  605. writel(0xFFFFFFFF, &ccm->CCGR6);
  606. writel(0xFFFFFFFF, &ccm->CCGR7);
  607. }
  608. static void spl_dram_init(void)
  609. {
  610. mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
  611. mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
  612. }
  613. void board_init_f(ulong dummy)
  614. {
  615. ccgr_init();
  616. /* setup AIPS and disable watchdog */
  617. arch_cpu_init();
  618. /* iomux and setup of i2c */
  619. board_early_init_f();
  620. /* setup GP timer */
  621. timer_init();
  622. /* UART clocks enabled and gd valid - init serial console */
  623. preloader_console_init();
  624. /* DDR initialization */
  625. spl_dram_init();
  626. /* Clear the BSS. */
  627. memset(__bss_start, 0, __bss_end - __bss_start);
  628. /* load/boot image from boot device */
  629. board_init_r(NULL, 0);
  630. }
  631. #endif