mx6sabresd.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Freescale Semiconductor, Inc.
  4. *
  5. * Author: Fabio Estevam <fabio.estevam@freescale.com>
  6. */
  7. #include <asm/arch/clock.h>
  8. #include <asm/arch/imx-regs.h>
  9. #include <asm/arch/iomux.h>
  10. #include <asm/arch/mx6-pins.h>
  11. #include <asm/mach-imx/spi.h>
  12. #include <env.h>
  13. #include <linux/errno.h>
  14. #include <asm/gpio.h>
  15. #include <asm/mach-imx/mxc_i2c.h>
  16. #include <asm/mach-imx/iomux-v3.h>
  17. #include <asm/mach-imx/boot_mode.h>
  18. #include <asm/mach-imx/video.h>
  19. #include <mmc.h>
  20. #include <fsl_esdhc_imx.h>
  21. #include <miiphy.h>
  22. #include <netdev.h>
  23. #include <asm/arch/mxc_hdmi.h>
  24. #include <asm/arch/crm_regs.h>
  25. #include <asm/io.h>
  26. #include <asm/arch/sys_proto.h>
  27. #include <i2c.h>
  28. #include <input.h>
  29. #include <power/pmic.h>
  30. #include <power/pfuze100_pmic.h>
  31. #include "../common/pfuze.h"
  32. #include <usb.h>
  33. #include <usb/ehci-ci.h>
  34. DECLARE_GLOBAL_DATA_PTR;
  35. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  36. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  37. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  38. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  39. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  40. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  41. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  42. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  43. #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  44. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  45. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  46. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  47. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  48. #define I2C_PMIC 1
  49. #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  50. #define DISP0_PWR_EN IMX_GPIO_NR(1, 21)
  51. #define KEY_VOL_UP IMX_GPIO_NR(1, 4)
  52. int dram_init(void)
  53. {
  54. gd->ram_size = imx_ddr_size();
  55. return 0;
  56. }
  57. static iomux_v3_cfg_t const uart1_pads[] = {
  58. IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  59. IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  60. };
  61. static iomux_v3_cfg_t const enet_pads[] = {
  62. IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  63. IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  64. IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  65. IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  66. IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  67. IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  68. IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  69. IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  70. IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  71. IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  72. IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  73. IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  74. IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  75. IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  76. IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  77. /* AR8031 PHY Reset */
  78. IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  79. };
  80. static void setup_iomux_enet(void)
  81. {
  82. SETUP_IOMUX_PADS(enet_pads);
  83. }
  84. static iomux_v3_cfg_t const usdhc2_pads[] = {
  85. IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  86. IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  87. IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  88. IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  89. IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  90. IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  91. IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  92. IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  93. IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  94. IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  95. IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
  96. };
  97. static iomux_v3_cfg_t const usdhc3_pads[] = {
  98. IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  99. IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  100. IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  101. IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  102. IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  103. IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  104. IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  105. IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  106. IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  107. IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  108. IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
  109. };
  110. static iomux_v3_cfg_t const usdhc4_pads[] = {
  111. IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  112. IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  113. IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  114. IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  115. IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  116. IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  117. IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  118. IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  119. IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  120. IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  121. };
  122. static iomux_v3_cfg_t const ecspi1_pads[] = {
  123. IOMUX_PADS(PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  124. IOMUX_PADS(PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  125. IOMUX_PADS(PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  126. IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  127. };
  128. static iomux_v3_cfg_t const rgb_pads[] = {
  129. IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)),
  130. IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  131. IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  132. IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  133. IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  134. IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  135. IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  136. IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  137. IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  138. IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  139. IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  140. IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  141. IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  142. IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  143. IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  144. IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  145. IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  146. IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  147. IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  148. IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  149. IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  150. IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  151. IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  152. IOMUX_PADS(PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  153. IOMUX_PADS(PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  154. IOMUX_PADS(PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  155. IOMUX_PADS(PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  156. IOMUX_PADS(PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  157. IOMUX_PADS(PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  158. };
  159. static iomux_v3_cfg_t const bl_pads[] = {
  160. IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  161. };
  162. static void enable_backlight(void)
  163. {
  164. SETUP_IOMUX_PADS(bl_pads);
  165. gpio_request(DISP0_PWR_EN, "Display Power Enable");
  166. gpio_direction_output(DISP0_PWR_EN, 1);
  167. }
  168. static void enable_rgb(struct display_info_t const *dev)
  169. {
  170. SETUP_IOMUX_PADS(rgb_pads);
  171. enable_backlight();
  172. }
  173. static void enable_lvds(struct display_info_t const *dev)
  174. {
  175. enable_backlight();
  176. }
  177. static struct i2c_pads_info mx6q_i2c_pad_info1 = {
  178. .scl = {
  179. .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
  180. .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
  181. .gp = IMX_GPIO_NR(4, 12)
  182. },
  183. .sda = {
  184. .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
  185. .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
  186. .gp = IMX_GPIO_NR(4, 13)
  187. }
  188. };
  189. static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
  190. .scl = {
  191. .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
  192. .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
  193. .gp = IMX_GPIO_NR(4, 12)
  194. },
  195. .sda = {
  196. .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
  197. .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
  198. .gp = IMX_GPIO_NR(4, 13)
  199. }
  200. };
  201. static void setup_spi(void)
  202. {
  203. SETUP_IOMUX_PADS(ecspi1_pads);
  204. }
  205. iomux_v3_cfg_t const pcie_pads[] = {
  206. IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* POWER */
  207. IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* RESET */
  208. };
  209. static void setup_pcie(void)
  210. {
  211. SETUP_IOMUX_PADS(pcie_pads);
  212. }
  213. iomux_v3_cfg_t const di0_pads[] = {
  214. IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK), /* DISP0_CLK */
  215. IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* DISP0_HSYNC */
  216. IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* DISP0_VSYNC */
  217. };
  218. static void setup_iomux_uart(void)
  219. {
  220. SETUP_IOMUX_PADS(uart1_pads);
  221. }
  222. #ifdef CONFIG_FSL_ESDHC_IMX
  223. struct fsl_esdhc_cfg usdhc_cfg[3] = {
  224. {USDHC2_BASE_ADDR},
  225. {USDHC3_BASE_ADDR},
  226. {USDHC4_BASE_ADDR},
  227. };
  228. #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
  229. #define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
  230. int board_mmc_get_env_dev(int devno)
  231. {
  232. return devno - 1;
  233. }
  234. int board_mmc_getcd(struct mmc *mmc)
  235. {
  236. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  237. int ret = 0;
  238. switch (cfg->esdhc_base) {
  239. case USDHC2_BASE_ADDR:
  240. ret = !gpio_get_value(USDHC2_CD_GPIO);
  241. break;
  242. case USDHC3_BASE_ADDR:
  243. ret = !gpio_get_value(USDHC3_CD_GPIO);
  244. break;
  245. case USDHC4_BASE_ADDR:
  246. ret = 1; /* eMMC/uSDHC4 is always present */
  247. break;
  248. }
  249. return ret;
  250. }
  251. int board_mmc_init(bd_t *bis)
  252. {
  253. struct src *psrc = (struct src *)SRC_BASE_ADDR;
  254. unsigned reg = readl(&psrc->sbmr1) >> 11;
  255. /*
  256. * Upon reading BOOT_CFG register the following map is done:
  257. * Bit 11 and 12 of BOOT_CFG register can determine the current
  258. * mmc port
  259. * 0x1 SD1
  260. * 0x2 SD2
  261. * 0x3 SD4
  262. */
  263. switch (reg & 0x3) {
  264. case 0x1:
  265. SETUP_IOMUX_PADS(usdhc2_pads);
  266. usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
  267. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  268. gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
  269. break;
  270. case 0x2:
  271. SETUP_IOMUX_PADS(usdhc3_pads);
  272. usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
  273. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  274. gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
  275. break;
  276. case 0x3:
  277. SETUP_IOMUX_PADS(usdhc4_pads);
  278. usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
  279. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  280. gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
  281. break;
  282. }
  283. return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  284. }
  285. #endif
  286. static int ar8031_phy_fixup(struct phy_device *phydev)
  287. {
  288. unsigned short val;
  289. /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
  290. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  291. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
  292. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
  293. val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
  294. val &= 0xffe3;
  295. val |= 0x18;
  296. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
  297. /* introduce tx clock delay */
  298. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
  299. val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
  300. val |= 0x0100;
  301. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
  302. return 0;
  303. }
  304. int board_phy_config(struct phy_device *phydev)
  305. {
  306. ar8031_phy_fixup(phydev);
  307. if (phydev->drv->config)
  308. phydev->drv->config(phydev);
  309. return 0;
  310. }
  311. #if defined(CONFIG_VIDEO_IPUV3)
  312. static void disable_lvds(struct display_info_t const *dev)
  313. {
  314. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  315. int reg = readl(&iomux->gpr[2]);
  316. reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
  317. IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
  318. writel(reg, &iomux->gpr[2]);
  319. }
  320. static void do_enable_hdmi(struct display_info_t const *dev)
  321. {
  322. disable_lvds(dev);
  323. imx_enable_hdmi_phy();
  324. }
  325. struct display_info_t const displays[] = {{
  326. .bus = -1,
  327. .addr = 0,
  328. .pixfmt = IPU_PIX_FMT_RGB666,
  329. .detect = NULL,
  330. .enable = enable_lvds,
  331. .mode = {
  332. .name = "Hannstar-XGA",
  333. .refresh = 60,
  334. .xres = 1024,
  335. .yres = 768,
  336. .pixclock = 15384,
  337. .left_margin = 160,
  338. .right_margin = 24,
  339. .upper_margin = 29,
  340. .lower_margin = 3,
  341. .hsync_len = 136,
  342. .vsync_len = 6,
  343. .sync = FB_SYNC_EXT,
  344. .vmode = FB_VMODE_NONINTERLACED
  345. } }, {
  346. .bus = -1,
  347. .addr = 0,
  348. .pixfmt = IPU_PIX_FMT_RGB24,
  349. .detect = detect_hdmi,
  350. .enable = do_enable_hdmi,
  351. .mode = {
  352. .name = "HDMI",
  353. .refresh = 60,
  354. .xres = 1024,
  355. .yres = 768,
  356. .pixclock = 15384,
  357. .left_margin = 160,
  358. .right_margin = 24,
  359. .upper_margin = 29,
  360. .lower_margin = 3,
  361. .hsync_len = 136,
  362. .vsync_len = 6,
  363. .sync = FB_SYNC_EXT,
  364. .vmode = FB_VMODE_NONINTERLACED
  365. } }, {
  366. .bus = 0,
  367. .addr = 0,
  368. .pixfmt = IPU_PIX_FMT_RGB24,
  369. .detect = NULL,
  370. .enable = enable_rgb,
  371. .mode = {
  372. .name = "SEIKO-WVGA",
  373. .refresh = 60,
  374. .xres = 800,
  375. .yres = 480,
  376. .pixclock = 29850,
  377. .left_margin = 89,
  378. .right_margin = 164,
  379. .upper_margin = 23,
  380. .lower_margin = 10,
  381. .hsync_len = 10,
  382. .vsync_len = 10,
  383. .sync = 0,
  384. .vmode = FB_VMODE_NONINTERLACED
  385. } } };
  386. size_t display_count = ARRAY_SIZE(displays);
  387. static void setup_display(void)
  388. {
  389. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  390. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  391. int reg;
  392. /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
  393. SETUP_IOMUX_PADS(di0_pads);
  394. enable_ipu_clock();
  395. imx_setup_hdmi();
  396. /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
  397. reg = readl(&mxc_ccm->CCGR3);
  398. reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
  399. writel(reg, &mxc_ccm->CCGR3);
  400. /* set LDB0, LDB1 clk select to 011/011 */
  401. reg = readl(&mxc_ccm->cs2cdr);
  402. reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
  403. | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
  404. reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
  405. | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
  406. writel(reg, &mxc_ccm->cs2cdr);
  407. reg = readl(&mxc_ccm->cscmr2);
  408. reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
  409. writel(reg, &mxc_ccm->cscmr2);
  410. reg = readl(&mxc_ccm->chsccdr);
  411. reg |= (CHSCCDR_CLK_SEL_LDB_DI0
  412. << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  413. reg |= (CHSCCDR_CLK_SEL_LDB_DI0
  414. << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
  415. writel(reg, &mxc_ccm->chsccdr);
  416. reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
  417. | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
  418. | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
  419. | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
  420. | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
  421. | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
  422. | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
  423. | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
  424. | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
  425. writel(reg, &iomux->gpr[2]);
  426. reg = readl(&iomux->gpr[3]);
  427. reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
  428. | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
  429. | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
  430. << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
  431. writel(reg, &iomux->gpr[3]);
  432. }
  433. #endif /* CONFIG_VIDEO_IPUV3 */
  434. /*
  435. * Do not overwrite the console
  436. * Use always serial for U-Boot console
  437. */
  438. int overwrite_console(void)
  439. {
  440. return 1;
  441. }
  442. int board_eth_init(bd_t *bis)
  443. {
  444. setup_iomux_enet();
  445. setup_pcie();
  446. return cpu_eth_init(bis);
  447. }
  448. #ifdef CONFIG_USB_EHCI_MX6
  449. static void setup_usb(void)
  450. {
  451. /*
  452. * set daisy chain for otg_pin_id on 6q.
  453. * for 6dl, this bit is reserved
  454. */
  455. imx_iomux_set_gpr_register(1, 13, 1, 0);
  456. }
  457. #endif
  458. int board_early_init_f(void)
  459. {
  460. setup_iomux_uart();
  461. return 0;
  462. }
  463. int board_init(void)
  464. {
  465. /* address of boot parameters */
  466. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  467. #ifdef CONFIG_MXC_SPI
  468. setup_spi();
  469. #endif
  470. if (is_mx6dq() || is_mx6dqp())
  471. setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
  472. else
  473. setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
  474. #if defined(CONFIG_VIDEO_IPUV3)
  475. setup_display();
  476. #endif
  477. #ifdef CONFIG_USB_EHCI_MX6
  478. setup_usb();
  479. #endif
  480. return 0;
  481. }
  482. int power_init_board(void)
  483. {
  484. struct pmic *p;
  485. unsigned int reg;
  486. int ret;
  487. p = pfuze_common_init(I2C_PMIC);
  488. if (!p)
  489. return -ENODEV;
  490. ret = pfuze_mode_init(p, APS_PFM);
  491. if (ret < 0)
  492. return ret;
  493. /* Increase VGEN3 from 2.5 to 2.8V */
  494. pmic_reg_read(p, PFUZE100_VGEN3VOL, &reg);
  495. reg &= ~LDO_VOL_MASK;
  496. reg |= LDOB_2_80V;
  497. pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
  498. /* Increase VGEN5 from 2.8 to 3V */
  499. pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
  500. reg &= ~LDO_VOL_MASK;
  501. reg |= LDOB_3_00V;
  502. pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
  503. return 0;
  504. }
  505. #ifdef CONFIG_MXC_SPI
  506. int board_spi_cs_gpio(unsigned bus, unsigned cs)
  507. {
  508. return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
  509. }
  510. #endif
  511. #ifdef CONFIG_CMD_BMODE
  512. static const struct boot_mode board_boot_modes[] = {
  513. /* 4 bit bus width */
  514. {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  515. {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  516. /* 8 bit bus width */
  517. {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
  518. {NULL, 0},
  519. };
  520. #endif
  521. int board_late_init(void)
  522. {
  523. #ifdef CONFIG_CMD_BMODE
  524. add_board_boot_modes(board_boot_modes);
  525. #endif
  526. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  527. env_set("board_name", "SABRESD");
  528. if (is_mx6dqp())
  529. env_set("board_rev", "MX6QP");
  530. else if (is_mx6dq())
  531. env_set("board_rev", "MX6Q");
  532. else if (is_mx6sdl())
  533. env_set("board_rev", "MX6DL");
  534. #endif
  535. return 0;
  536. }
  537. int checkboard(void)
  538. {
  539. puts("Board: MX6-SabreSD\n");
  540. return 0;
  541. }
  542. #ifdef CONFIG_SPL_BUILD
  543. #include <asm/arch/mx6-ddr.h>
  544. #include <spl.h>
  545. #include <linux/libfdt.h>
  546. #ifdef CONFIG_SPL_OS_BOOT
  547. int spl_start_uboot(void)
  548. {
  549. gpio_request(KEY_VOL_UP, "KEY Volume UP");
  550. gpio_direction_input(KEY_VOL_UP);
  551. /* Only enter in Falcon mode if KEY_VOL_UP is pressed */
  552. return gpio_get_value(KEY_VOL_UP);
  553. }
  554. #endif
  555. static void ccgr_init(void)
  556. {
  557. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  558. writel(0x00C03F3F, &ccm->CCGR0);
  559. writel(0x0030FC03, &ccm->CCGR1);
  560. writel(0x0FFFC000, &ccm->CCGR2);
  561. writel(0x3FF00000, &ccm->CCGR3);
  562. writel(0x00FFF300, &ccm->CCGR4);
  563. writel(0x0F0000C3, &ccm->CCGR5);
  564. writel(0x000003FF, &ccm->CCGR6);
  565. }
  566. static int mx6q_dcd_table[] = {
  567. 0x020e0798, 0x000C0000,
  568. 0x020e0758, 0x00000000,
  569. 0x020e0588, 0x00000030,
  570. 0x020e0594, 0x00000030,
  571. 0x020e056c, 0x00000030,
  572. 0x020e0578, 0x00000030,
  573. 0x020e074c, 0x00000030,
  574. 0x020e057c, 0x00000030,
  575. 0x020e058c, 0x00000000,
  576. 0x020e059c, 0x00000030,
  577. 0x020e05a0, 0x00000030,
  578. 0x020e078c, 0x00000030,
  579. 0x020e0750, 0x00020000,
  580. 0x020e05a8, 0x00000030,
  581. 0x020e05b0, 0x00000030,
  582. 0x020e0524, 0x00000030,
  583. 0x020e051c, 0x00000030,
  584. 0x020e0518, 0x00000030,
  585. 0x020e050c, 0x00000030,
  586. 0x020e05b8, 0x00000030,
  587. 0x020e05c0, 0x00000030,
  588. 0x020e0774, 0x00020000,
  589. 0x020e0784, 0x00000030,
  590. 0x020e0788, 0x00000030,
  591. 0x020e0794, 0x00000030,
  592. 0x020e079c, 0x00000030,
  593. 0x020e07a0, 0x00000030,
  594. 0x020e07a4, 0x00000030,
  595. 0x020e07a8, 0x00000030,
  596. 0x020e0748, 0x00000030,
  597. 0x020e05ac, 0x00000030,
  598. 0x020e05b4, 0x00000030,
  599. 0x020e0528, 0x00000030,
  600. 0x020e0520, 0x00000030,
  601. 0x020e0514, 0x00000030,
  602. 0x020e0510, 0x00000030,
  603. 0x020e05bc, 0x00000030,
  604. 0x020e05c4, 0x00000030,
  605. 0x021b0800, 0xa1390003,
  606. 0x021b080c, 0x001F001F,
  607. 0x021b0810, 0x001F001F,
  608. 0x021b480c, 0x001F001F,
  609. 0x021b4810, 0x001F001F,
  610. 0x021b083c, 0x43270338,
  611. 0x021b0840, 0x03200314,
  612. 0x021b483c, 0x431A032F,
  613. 0x021b4840, 0x03200263,
  614. 0x021b0848, 0x4B434748,
  615. 0x021b4848, 0x4445404C,
  616. 0x021b0850, 0x38444542,
  617. 0x021b4850, 0x4935493A,
  618. 0x021b081c, 0x33333333,
  619. 0x021b0820, 0x33333333,
  620. 0x021b0824, 0x33333333,
  621. 0x021b0828, 0x33333333,
  622. 0x021b481c, 0x33333333,
  623. 0x021b4820, 0x33333333,
  624. 0x021b4824, 0x33333333,
  625. 0x021b4828, 0x33333333,
  626. 0x021b08b8, 0x00000800,
  627. 0x021b48b8, 0x00000800,
  628. 0x021b0004, 0x00020036,
  629. 0x021b0008, 0x09444040,
  630. 0x021b000c, 0x555A7975,
  631. 0x021b0010, 0xFF538F64,
  632. 0x021b0014, 0x01FF00DB,
  633. 0x021b0018, 0x00001740,
  634. 0x021b001c, 0x00008000,
  635. 0x021b002c, 0x000026d2,
  636. 0x021b0030, 0x005A1023,
  637. 0x021b0040, 0x00000027,
  638. 0x021b0000, 0x831A0000,
  639. 0x021b001c, 0x04088032,
  640. 0x021b001c, 0x00008033,
  641. 0x021b001c, 0x00048031,
  642. 0x021b001c, 0x09408030,
  643. 0x021b001c, 0x04008040,
  644. 0x021b0020, 0x00005800,
  645. 0x021b0818, 0x00011117,
  646. 0x021b4818, 0x00011117,
  647. 0x021b0004, 0x00025576,
  648. 0x021b0404, 0x00011006,
  649. 0x021b001c, 0x00000000,
  650. };
  651. static int mx6qp_dcd_table[] = {
  652. 0x020e0798, 0x000c0000,
  653. 0x020e0758, 0x00000000,
  654. 0x020e0588, 0x00000030,
  655. 0x020e0594, 0x00000030,
  656. 0x020e056c, 0x00000030,
  657. 0x020e0578, 0x00000030,
  658. 0x020e074c, 0x00000030,
  659. 0x020e057c, 0x00000030,
  660. 0x020e058c, 0x00000000,
  661. 0x020e059c, 0x00000030,
  662. 0x020e05a0, 0x00000030,
  663. 0x020e078c, 0x00000030,
  664. 0x020e0750, 0x00020000,
  665. 0x020e05a8, 0x00000030,
  666. 0x020e05b0, 0x00000030,
  667. 0x020e0524, 0x00000030,
  668. 0x020e051c, 0x00000030,
  669. 0x020e0518, 0x00000030,
  670. 0x020e050c, 0x00000030,
  671. 0x020e05b8, 0x00000030,
  672. 0x020e05c0, 0x00000030,
  673. 0x020e0774, 0x00020000,
  674. 0x020e0784, 0x00000030,
  675. 0x020e0788, 0x00000030,
  676. 0x020e0794, 0x00000030,
  677. 0x020e079c, 0x00000030,
  678. 0x020e07a0, 0x00000030,
  679. 0x020e07a4, 0x00000030,
  680. 0x020e07a8, 0x00000030,
  681. 0x020e0748, 0x00000030,
  682. 0x020e05ac, 0x00000030,
  683. 0x020e05b4, 0x00000030,
  684. 0x020e0528, 0x00000030,
  685. 0x020e0520, 0x00000030,
  686. 0x020e0514, 0x00000030,
  687. 0x020e0510, 0x00000030,
  688. 0x020e05bc, 0x00000030,
  689. 0x020e05c4, 0x00000030,
  690. 0x021b0800, 0xa1390003,
  691. 0x021b080c, 0x001b001e,
  692. 0x021b0810, 0x002e0029,
  693. 0x021b480c, 0x001b002a,
  694. 0x021b4810, 0x0019002c,
  695. 0x021b083c, 0x43240334,
  696. 0x021b0840, 0x0324031a,
  697. 0x021b483c, 0x43340344,
  698. 0x021b4840, 0x03280276,
  699. 0x021b0848, 0x44383A3E,
  700. 0x021b4848, 0x3C3C3846,
  701. 0x021b0850, 0x2e303230,
  702. 0x021b4850, 0x38283E34,
  703. 0x021b081c, 0x33333333,
  704. 0x021b0820, 0x33333333,
  705. 0x021b0824, 0x33333333,
  706. 0x021b0828, 0x33333333,
  707. 0x021b481c, 0x33333333,
  708. 0x021b4820, 0x33333333,
  709. 0x021b4824, 0x33333333,
  710. 0x021b4828, 0x33333333,
  711. 0x021b08c0, 0x24912249,
  712. 0x021b48c0, 0x24914289,
  713. 0x021b08b8, 0x00000800,
  714. 0x021b48b8, 0x00000800,
  715. 0x021b0004, 0x00020036,
  716. 0x021b0008, 0x24444040,
  717. 0x021b000c, 0x555A7955,
  718. 0x021b0010, 0xFF320F64,
  719. 0x021b0014, 0x01ff00db,
  720. 0x021b0018, 0x00001740,
  721. 0x021b001c, 0x00008000,
  722. 0x021b002c, 0x000026d2,
  723. 0x021b0030, 0x005A1023,
  724. 0x021b0040, 0x00000027,
  725. 0x021b0400, 0x14420000,
  726. 0x021b0000, 0x831A0000,
  727. 0x021b0890, 0x00400C58,
  728. 0x00bb0008, 0x00000000,
  729. 0x00bb000c, 0x2891E41A,
  730. 0x00bb0038, 0x00000564,
  731. 0x00bb0014, 0x00000040,
  732. 0x00bb0028, 0x00000020,
  733. 0x00bb002c, 0x00000020,
  734. 0x021b001c, 0x04088032,
  735. 0x021b001c, 0x00008033,
  736. 0x021b001c, 0x00048031,
  737. 0x021b001c, 0x09408030,
  738. 0x021b001c, 0x04008040,
  739. 0x021b0020, 0x00005800,
  740. 0x021b0818, 0x00011117,
  741. 0x021b4818, 0x00011117,
  742. 0x021b0004, 0x00025576,
  743. 0x021b0404, 0x00011006,
  744. 0x021b001c, 0x00000000,
  745. };
  746. static int mx6dl_dcd_table[] = {
  747. 0x020e0774, 0x000C0000,
  748. 0x020e0754, 0x00000000,
  749. 0x020e04ac, 0x00000030,
  750. 0x020e04b0, 0x00000030,
  751. 0x020e0464, 0x00000030,
  752. 0x020e0490, 0x00000030,
  753. 0x020e074c, 0x00000030,
  754. 0x020e0494, 0x00000030,
  755. 0x020e04a0, 0x00000000,
  756. 0x020e04b4, 0x00000030,
  757. 0x020e04b8, 0x00000030,
  758. 0x020e076c, 0x00000030,
  759. 0x020e0750, 0x00020000,
  760. 0x020e04bc, 0x00000030,
  761. 0x020e04c0, 0x00000030,
  762. 0x020e04c4, 0x00000030,
  763. 0x020e04c8, 0x00000030,
  764. 0x020e04cc, 0x00000030,
  765. 0x020e04d0, 0x00000030,
  766. 0x020e04d4, 0x00000030,
  767. 0x020e04d8, 0x00000030,
  768. 0x020e0760, 0x00020000,
  769. 0x020e0764, 0x00000030,
  770. 0x020e0770, 0x00000030,
  771. 0x020e0778, 0x00000030,
  772. 0x020e077c, 0x00000030,
  773. 0x020e0780, 0x00000030,
  774. 0x020e0784, 0x00000030,
  775. 0x020e078c, 0x00000030,
  776. 0x020e0748, 0x00000030,
  777. 0x020e0470, 0x00000030,
  778. 0x020e0474, 0x00000030,
  779. 0x020e0478, 0x00000030,
  780. 0x020e047c, 0x00000030,
  781. 0x020e0480, 0x00000030,
  782. 0x020e0484, 0x00000030,
  783. 0x020e0488, 0x00000030,
  784. 0x020e048c, 0x00000030,
  785. 0x021b0800, 0xa1390003,
  786. 0x021b080c, 0x001F001F,
  787. 0x021b0810, 0x001F001F,
  788. 0x021b480c, 0x001F001F,
  789. 0x021b4810, 0x001F001F,
  790. 0x021b083c, 0x4220021F,
  791. 0x021b0840, 0x0207017E,
  792. 0x021b483c, 0x4201020C,
  793. 0x021b4840, 0x01660172,
  794. 0x021b0848, 0x4A4D4E4D,
  795. 0x021b4848, 0x4A4F5049,
  796. 0x021b0850, 0x3F3C3D31,
  797. 0x021b4850, 0x3238372B,
  798. 0x021b081c, 0x33333333,
  799. 0x021b0820, 0x33333333,
  800. 0x021b0824, 0x33333333,
  801. 0x021b0828, 0x33333333,
  802. 0x021b481c, 0x33333333,
  803. 0x021b4820, 0x33333333,
  804. 0x021b4824, 0x33333333,
  805. 0x021b4828, 0x33333333,
  806. 0x021b08b8, 0x00000800,
  807. 0x021b48b8, 0x00000800,
  808. 0x021b0004, 0x0002002D,
  809. 0x021b0008, 0x00333030,
  810. 0x021b000c, 0x3F435313,
  811. 0x021b0010, 0xB66E8B63,
  812. 0x021b0014, 0x01FF00DB,
  813. 0x021b0018, 0x00001740,
  814. 0x021b001c, 0x00008000,
  815. 0x021b002c, 0x000026d2,
  816. 0x021b0030, 0x00431023,
  817. 0x021b0040, 0x00000027,
  818. 0x021b0000, 0x831A0000,
  819. 0x021b001c, 0x04008032,
  820. 0x021b001c, 0x00008033,
  821. 0x021b001c, 0x00048031,
  822. 0x021b001c, 0x05208030,
  823. 0x021b001c, 0x04008040,
  824. 0x021b0020, 0x00005800,
  825. 0x021b0818, 0x00011117,
  826. 0x021b4818, 0x00011117,
  827. 0x021b0004, 0x0002556D,
  828. 0x021b0404, 0x00011006,
  829. 0x021b001c, 0x00000000,
  830. };
  831. static void ddr_init(int *table, int size)
  832. {
  833. int i;
  834. for (i = 0; i < size / 2 ; i++)
  835. writel(table[2 * i + 1], table[2 * i]);
  836. }
  837. static void spl_dram_init(void)
  838. {
  839. if (is_mx6dq())
  840. ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
  841. else if (is_mx6dqp())
  842. ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
  843. else if (is_mx6sdl())
  844. ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
  845. }
  846. void board_init_f(ulong dummy)
  847. {
  848. /* DDR initialization */
  849. spl_dram_init();
  850. /* setup AIPS and disable watchdog */
  851. arch_cpu_init();
  852. ccgr_init();
  853. gpr_init();
  854. /* iomux and setup of i2c */
  855. board_early_init_f();
  856. /* setup GP timer */
  857. timer_init();
  858. /* UART clocks enabled and gd valid - init serial console */
  859. preloader_console_init();
  860. /* Clear the BSS. */
  861. memset(__bss_start, 0, __bss_end - __bss_start);
  862. /* load/boot image from boot device */
  863. board_init_r(NULL, 0);
  864. }
  865. #endif
  866. #ifdef CONFIG_SPL_LOAD_FIT
  867. int board_fit_config_name_match(const char *name)
  868. {
  869. if (is_mx6dq()) {
  870. if (!strcmp(name, "imx6q-sabresd"))
  871. return 0;
  872. } else if (is_mx6dqp()) {
  873. if (!strcmp(name, "imx6qp-sabresd"))
  874. return 0;
  875. } else if (is_mx6dl()) {
  876. if (!strcmp(name, "imx6dl-sabresd"))
  877. return 0;
  878. }
  879. return -1;
  880. }
  881. #endif