mx6sabreauto.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Freescale Semiconductor, Inc.
  4. *
  5. * Author: Fabio Estevam <fabio.estevam@freescale.com>
  6. */
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <asm/arch/iomux.h>
  12. #include <asm/arch/mx6-pins.h>
  13. #include <env.h>
  14. #include <linux/errno.h>
  15. #include <asm/gpio.h>
  16. #include <asm/mach-imx/iomux-v3.h>
  17. #include <asm/mach-imx/mxc_i2c.h>
  18. #include <asm/mach-imx/boot_mode.h>
  19. #include <asm/mach-imx/spi.h>
  20. #include <mmc.h>
  21. #include <fsl_esdhc_imx.h>
  22. #include <miiphy.h>
  23. #include <netdev.h>
  24. #include <asm/arch/sys_proto.h>
  25. #include <i2c.h>
  26. #include <input.h>
  27. #include <asm/arch/mxc_hdmi.h>
  28. #include <asm/mach-imx/video.h>
  29. #include <asm/arch/crm_regs.h>
  30. #include <pca953x.h>
  31. #include <power/pmic.h>
  32. #include <power/pfuze100_pmic.h>
  33. #include "../common/pfuze.h"
  34. DECLARE_GLOBAL_DATA_PTR;
  35. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  36. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  37. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  38. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  39. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  40. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  41. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  42. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  43. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  44. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  45. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  46. #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
  47. #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
  48. PAD_CTL_SRE_FAST)
  49. #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
  50. #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  51. #define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  52. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  53. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  54. #define I2C_PMIC 1
  55. int dram_init(void)
  56. {
  57. gd->ram_size = imx_ddr_size();
  58. return 0;
  59. }
  60. static iomux_v3_cfg_t const uart4_pads[] = {
  61. IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  62. IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  63. };
  64. static iomux_v3_cfg_t const enet_pads[] = {
  65. IOMUX_PADS(PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  66. IOMUX_PADS(PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  67. IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  68. IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  69. IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  70. IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  71. IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  72. IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  73. IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  74. IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  75. IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  76. IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  77. IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  78. IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  79. IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  80. };
  81. /* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
  82. static struct i2c_pads_info mx6q_i2c_pad_info1 = {
  83. .scl = {
  84. .i2c_mode = MX6Q_PAD_EIM_EB2__I2C2_SCL | PC,
  85. .gpio_mode = MX6Q_PAD_EIM_EB2__GPIO2_IO30 | PC,
  86. .gp = IMX_GPIO_NR(2, 30)
  87. },
  88. .sda = {
  89. .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
  90. .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
  91. .gp = IMX_GPIO_NR(4, 13)
  92. }
  93. };
  94. static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
  95. .scl = {
  96. .i2c_mode = MX6DL_PAD_EIM_EB2__I2C2_SCL | PC,
  97. .gpio_mode = MX6DL_PAD_EIM_EB2__GPIO2_IO30 | PC,
  98. .gp = IMX_GPIO_NR(2, 30)
  99. },
  100. .sda = {
  101. .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
  102. .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
  103. .gp = IMX_GPIO_NR(4, 13)
  104. }
  105. };
  106. #ifndef CONFIG_SYS_FLASH_CFI
  107. /*
  108. * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
  109. * Compass Sensor, Accelerometer, Res Touch
  110. */
  111. static struct i2c_pads_info mx6q_i2c_pad_info2 = {
  112. .scl = {
  113. .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
  114. .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
  115. .gp = IMX_GPIO_NR(1, 3)
  116. },
  117. .sda = {
  118. .i2c_mode = MX6Q_PAD_EIM_D18__I2C3_SDA | PC,
  119. .gpio_mode = MX6Q_PAD_EIM_D18__GPIO3_IO18 | PC,
  120. .gp = IMX_GPIO_NR(3, 18)
  121. }
  122. };
  123. static struct i2c_pads_info mx6dl_i2c_pad_info2 = {
  124. .scl = {
  125. .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
  126. .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
  127. .gp = IMX_GPIO_NR(1, 3)
  128. },
  129. .sda = {
  130. .i2c_mode = MX6DL_PAD_EIM_D18__I2C3_SDA | PC,
  131. .gpio_mode = MX6DL_PAD_EIM_D18__GPIO3_IO18 | PC,
  132. .gp = IMX_GPIO_NR(3, 18)
  133. }
  134. };
  135. #endif
  136. static iomux_v3_cfg_t const i2c3_pads[] = {
  137. IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  138. };
  139. static iomux_v3_cfg_t const port_exp[] = {
  140. IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  141. };
  142. #ifdef CONFIG_MTD_NOR_FLASH
  143. static iomux_v3_cfg_t const eimnor_pads[] = {
  144. IOMUX_PADS(PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  145. IOMUX_PADS(PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  146. IOMUX_PADS(PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  147. IOMUX_PADS(PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  148. IOMUX_PADS(PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  149. IOMUX_PADS(PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  150. IOMUX_PADS(PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  151. IOMUX_PADS(PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  152. IOMUX_PADS(PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  153. IOMUX_PADS(PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  154. IOMUX_PADS(PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  155. IOMUX_PADS(PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  156. IOMUX_PADS(PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  157. IOMUX_PADS(PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  158. IOMUX_PADS(PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  159. IOMUX_PADS(PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  160. IOMUX_PADS(PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  161. IOMUX_PADS(PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  162. IOMUX_PADS(PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  163. IOMUX_PADS(PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  164. IOMUX_PADS(PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  165. IOMUX_PADS(PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  166. IOMUX_PADS(PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  167. IOMUX_PADS(PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  168. IOMUX_PADS(PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  169. IOMUX_PADS(PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  170. IOMUX_PADS(PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  171. IOMUX_PADS(PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  172. IOMUX_PADS(PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  173. IOMUX_PADS(PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  174. IOMUX_PADS(PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  175. IOMUX_PADS(PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  176. IOMUX_PADS(PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  177. IOMUX_PADS(PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  178. IOMUX_PADS(PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  179. IOMUX_PADS(PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  180. IOMUX_PADS(PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  181. IOMUX_PADS(PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  182. IOMUX_PADS(PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  183. IOMUX_PADS(PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  184. IOMUX_PADS(PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  185. IOMUX_PADS(PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL)),
  186. IOMUX_PADS(PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  187. };
  188. static void eimnor_cs_setup(void)
  189. {
  190. struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
  191. writel(0x00020181, &weim_regs->cs0gcr1);
  192. writel(0x00000001, &weim_regs->cs0gcr2);
  193. writel(0x0a020000, &weim_regs->cs0rcr1);
  194. writel(0x0000c000, &weim_regs->cs0rcr2);
  195. writel(0x0804a240, &weim_regs->cs0wcr1);
  196. writel(0x00000120, &weim_regs->wcr);
  197. set_chipselect_size(CS0_128);
  198. }
  199. static void eim_clk_setup(void)
  200. {
  201. struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  202. int cscmr1, ccgr6;
  203. /* Turn off EIM clock */
  204. ccgr6 = readl(&imx_ccm->CCGR6);
  205. ccgr6 &= ~(0x3 << 10);
  206. writel(ccgr6, &imx_ccm->CCGR6);
  207. /*
  208. * Configure clk_eim_slow_sel = 00 --> derive clock from AXI clk root
  209. * and aclk_eim_slow_podf = 01 --> divide by 2
  210. * so that we can have EIM at the maximum clock of 132MHz
  211. */
  212. cscmr1 = readl(&imx_ccm->cscmr1);
  213. cscmr1 &= ~(MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK |
  214. MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK);
  215. cscmr1 |= (1 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET);
  216. writel(cscmr1, &imx_ccm->cscmr1);
  217. /* Turn on EIM clock */
  218. ccgr6 |= (0x3 << 10);
  219. writel(ccgr6, &imx_ccm->CCGR6);
  220. }
  221. static void setup_iomux_eimnor(void)
  222. {
  223. SETUP_IOMUX_PADS(eimnor_pads);
  224. gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
  225. eimnor_cs_setup();
  226. }
  227. #endif
  228. static void setup_iomux_enet(void)
  229. {
  230. SETUP_IOMUX_PADS(enet_pads);
  231. }
  232. static iomux_v3_cfg_t const usdhc3_pads[] = {
  233. IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  234. IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  235. IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  236. IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  237. IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  238. IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  239. IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  240. IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  241. IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  242. IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  243. IOMUX_PADS(PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  244. IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  245. };
  246. static void setup_iomux_uart(void)
  247. {
  248. SETUP_IOMUX_PADS(uart4_pads);
  249. }
  250. #ifdef CONFIG_FSL_ESDHC_IMX
  251. static struct fsl_esdhc_cfg usdhc_cfg[1] = {
  252. {USDHC3_BASE_ADDR},
  253. };
  254. int board_mmc_getcd(struct mmc *mmc)
  255. {
  256. gpio_direction_input(IMX_GPIO_NR(6, 15));
  257. return !gpio_get_value(IMX_GPIO_NR(6, 15));
  258. }
  259. int board_mmc_init(bd_t *bis)
  260. {
  261. SETUP_IOMUX_PADS(usdhc3_pads);
  262. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  263. return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  264. }
  265. #endif
  266. #ifdef CONFIG_NAND_MXS
  267. static iomux_v3_cfg_t gpmi_pads[] = {
  268. IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  269. IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  270. IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  271. IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0)),
  272. IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  273. IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  274. IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  275. IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  276. IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  277. IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  278. IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  279. IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  280. IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  281. IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  282. IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  283. IOMUX_PADS(PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL1)),
  284. };
  285. static void setup_gpmi_nand(void)
  286. {
  287. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  288. /* config gpmi nand iomux */
  289. SETUP_IOMUX_PADS(gpmi_pads);
  290. setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
  291. MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
  292. MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)));
  293. /* enable apbh clock gating */
  294. setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  295. }
  296. #endif
  297. static void setup_fec(void)
  298. {
  299. if (is_mx6dqp()) {
  300. /*
  301. * select ENET MAC0 TX clock from PLL
  302. */
  303. imx_iomux_set_gpr_register(5, 9, 1, 1);
  304. enable_fec_anatop_clock(0, ENET_125MHZ);
  305. }
  306. setup_iomux_enet();
  307. }
  308. int board_eth_init(bd_t *bis)
  309. {
  310. setup_fec();
  311. return cpu_eth_init(bis);
  312. }
  313. u32 get_board_rev(void)
  314. {
  315. int rev = nxp_board_rev();
  316. return (get_cpu_rev() & ~(0xF << 8)) | rev;
  317. }
  318. static int ar8031_phy_fixup(struct phy_device *phydev)
  319. {
  320. unsigned short val;
  321. /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
  322. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  323. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
  324. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
  325. val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
  326. val &= 0xffe3;
  327. val |= 0x18;
  328. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
  329. /* introduce tx clock delay */
  330. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
  331. val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
  332. val |= 0x0100;
  333. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
  334. return 0;
  335. }
  336. int board_phy_config(struct phy_device *phydev)
  337. {
  338. ar8031_phy_fixup(phydev);
  339. if (phydev->drv->config)
  340. phydev->drv->config(phydev);
  341. return 0;
  342. }
  343. #if defined(CONFIG_VIDEO_IPUV3)
  344. static void disable_lvds(struct display_info_t const *dev)
  345. {
  346. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  347. clrbits_le32(&iomux->gpr[2],
  348. IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
  349. IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
  350. }
  351. static void do_enable_hdmi(struct display_info_t const *dev)
  352. {
  353. disable_lvds(dev);
  354. imx_enable_hdmi_phy();
  355. }
  356. struct display_info_t const displays[] = {{
  357. .bus = -1,
  358. .addr = 0,
  359. .pixfmt = IPU_PIX_FMT_RGB666,
  360. .detect = NULL,
  361. .enable = NULL,
  362. .mode = {
  363. .name = "Hannstar-XGA",
  364. .refresh = 60,
  365. .xres = 1024,
  366. .yres = 768,
  367. .pixclock = 15385,
  368. .left_margin = 220,
  369. .right_margin = 40,
  370. .upper_margin = 21,
  371. .lower_margin = 7,
  372. .hsync_len = 60,
  373. .vsync_len = 10,
  374. .sync = FB_SYNC_EXT,
  375. .vmode = FB_VMODE_NONINTERLACED
  376. } }, {
  377. .bus = -1,
  378. .addr = 0,
  379. .pixfmt = IPU_PIX_FMT_RGB24,
  380. .detect = detect_hdmi,
  381. .enable = do_enable_hdmi,
  382. .mode = {
  383. .name = "HDMI",
  384. .refresh = 60,
  385. .xres = 1024,
  386. .yres = 768,
  387. .pixclock = 15385,
  388. .left_margin = 220,
  389. .right_margin = 40,
  390. .upper_margin = 21,
  391. .lower_margin = 7,
  392. .hsync_len = 60,
  393. .vsync_len = 10,
  394. .sync = FB_SYNC_EXT,
  395. .vmode = FB_VMODE_NONINTERLACED,
  396. } } };
  397. size_t display_count = ARRAY_SIZE(displays);
  398. iomux_v3_cfg_t const backlight_pads[] = {
  399. IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  400. };
  401. static void setup_iomux_backlight(void)
  402. {
  403. gpio_request(IMX_GPIO_NR(2, 9), "backlight");
  404. gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
  405. SETUP_IOMUX_PADS(backlight_pads);
  406. }
  407. static void setup_display(void)
  408. {
  409. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  410. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  411. int reg;
  412. setup_iomux_backlight();
  413. enable_ipu_clock();
  414. imx_setup_hdmi();
  415. /* Turn on LDB_DI0 and LDB_DI1 clocks */
  416. reg = readl(&mxc_ccm->CCGR3);
  417. reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
  418. writel(reg, &mxc_ccm->CCGR3);
  419. /* Set LDB_DI0 and LDB_DI1 clk select to 3b'011 */
  420. reg = readl(&mxc_ccm->cs2cdr);
  421. reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
  422. MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
  423. reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
  424. (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
  425. writel(reg, &mxc_ccm->cs2cdr);
  426. reg = readl(&mxc_ccm->cscmr2);
  427. reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
  428. writel(reg, &mxc_ccm->cscmr2);
  429. reg = readl(&mxc_ccm->chsccdr);
  430. reg |= (CHSCCDR_CLK_SEL_LDB_DI0
  431. << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  432. reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
  433. MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
  434. writel(reg, &mxc_ccm->chsccdr);
  435. reg = IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
  436. IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
  437. IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
  438. IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
  439. IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
  440. IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
  441. IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
  442. IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED;
  443. writel(reg, &iomux->gpr[2]);
  444. reg = readl(&iomux->gpr[3]);
  445. reg &= ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
  446. IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
  447. reg |= (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
  448. IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
  449. (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
  450. IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET);
  451. writel(reg, &iomux->gpr[3]);
  452. }
  453. #endif /* CONFIG_VIDEO_IPUV3 */
  454. /*
  455. * Do not overwrite the console
  456. * Use always serial for U-Boot console
  457. */
  458. int overwrite_console(void)
  459. {
  460. return 1;
  461. }
  462. int board_early_init_f(void)
  463. {
  464. setup_iomux_uart();
  465. #ifdef CONFIG_NAND_MXS
  466. setup_gpmi_nand();
  467. #endif
  468. #ifdef CONFIG_MTD_NOR_FLASH
  469. eim_clk_setup();
  470. #endif
  471. return 0;
  472. }
  473. int board_init(void)
  474. {
  475. /* address of boot parameters */
  476. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  477. /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
  478. if (is_mx6dq() || is_mx6dqp())
  479. setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
  480. else
  481. setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
  482. /* I2C 3 Steer */
  483. gpio_request(IMX_GPIO_NR(5, 4), "steer logic");
  484. gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
  485. SETUP_IOMUX_PADS(i2c3_pads);
  486. #ifndef CONFIG_SYS_FLASH_CFI
  487. if (is_mx6dq() || is_mx6dqp())
  488. setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
  489. else
  490. setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
  491. #endif
  492. gpio_request(IMX_GPIO_NR(1, 15), "expander en");
  493. gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
  494. SETUP_IOMUX_PADS(port_exp);
  495. #ifdef CONFIG_VIDEO_IPUV3
  496. setup_display();
  497. #endif
  498. #ifdef CONFIG_MTD_NOR_FLASH
  499. setup_iomux_eimnor();
  500. #endif
  501. return 0;
  502. }
  503. #ifdef CONFIG_MXC_SPI
  504. int board_spi_cs_gpio(unsigned bus, unsigned cs)
  505. {
  506. return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
  507. }
  508. #endif
  509. int power_init_board(void)
  510. {
  511. struct pmic *p;
  512. unsigned int value;
  513. p = pfuze_common_init(I2C_PMIC);
  514. if (!p)
  515. return -ENODEV;
  516. if (is_mx6dqp()) {
  517. /* set SW2 staby volatage 0.975V*/
  518. pmic_reg_read(p, PFUZE100_SW2STBY, &value);
  519. value &= ~0x3f;
  520. value |= 0x17;
  521. pmic_reg_write(p, PFUZE100_SW2STBY, value);
  522. }
  523. return pfuze_mode_init(p, APS_PFM);
  524. }
  525. #ifdef CONFIG_CMD_BMODE
  526. static const struct boot_mode board_boot_modes[] = {
  527. /* 4 bit bus width */
  528. {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  529. {NULL, 0},
  530. };
  531. #endif
  532. int board_late_init(void)
  533. {
  534. #ifdef CONFIG_CMD_BMODE
  535. add_board_boot_modes(board_boot_modes);
  536. #endif
  537. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  538. env_set("board_name", "SABREAUTO");
  539. if (is_mx6dqp())
  540. env_set("board_rev", "MX6QP");
  541. else if (is_mx6dq())
  542. env_set("board_rev", "MX6Q");
  543. else if (is_mx6sdl())
  544. env_set("board_rev", "MX6DL");
  545. #endif
  546. return 0;
  547. }
  548. int checkboard(void)
  549. {
  550. printf("Board: MX6Q-Sabreauto rev%c\n", nxp_board_rev_string());
  551. return 0;
  552. }
  553. #ifdef CONFIG_USB_EHCI_MX6
  554. int board_ehci_hcd_init(int port)
  555. {
  556. switch (port) {
  557. case 0:
  558. /*
  559. * Set daisy chain for otg_pin_id on 6q.
  560. * For 6dl, this bit is reserved.
  561. */
  562. imx_iomux_set_gpr_register(1, 13, 1, 0);
  563. break;
  564. case 1:
  565. break;
  566. default:
  567. printf("MXC USB port %d not yet supported\n", port);
  568. return -EINVAL;
  569. }
  570. return 0;
  571. }
  572. #endif
  573. #ifdef CONFIG_SPL_BUILD
  574. #include <asm/arch/mx6-ddr.h>
  575. #include <spl.h>
  576. #include <linux/libfdt.h>
  577. #ifdef CONFIG_SPL_OS_BOOT
  578. int spl_start_uboot(void)
  579. {
  580. return 0;
  581. }
  582. #endif
  583. static void ccgr_init(void)
  584. {
  585. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  586. writel(0x00C03F3F, &ccm->CCGR0);
  587. writel(0x0030FC03, &ccm->CCGR1);
  588. writel(0x0FFFC000, &ccm->CCGR2);
  589. writel(0x3FF00000, &ccm->CCGR3);
  590. writel(0x00FFF300, &ccm->CCGR4);
  591. writel(0x0F0000C3, &ccm->CCGR5);
  592. writel(0x000003FF, &ccm->CCGR6);
  593. }
  594. static int mx6q_dcd_table[] = {
  595. 0x020e0798, 0x000C0000,
  596. 0x020e0758, 0x00000000,
  597. 0x020e0588, 0x00000030,
  598. 0x020e0594, 0x00000030,
  599. 0x020e056c, 0x00000030,
  600. 0x020e0578, 0x00000030,
  601. 0x020e074c, 0x00000030,
  602. 0x020e057c, 0x00000030,
  603. 0x020e058c, 0x00000000,
  604. 0x020e059c, 0x00000030,
  605. 0x020e05a0, 0x00000030,
  606. 0x020e078c, 0x00000030,
  607. 0x020e0750, 0x00020000,
  608. 0x020e05a8, 0x00000028,
  609. 0x020e05b0, 0x00000028,
  610. 0x020e0524, 0x00000028,
  611. 0x020e051c, 0x00000028,
  612. 0x020e0518, 0x00000028,
  613. 0x020e050c, 0x00000028,
  614. 0x020e05b8, 0x00000028,
  615. 0x020e05c0, 0x00000028,
  616. 0x020e0774, 0x00020000,
  617. 0x020e0784, 0x00000028,
  618. 0x020e0788, 0x00000028,
  619. 0x020e0794, 0x00000028,
  620. 0x020e079c, 0x00000028,
  621. 0x020e07a0, 0x00000028,
  622. 0x020e07a4, 0x00000028,
  623. 0x020e07a8, 0x00000028,
  624. 0x020e0748, 0x00000028,
  625. 0x020e05ac, 0x00000028,
  626. 0x020e05b4, 0x00000028,
  627. 0x020e0528, 0x00000028,
  628. 0x020e0520, 0x00000028,
  629. 0x020e0514, 0x00000028,
  630. 0x020e0510, 0x00000028,
  631. 0x020e05bc, 0x00000028,
  632. 0x020e05c4, 0x00000028,
  633. 0x021b0800, 0xa1390003,
  634. 0x021b080c, 0x001F001F,
  635. 0x021b0810, 0x001F001F,
  636. 0x021b480c, 0x001F001F,
  637. 0x021b4810, 0x001F001F,
  638. 0x021b083c, 0x43260335,
  639. 0x021b0840, 0x031A030B,
  640. 0x021b483c, 0x4323033B,
  641. 0x021b4840, 0x0323026F,
  642. 0x021b0848, 0x483D4545,
  643. 0x021b4848, 0x44433E48,
  644. 0x021b0850, 0x41444840,
  645. 0x021b4850, 0x4835483E,
  646. 0x021b081c, 0x33333333,
  647. 0x021b0820, 0x33333333,
  648. 0x021b0824, 0x33333333,
  649. 0x021b0828, 0x33333333,
  650. 0x021b481c, 0x33333333,
  651. 0x021b4820, 0x33333333,
  652. 0x021b4824, 0x33333333,
  653. 0x021b4828, 0x33333333,
  654. 0x021b08b8, 0x00000800,
  655. 0x021b48b8, 0x00000800,
  656. 0x021b0004, 0x00020036,
  657. 0x021b0008, 0x09444040,
  658. 0x021b000c, 0x8A8F7955,
  659. 0x021b0010, 0xFF328F64,
  660. 0x021b0014, 0x01FF00DB,
  661. 0x021b0018, 0x00001740,
  662. 0x021b001c, 0x00008000,
  663. 0x021b002c, 0x000026d2,
  664. 0x021b0030, 0x008F1023,
  665. 0x021b0040, 0x00000047,
  666. 0x021b0000, 0x841A0000,
  667. 0x021b001c, 0x04088032,
  668. 0x021b001c, 0x00008033,
  669. 0x021b001c, 0x00048031,
  670. 0x021b001c, 0x09408030,
  671. 0x021b001c, 0x04008040,
  672. 0x021b0020, 0x00005800,
  673. 0x021b0818, 0x00011117,
  674. 0x021b4818, 0x00011117,
  675. 0x021b0004, 0x00025576,
  676. 0x021b0404, 0x00011006,
  677. 0x021b001c, 0x00000000,
  678. 0x020c4068, 0x00C03F3F,
  679. 0x020c406c, 0x0030FC03,
  680. 0x020c4070, 0x0FFFC000,
  681. 0x020c4074, 0x3FF00000,
  682. 0x020c4078, 0xFFFFF300,
  683. 0x020c407c, 0x0F0000F3,
  684. 0x020c4080, 0x00000FFF,
  685. 0x020e0010, 0xF00000CF,
  686. 0x020e0018, 0x007F007F,
  687. 0x020e001c, 0x007F007F,
  688. };
  689. static int mx6qp_dcd_table[] = {
  690. 0x020e0798, 0x000C0000,
  691. 0x020e0758, 0x00000000,
  692. 0x020e0588, 0x00000030,
  693. 0x020e0594, 0x00000030,
  694. 0x020e056c, 0x00000030,
  695. 0x020e0578, 0x00000030,
  696. 0x020e074c, 0x00000030,
  697. 0x020e057c, 0x00000030,
  698. 0x020e058c, 0x00000000,
  699. 0x020e059c, 0x00000030,
  700. 0x020e05a0, 0x00000030,
  701. 0x020e078c, 0x00000030,
  702. 0x020e0750, 0x00020000,
  703. 0x020e05a8, 0x00000030,
  704. 0x020e05b0, 0x00000030,
  705. 0x020e0524, 0x00000030,
  706. 0x020e051c, 0x00000030,
  707. 0x020e0518, 0x00000030,
  708. 0x020e050c, 0x00000030,
  709. 0x020e05b8, 0x00000030,
  710. 0x020e05c0, 0x00000030,
  711. 0x020e0774, 0x00020000,
  712. 0x020e0784, 0x00000030,
  713. 0x020e0788, 0x00000030,
  714. 0x020e0794, 0x00000030,
  715. 0x020e079c, 0x00000030,
  716. 0x020e07a0, 0x00000030,
  717. 0x020e07a4, 0x00000030,
  718. 0x020e07a8, 0x00000030,
  719. 0x020e0748, 0x00000030,
  720. 0x020e05ac, 0x00000030,
  721. 0x020e05b4, 0x00000030,
  722. 0x020e0528, 0x00000030,
  723. 0x020e0520, 0x00000030,
  724. 0x020e0514, 0x00000030,
  725. 0x020e0510, 0x00000030,
  726. 0x020e05bc, 0x00000030,
  727. 0x020e05c4, 0x00000030,
  728. 0x021b0800, 0xa1390003,
  729. 0x021b080c, 0x001b001e,
  730. 0x021b0810, 0x002e0029,
  731. 0x021b480c, 0x001b002a,
  732. 0x021b4810, 0x0019002c,
  733. 0x021b083c, 0x43240334,
  734. 0x021b0840, 0x0324031a,
  735. 0x021b483c, 0x43340344,
  736. 0x021b4840, 0x03280276,
  737. 0x021b0848, 0x44383A3E,
  738. 0x021b4848, 0x3C3C3846,
  739. 0x021b0850, 0x2e303230,
  740. 0x021b4850, 0x38283E34,
  741. 0x021b081c, 0x33333333,
  742. 0x021b0820, 0x33333333,
  743. 0x021b0824, 0x33333333,
  744. 0x021b0828, 0x33333333,
  745. 0x021b481c, 0x33333333,
  746. 0x021b4820, 0x33333333,
  747. 0x021b4824, 0x33333333,
  748. 0x021b4828, 0x33333333,
  749. 0x021b08c0, 0x24912492,
  750. 0x021b48c0, 0x24912492,
  751. 0x021b08b8, 0x00000800,
  752. 0x021b48b8, 0x00000800,
  753. 0x021b0004, 0x00020036,
  754. 0x021b0008, 0x09444040,
  755. 0x021b000c, 0x898E7955,
  756. 0x021b0010, 0xFF328F64,
  757. 0x021b0014, 0x01FF00DB,
  758. 0x021b0018, 0x00001740,
  759. 0x021b001c, 0x00008000,
  760. 0x021b002c, 0x000026d2,
  761. 0x021b0030, 0x008E1023,
  762. 0x021b0040, 0x00000047,
  763. 0x021b0400, 0x14420000,
  764. 0x021b0000, 0x841A0000,
  765. 0x00bb0008, 0x00000004,
  766. 0x00bb000c, 0x2891E41A,
  767. 0x00bb0038, 0x00000564,
  768. 0x00bb0014, 0x00000040,
  769. 0x00bb0028, 0x00000020,
  770. 0x00bb002c, 0x00000020,
  771. 0x021b001c, 0x04088032,
  772. 0x021b001c, 0x00008033,
  773. 0x021b001c, 0x00048031,
  774. 0x021b001c, 0x09408030,
  775. 0x021b001c, 0x04008040,
  776. 0x021b0020, 0x00005800,
  777. 0x021b0818, 0x00011117,
  778. 0x021b4818, 0x00011117,
  779. 0x021b0004, 0x00025576,
  780. 0x021b0404, 0x00011006,
  781. 0x021b001c, 0x00000000,
  782. 0x020c4068, 0x00C03F3F,
  783. 0x020c406c, 0x0030FC03,
  784. 0x020c4070, 0x0FFFC000,
  785. 0x020c4074, 0x3FF00000,
  786. 0x020c4078, 0xFFFFF300,
  787. 0x020c407c, 0x0F0000F3,
  788. 0x020c4080, 0x00000FFF,
  789. 0x020e0010, 0xF00000CF,
  790. 0x020e0018, 0x77177717,
  791. 0x020e001c, 0x77177717,
  792. };
  793. static int mx6dl_dcd_table[] = {
  794. 0x020e0774, 0x000C0000,
  795. 0x020e0754, 0x00000000,
  796. 0x020e04ac, 0x00000030,
  797. 0x020e04b0, 0x00000030,
  798. 0x020e0464, 0x00000030,
  799. 0x020e0490, 0x00000030,
  800. 0x020e074c, 0x00000030,
  801. 0x020e0494, 0x00000030,
  802. 0x020e04a0, 0x00000000,
  803. 0x020e04b4, 0x00000030,
  804. 0x020e04b8, 0x00000030,
  805. 0x020e076c, 0x00000030,
  806. 0x020e0750, 0x00020000,
  807. 0x020e04bc, 0x00000028,
  808. 0x020e04c0, 0x00000028,
  809. 0x020e04c4, 0x00000028,
  810. 0x020e04c8, 0x00000028,
  811. 0x020e04cc, 0x00000028,
  812. 0x020e04d0, 0x00000028,
  813. 0x020e04d4, 0x00000028,
  814. 0x020e04d8, 0x00000028,
  815. 0x020e0760, 0x00020000,
  816. 0x020e0764, 0x00000028,
  817. 0x020e0770, 0x00000028,
  818. 0x020e0778, 0x00000028,
  819. 0x020e077c, 0x00000028,
  820. 0x020e0780, 0x00000028,
  821. 0x020e0784, 0x00000028,
  822. 0x020e078c, 0x00000028,
  823. 0x020e0748, 0x00000028,
  824. 0x020e0470, 0x00000028,
  825. 0x020e0474, 0x00000028,
  826. 0x020e0478, 0x00000028,
  827. 0x020e047c, 0x00000028,
  828. 0x020e0480, 0x00000028,
  829. 0x020e0484, 0x00000028,
  830. 0x020e0488, 0x00000028,
  831. 0x020e048c, 0x00000028,
  832. 0x021b0800, 0xa1390003,
  833. 0x021b080c, 0x001F001F,
  834. 0x021b0810, 0x001F001F,
  835. 0x021b480c, 0x001F001F,
  836. 0x021b4810, 0x001F001F,
  837. 0x021b083c, 0x42190217,
  838. 0x021b0840, 0x017B017B,
  839. 0x021b483c, 0x4176017B,
  840. 0x021b4840, 0x015F016C,
  841. 0x021b0848, 0x4C4C4D4C,
  842. 0x021b4848, 0x4A4D4C48,
  843. 0x021b0850, 0x3F3F3F40,
  844. 0x021b4850, 0x3538382E,
  845. 0x021b081c, 0x33333333,
  846. 0x021b0820, 0x33333333,
  847. 0x021b0824, 0x33333333,
  848. 0x021b0828, 0x33333333,
  849. 0x021b481c, 0x33333333,
  850. 0x021b4820, 0x33333333,
  851. 0x021b4824, 0x33333333,
  852. 0x021b4828, 0x33333333,
  853. 0x021b08b8, 0x00000800,
  854. 0x021b48b8, 0x00000800,
  855. 0x021b0004, 0x00020025,
  856. 0x021b0008, 0x00333030,
  857. 0x021b000c, 0x676B5313,
  858. 0x021b0010, 0xB66E8B63,
  859. 0x021b0014, 0x01FF00DB,
  860. 0x021b0018, 0x00001740,
  861. 0x021b001c, 0x00008000,
  862. 0x021b002c, 0x000026d2,
  863. 0x021b0030, 0x006B1023,
  864. 0x021b0040, 0x00000047,
  865. 0x021b0000, 0x841A0000,
  866. 0x021b001c, 0x04008032,
  867. 0x021b001c, 0x00008033,
  868. 0x021b001c, 0x00048031,
  869. 0x021b001c, 0x05208030,
  870. 0x021b001c, 0x04008040,
  871. 0x021b0020, 0x00005800,
  872. 0x021b0818, 0x00011117,
  873. 0x021b4818, 0x00011117,
  874. 0x021b0004, 0x00025565,
  875. 0x021b0404, 0x00011006,
  876. 0x021b001c, 0x00000000,
  877. 0x020c4068, 0x00C03F3F,
  878. 0x020c406c, 0x0030FC03,
  879. 0x020c4070, 0x0FFFC000,
  880. 0x020c4074, 0x3FF00000,
  881. 0x020c4078, 0xFFFFF300,
  882. 0x020c407c, 0x0F0000C3,
  883. 0x020c4080, 0x00000FFF,
  884. 0x020e0010, 0xF00000CF,
  885. 0x020e0018, 0x007F007F,
  886. 0x020e001c, 0x007F007F,
  887. };
  888. static void ddr_init(int *table, int size)
  889. {
  890. int i;
  891. for (i = 0; i < size / 2 ; i++)
  892. writel(table[2 * i + 1], table[2 * i]);
  893. }
  894. static void spl_dram_init(void)
  895. {
  896. if (is_mx6dq())
  897. ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
  898. else if (is_mx6dqp())
  899. ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
  900. else if (is_mx6sdl())
  901. ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
  902. }
  903. void board_init_f(ulong dummy)
  904. {
  905. /* DDR initialization */
  906. spl_dram_init();
  907. /* setup AIPS and disable watchdog */
  908. arch_cpu_init();
  909. ccgr_init();
  910. gpr_init();
  911. /* iomux and setup of i2c */
  912. board_early_init_f();
  913. /* setup GP timer */
  914. timer_init();
  915. /* UART clocks enabled and gd valid - init serial console */
  916. preloader_console_init();
  917. /* Clear the BSS. */
  918. memset(__bss_start, 0, __bss_end - __bss_start);
  919. /* load/boot image from boot device */
  920. board_init_r(NULL, 0);
  921. }
  922. #endif
  923. #ifdef CONFIG_SPL_LOAD_FIT
  924. int board_fit_config_name_match(const char *name)
  925. {
  926. if (is_mx6dq()) {
  927. if (!strcmp(name, "imx6q-sabreauto"))
  928. return 0;
  929. } else if (is_mx6dqp()) {
  930. if (!strcmp(name, "imx6qp-sabreauto"))
  931. return 0;
  932. } else if (is_mx6dl()) {
  933. if (!strcmp(name, "imx6dl-sabreauto"))
  934. return 0;
  935. }
  936. return -1;
  937. }
  938. #endif