mx53loco.c 9.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2011 Freescale Semiconductor, Inc.
  4. * Jason Liu <r64343@freescale.com>
  5. */
  6. #include <common.h>
  7. #include <asm/io.h>
  8. #include <asm/arch/imx-regs.h>
  9. #include <asm/arch/sys_proto.h>
  10. #include <asm/arch/crm_regs.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/iomux-mx53.h>
  13. #include <asm/arch/clock.h>
  14. #include <env.h>
  15. #include <linux/errno.h>
  16. #include <asm/mach-imx/mx5_video.h>
  17. #include <netdev.h>
  18. #include <i2c.h>
  19. #include <input.h>
  20. #include <mmc.h>
  21. #include <fsl_esdhc_imx.h>
  22. #include <asm/gpio.h>
  23. #include <power/pmic.h>
  24. #include <dialog_pmic.h>
  25. #include <fsl_pmic.h>
  26. #include <linux/fb.h>
  27. #include <ipu_pixfmt.h>
  28. #define MX53LOCO_LCD_POWER IMX_GPIO_NR(3, 24)
  29. DECLARE_GLOBAL_DATA_PTR;
  30. u32 get_board_rev(void)
  31. {
  32. struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
  33. struct fuse_bank *bank = &iim->bank[0];
  34. struct fuse_bank0_regs *fuse =
  35. (struct fuse_bank0_regs *)bank->fuse_regs;
  36. int rev = readl(&fuse->gp[6]);
  37. if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR))
  38. rev = 0;
  39. return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
  40. }
  41. #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
  42. PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
  43. static void setup_iomux_uart(void)
  44. {
  45. static const iomux_v3_cfg_t uart_pads[] = {
  46. NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
  47. NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
  48. };
  49. imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  50. }
  51. #ifdef CONFIG_USB_EHCI_MX5
  52. int board_ehci_hcd_init(int port)
  53. {
  54. /* request VBUS power enable pin, GPIO7_8 */
  55. imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8);
  56. gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
  57. return 0;
  58. }
  59. #endif
  60. static void setup_iomux_fec(void)
  61. {
  62. static const iomux_v3_cfg_t fec_pads[] = {
  63. NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
  64. PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
  65. NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
  66. NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
  67. PAD_CTL_HYS | PAD_CTL_PKE),
  68. NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
  69. PAD_CTL_HYS | PAD_CTL_PKE),
  70. NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
  71. NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
  72. NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
  73. NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
  74. PAD_CTL_HYS | PAD_CTL_PKE),
  75. NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
  76. PAD_CTL_HYS | PAD_CTL_PKE),
  77. NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
  78. PAD_CTL_HYS | PAD_CTL_PKE),
  79. };
  80. imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
  81. }
  82. #ifdef CONFIG_FSL_ESDHC_IMX
  83. struct fsl_esdhc_cfg esdhc_cfg[2] = {
  84. {MMC_SDHC1_BASE_ADDR},
  85. {MMC_SDHC3_BASE_ADDR},
  86. };
  87. int board_mmc_getcd(struct mmc *mmc)
  88. {
  89. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  90. int ret;
  91. imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11);
  92. gpio_direction_input(IMX_GPIO_NR(3, 11));
  93. imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
  94. gpio_direction_input(IMX_GPIO_NR(3, 13));
  95. if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
  96. ret = !gpio_get_value(IMX_GPIO_NR(3, 13));
  97. else
  98. ret = !gpio_get_value(IMX_GPIO_NR(3, 11));
  99. return ret;
  100. }
  101. #define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
  102. PAD_CTL_PUS_100K_UP)
  103. #define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
  104. PAD_CTL_DSE_HIGH)
  105. int board_mmc_init(bd_t *bis)
  106. {
  107. static const iomux_v3_cfg_t sd1_pads[] = {
  108. NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
  109. NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
  110. NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
  111. NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
  112. NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
  113. NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
  114. MX53_PAD_EIM_DA13__GPIO3_13,
  115. };
  116. static const iomux_v3_cfg_t sd2_pads[] = {
  117. NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
  118. SD_CMD_PAD_CTRL),
  119. NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
  120. NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
  121. NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
  122. NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
  123. NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
  124. NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
  125. NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
  126. NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
  127. NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
  128. MX53_PAD_EIM_DA11__GPIO3_11,
  129. };
  130. u32 index;
  131. int ret;
  132. esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  133. esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  134. for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
  135. switch (index) {
  136. case 0:
  137. imx_iomux_v3_setup_multiple_pads(sd1_pads,
  138. ARRAY_SIZE(sd1_pads));
  139. break;
  140. case 1:
  141. imx_iomux_v3_setup_multiple_pads(sd2_pads,
  142. ARRAY_SIZE(sd2_pads));
  143. break;
  144. default:
  145. printf("Warning: you configured more ESDHC controller"
  146. "(%d) as supported by the board(2)\n",
  147. CONFIG_SYS_FSL_ESDHC_NUM);
  148. return -EINVAL;
  149. }
  150. ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
  151. if (ret)
  152. return ret;
  153. }
  154. return 0;
  155. }
  156. #endif
  157. #define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
  158. PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
  159. static void setup_iomux_i2c(void)
  160. {
  161. static const iomux_v3_cfg_t i2c1_pads[] = {
  162. NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
  163. NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
  164. };
  165. imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
  166. }
  167. static int power_init(void)
  168. {
  169. unsigned int val;
  170. int ret;
  171. struct pmic *p;
  172. if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) {
  173. ret = pmic_dialog_init(I2C_PMIC);
  174. if (ret)
  175. return ret;
  176. p = pmic_get("DIALOG_PMIC");
  177. if (!p)
  178. return -ENODEV;
  179. env_set("fdt_file", "imx53-qsb.dtb");
  180. /* Set VDDA to 1.25V */
  181. val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V;
  182. ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);
  183. if (ret) {
  184. printf("Writing to BUCKCORE_REG failed: %d\n", ret);
  185. return ret;
  186. }
  187. pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
  188. val |= DA9052_SUPPLY_VBCOREGO;
  189. ret = pmic_reg_write(p, DA9053_SUPPLY_REG, val);
  190. if (ret) {
  191. printf("Writing to SUPPLY_REG failed: %d\n", ret);
  192. return ret;
  193. }
  194. /* Set Vcc peripheral to 1.30V */
  195. ret = pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
  196. if (ret) {
  197. printf("Writing to BUCKPRO_REG failed: %d\n", ret);
  198. return ret;
  199. }
  200. ret = pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
  201. if (ret) {
  202. printf("Writing to SUPPLY_REG failed: %d\n", ret);
  203. return ret;
  204. }
  205. return ret;
  206. }
  207. if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
  208. ret = pmic_init(I2C_0);
  209. if (ret)
  210. return ret;
  211. p = pmic_get("FSL_PMIC");
  212. if (!p)
  213. return -ENODEV;
  214. env_set("fdt_file", "imx53-qsrb.dtb");
  215. /* Set VDDGP to 1.25V for 1GHz on SW1 */
  216. pmic_reg_read(p, REG_SW_0, &val);
  217. val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708;
  218. ret = pmic_reg_write(p, REG_SW_0, val);
  219. if (ret) {
  220. printf("Writing to REG_SW_0 failed: %d\n", ret);
  221. return ret;
  222. }
  223. /* Set VCC as 1.30V on SW2 */
  224. pmic_reg_read(p, REG_SW_1, &val);
  225. val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708;
  226. ret = pmic_reg_write(p, REG_SW_1, val);
  227. if (ret) {
  228. printf("Writing to REG_SW_1 failed: %d\n", ret);
  229. return ret;
  230. }
  231. /* Set global reset timer to 4s */
  232. pmic_reg_read(p, REG_POWER_CTL2, &val);
  233. val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708;
  234. ret = pmic_reg_write(p, REG_POWER_CTL2, val);
  235. if (ret) {
  236. printf("Writing to REG_POWER_CTL2 failed: %d\n", ret);
  237. return ret;
  238. }
  239. /* Set VUSBSEL and VUSBEN for USB PHY supply*/
  240. pmic_reg_read(p, REG_MODE_0, &val);
  241. val |= (VUSBSEL_MC34708 | VUSBEN_MC34708);
  242. ret = pmic_reg_write(p, REG_MODE_0, val);
  243. if (ret) {
  244. printf("Writing to REG_MODE_0 failed: %d\n", ret);
  245. return ret;
  246. }
  247. /* Set SWBST to 5V in auto mode */
  248. val = SWBST_AUTO;
  249. ret = pmic_reg_write(p, SWBST_CTRL, val);
  250. if (ret) {
  251. printf("Writing to SWBST_CTRL failed: %d\n", ret);
  252. return ret;
  253. }
  254. return ret;
  255. }
  256. return -1;
  257. }
  258. static void clock_1GHz(void)
  259. {
  260. int ret;
  261. u32 ref_clk = MXC_HCLK;
  262. /*
  263. * After increasing voltage to 1.25V, we can switch
  264. * CPU clock to 1GHz and DDR to 400MHz safely
  265. */
  266. ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
  267. if (ret)
  268. printf("CPU: Switch CPU clock to 1GHZ failed\n");
  269. ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
  270. ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
  271. if (ret)
  272. printf("CPU: Switch DDR clock to 400MHz failed\n");
  273. }
  274. int board_early_init_f(void)
  275. {
  276. setup_iomux_uart();
  277. setup_iomux_fec();
  278. setup_iomux_lcd();
  279. return 0;
  280. }
  281. /*
  282. * Do not overwrite the console
  283. * Use always serial for U-Boot console
  284. */
  285. int overwrite_console(void)
  286. {
  287. return 1;
  288. }
  289. int board_init(void)
  290. {
  291. gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  292. mxc_set_sata_internal_clock();
  293. setup_iomux_i2c();
  294. return 0;
  295. }
  296. int board_late_init(void)
  297. {
  298. if (!power_init())
  299. clock_1GHz();
  300. return 0;
  301. }
  302. int checkboard(void)
  303. {
  304. puts("Board: MX53 LOCO\n");
  305. return 0;
  306. }