ls2080ardb.c 10.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2015 Freescale Semiconductor
  4. * Copyright 2017 NXP
  5. */
  6. #include <common.h>
  7. #include <env.h>
  8. #include <malloc.h>
  9. #include <errno.h>
  10. #include <netdev.h>
  11. #include <fsl_ifc.h>
  12. #include <fsl_ddr.h>
  13. #include <asm/io.h>
  14. #include <hwconfig.h>
  15. #include <fdt_support.h>
  16. #include <linux/libfdt.h>
  17. #include <fsl-mc/fsl_mc.h>
  18. #include <environment.h>
  19. #include <efi_loader.h>
  20. #include <i2c.h>
  21. #include <asm/arch/mmu.h>
  22. #include <asm/arch/soc.h>
  23. #include <asm/arch/ppa.h>
  24. #include <fsl_sec.h>
  25. #ifdef CONFIG_FSL_QIXIS
  26. #include "../common/qixis.h"
  27. #include "ls2080ardb_qixis.h"
  28. #endif
  29. #include "../common/vid.h"
  30. #define PIN_MUX_SEL_SDHC 0x00
  31. #define PIN_MUX_SEL_DSPI 0x0a
  32. #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
  33. DECLARE_GLOBAL_DATA_PTR;
  34. enum {
  35. MUX_TYPE_SDHC,
  36. MUX_TYPE_DSPI,
  37. };
  38. unsigned long long get_qixis_addr(void)
  39. {
  40. unsigned long long addr;
  41. if (gd->flags & GD_FLG_RELOC)
  42. addr = QIXIS_BASE_PHYS;
  43. else
  44. addr = QIXIS_BASE_PHYS_EARLY;
  45. /*
  46. * IFC address under 256MB is mapped to 0x30000000, any address above
  47. * is mapped to 0x5_10000000 up to 4GB.
  48. */
  49. addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
  50. return addr;
  51. }
  52. int checkboard(void)
  53. {
  54. #ifdef CONFIG_FSL_QIXIS
  55. u8 sw;
  56. #endif
  57. char buf[15];
  58. cpu_name(buf);
  59. printf("Board: %s-RDB, ", buf);
  60. #ifdef CONFIG_TARGET_LS2081ARDB
  61. #ifdef CONFIG_FSL_QIXIS
  62. sw = QIXIS_READ(arch);
  63. printf("Board version: %c, ", (sw & 0xf) + 'A');
  64. sw = QIXIS_READ(brdcfg[0]);
  65. sw = (sw >> QIXIS_QMAP_SHIFT) & QIXIS_QMAP_MASK;
  66. switch (sw) {
  67. case 0:
  68. puts("boot from QSPI DEV#0\n");
  69. puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
  70. break;
  71. case 1:
  72. puts("boot from QSPI DEV#1\n");
  73. puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
  74. break;
  75. case 2:
  76. puts("boot from QSPI EMU\n");
  77. puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
  78. break;
  79. case 3:
  80. puts("boot from QSPI EMU\n");
  81. puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
  82. break;
  83. case 4:
  84. puts("boot from QSPI DEV#0\n");
  85. puts("QSPI_CSA_1 mapped to QSPI EMU\n");
  86. break;
  87. default:
  88. printf("invalid setting of SW%u\n", sw);
  89. break;
  90. }
  91. printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
  92. #endif
  93. puts("SERDES1 Reference : ");
  94. printf("Clock1 = 100MHz ");
  95. printf("Clock2 = 161.13MHz");
  96. #else
  97. #ifdef CONFIG_FSL_QIXIS
  98. sw = QIXIS_READ(arch);
  99. printf("Board Arch: V%d, ", sw >> 4);
  100. printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
  101. sw = QIXIS_READ(brdcfg[0]);
  102. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  103. if (sw < 0x8)
  104. printf("vBank: %d\n", sw);
  105. else if (sw == 0x9)
  106. puts("NAND\n");
  107. else
  108. printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  109. printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
  110. #endif
  111. puts("SERDES1 Reference : ");
  112. printf("Clock1 = 156.25MHz ");
  113. printf("Clock2 = 156.25MHz");
  114. #endif
  115. puts("\nSERDES2 Reference : ");
  116. printf("Clock1 = 100MHz ");
  117. printf("Clock2 = 100MHz\n");
  118. return 0;
  119. }
  120. unsigned long get_board_sys_clk(void)
  121. {
  122. #ifdef CONFIG_FSL_QIXIS
  123. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  124. switch (sysclk_conf & 0x0F) {
  125. case QIXIS_SYSCLK_83:
  126. return 83333333;
  127. case QIXIS_SYSCLK_100:
  128. return 100000000;
  129. case QIXIS_SYSCLK_125:
  130. return 125000000;
  131. case QIXIS_SYSCLK_133:
  132. return 133333333;
  133. case QIXIS_SYSCLK_150:
  134. return 150000000;
  135. case QIXIS_SYSCLK_160:
  136. return 160000000;
  137. case QIXIS_SYSCLK_166:
  138. return 166666666;
  139. }
  140. #endif
  141. return 100000000;
  142. }
  143. int select_i2c_ch_pca9547(u8 ch)
  144. {
  145. int ret;
  146. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  147. if (ret) {
  148. puts("PCA: failed to select proper channel\n");
  149. return ret;
  150. }
  151. return 0;
  152. }
  153. int i2c_multiplexer_select_vid_channel(u8 channel)
  154. {
  155. return select_i2c_ch_pca9547(channel);
  156. }
  157. int config_board_mux(int ctrl_type)
  158. {
  159. #ifdef CONFIG_FSL_QIXIS
  160. u8 reg5;
  161. reg5 = QIXIS_READ(brdcfg[5]);
  162. switch (ctrl_type) {
  163. case MUX_TYPE_SDHC:
  164. reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
  165. break;
  166. case MUX_TYPE_DSPI:
  167. reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
  168. break;
  169. default:
  170. printf("Wrong mux interface type\n");
  171. return -1;
  172. }
  173. QIXIS_WRITE(brdcfg[5], reg5);
  174. #endif
  175. return 0;
  176. }
  177. int board_init(void)
  178. {
  179. #ifdef CONFIG_FSL_MC_ENET
  180. u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
  181. #endif
  182. init_final_memctl_regs();
  183. #ifdef CONFIG_ENV_IS_NOWHERE
  184. gd->env_addr = (ulong)&default_environment[0];
  185. #endif
  186. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  187. #ifdef CONFIG_FSL_QIXIS
  188. QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
  189. #endif
  190. #ifdef CONFIG_FSL_CAAM
  191. sec_init();
  192. #endif
  193. #ifdef CONFIG_FSL_LS_PPA
  194. ppa_init();
  195. #endif
  196. #ifdef CONFIG_FSL_MC_ENET
  197. /* invert AQR405 IRQ pins polarity */
  198. out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
  199. #endif
  200. #ifdef CONFIG_FSL_CAAM
  201. sec_init();
  202. #endif
  203. return 0;
  204. }
  205. int board_early_init_f(void)
  206. {
  207. #ifdef CONFIG_SYS_I2C_EARLY_INIT
  208. i2c_early_init_f();
  209. #endif
  210. fsl_lsch3_early_init_f();
  211. return 0;
  212. }
  213. int misc_init_r(void)
  214. {
  215. char *env_hwconfig;
  216. u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
  217. u32 val;
  218. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  219. u32 svr = gur_in32(&gur->svr);
  220. val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
  221. env_hwconfig = env_get("hwconfig");
  222. if (hwconfig_f("dspi", env_hwconfig) &&
  223. DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
  224. config_board_mux(MUX_TYPE_DSPI);
  225. else
  226. config_board_mux(MUX_TYPE_SDHC);
  227. /*
  228. * LS2081ARDB RevF board has smart voltage translator
  229. * which needs to be programmed to enable high speed SD interface
  230. * by setting GPIO4_10 output to zero
  231. */
  232. #ifdef CONFIG_TARGET_LS2081ARDB
  233. out_le32(GPIO4_GPDIR_ADDR, (1 << 21 |
  234. in_le32(GPIO4_GPDIR_ADDR)));
  235. out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) &
  236. in_le32(GPIO4_GPDAT_ADDR)));
  237. #endif
  238. if (hwconfig("sdhc"))
  239. config_board_mux(MUX_TYPE_SDHC);
  240. if (adjust_vdd(0))
  241. printf("Warning: Adjusting core voltage failed.\n");
  242. /*
  243. * Default value of board env is based on filename which is
  244. * ls2080ardb. Modify board env for other supported SoCs
  245. */
  246. if ((SVR_SOC_VER(svr) == SVR_LS2088A) ||
  247. (SVR_SOC_VER(svr) == SVR_LS2048A))
  248. env_set("board", "ls2088ardb");
  249. else if ((SVR_SOC_VER(svr) == SVR_LS2081A) ||
  250. (SVR_SOC_VER(svr) == SVR_LS2041A))
  251. env_set("board", "ls2081ardb");
  252. return 0;
  253. }
  254. void detail_board_ddr_info(void)
  255. {
  256. puts("\nDDR ");
  257. print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
  258. print_ddr_info(0);
  259. #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  260. if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
  261. puts("\nDP-DDR ");
  262. print_size(gd->bd->bi_dram[2].size, "");
  263. print_ddr_info(CONFIG_DP_DDR_CTRL);
  264. }
  265. #endif
  266. }
  267. #if defined(CONFIG_ARCH_MISC_INIT)
  268. int arch_misc_init(void)
  269. {
  270. return 0;
  271. }
  272. #endif
  273. #ifdef CONFIG_FSL_MC_ENET
  274. void fdt_fixup_board_enet(void *fdt)
  275. {
  276. int offset;
  277. offset = fdt_path_offset(fdt, "/soc/fsl-mc");
  278. if (offset < 0)
  279. offset = fdt_path_offset(fdt, "/fsl-mc");
  280. if (offset < 0) {
  281. printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
  282. __func__, offset);
  283. return;
  284. }
  285. if (get_mc_boot_status() == 0 &&
  286. (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
  287. fdt_status_okay(fdt, offset);
  288. else
  289. fdt_status_fail(fdt, offset);
  290. }
  291. void board_quiesce_devices(void)
  292. {
  293. fsl_mc_ldpaa_exit(gd->bd);
  294. }
  295. #endif
  296. #ifdef CONFIG_OF_BOARD_SETUP
  297. void fsl_fdt_fixup_flash(void *fdt)
  298. {
  299. int offset;
  300. #ifdef CONFIG_TFABOOT
  301. u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
  302. u32 val;
  303. #endif
  304. /*
  305. * IFC and QSPI are muxed on board.
  306. * So disable IFC node in dts if QSPI is enabled or
  307. * disable QSPI node in dts in case QSPI is not enabled.
  308. */
  309. #ifdef CONFIG_TFABOOT
  310. enum boot_src src = get_boot_src();
  311. bool disable_ifc = false;
  312. switch (src) {
  313. case BOOT_SOURCE_IFC_NOR:
  314. disable_ifc = false;
  315. break;
  316. case BOOT_SOURCE_QSPI_NOR:
  317. disable_ifc = true;
  318. break;
  319. default:
  320. val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
  321. if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
  322. disable_ifc = true;
  323. break;
  324. }
  325. if (disable_ifc) {
  326. offset = fdt_path_offset(fdt, "/soc/ifc");
  327. if (offset < 0)
  328. offset = fdt_path_offset(fdt, "/ifc");
  329. } else {
  330. offset = fdt_path_offset(fdt, "/soc/quadspi");
  331. if (offset < 0)
  332. offset = fdt_path_offset(fdt, "/quadspi");
  333. }
  334. #else
  335. #ifdef CONFIG_FSL_QSPI
  336. offset = fdt_path_offset(fdt, "/soc/ifc");
  337. if (offset < 0)
  338. offset = fdt_path_offset(fdt, "/ifc");
  339. #else
  340. offset = fdt_path_offset(fdt, "/soc/quadspi");
  341. if (offset < 0)
  342. offset = fdt_path_offset(fdt, "/quadspi");
  343. #endif
  344. #endif
  345. if (offset < 0)
  346. return;
  347. fdt_status_disabled(fdt, offset);
  348. }
  349. int ft_board_setup(void *blob, bd_t *bd)
  350. {
  351. u64 base[CONFIG_NR_DRAM_BANKS];
  352. u64 size[CONFIG_NR_DRAM_BANKS];
  353. ft_cpu_setup(blob, bd);
  354. /* fixup DT for the two GPP DDR banks */
  355. base[0] = gd->bd->bi_dram[0].start;
  356. size[0] = gd->bd->bi_dram[0].size;
  357. base[1] = gd->bd->bi_dram[1].start;
  358. size[1] = gd->bd->bi_dram[1].size;
  359. #ifdef CONFIG_RESV_RAM
  360. /* reduce size if reserved memory is within this bank */
  361. if (gd->arch.resv_ram >= base[0] &&
  362. gd->arch.resv_ram < base[0] + size[0])
  363. size[0] = gd->arch.resv_ram - base[0];
  364. else if (gd->arch.resv_ram >= base[1] &&
  365. gd->arch.resv_ram < base[1] + size[1])
  366. size[1] = gd->arch.resv_ram - base[1];
  367. #endif
  368. fdt_fixup_memory_banks(blob, base, size, 2);
  369. fdt_fsl_mc_fixup_iommu_map_entry(blob);
  370. fsl_fdt_fixup_dr_usb(blob, bd);
  371. fsl_fdt_fixup_flash(blob);
  372. #ifdef CONFIG_FSL_MC_ENET
  373. fdt_fixup_board_enet(blob);
  374. #endif
  375. return 0;
  376. }
  377. #endif
  378. void qixis_dump_switch(void)
  379. {
  380. #ifdef CONFIG_FSL_QIXIS
  381. int i, nr_of_cfgsw;
  382. QIXIS_WRITE(cms[0], 0x00);
  383. nr_of_cfgsw = QIXIS_READ(cms[1]);
  384. puts("DIP switch settings dump:\n");
  385. for (i = 1; i <= nr_of_cfgsw; i++) {
  386. QIXIS_WRITE(cms[0], i);
  387. printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
  388. }
  389. #endif
  390. }
  391. /*
  392. * Board rev C and earlier has duplicated I2C addresses for 2nd controller.
  393. * Both slots has 0x54, resulting 2nd slot unusable.
  394. */
  395. void update_spd_address(unsigned int ctrl_num,
  396. unsigned int slot,
  397. unsigned int *addr)
  398. {
  399. #ifndef CONFIG_TARGET_LS2081ARDB
  400. #ifdef CONFIG_FSL_QIXIS
  401. u8 sw;
  402. sw = QIXIS_READ(arch);
  403. if ((sw & 0xf) < 0x3) {
  404. if (ctrl_num == 1 && slot == 0)
  405. *addr = SPD_EEPROM_ADDRESS4;
  406. else if (ctrl_num == 1 && slot == 1)
  407. *addr = SPD_EEPROM_ADDRESS3;
  408. }
  409. #endif
  410. #endif
  411. }