omapl138_lcdk.c 8.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
  4. *
  5. * Based on da850evm.c. Original Copyrights follow:
  6. *
  7. * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
  8. * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  9. */
  10. #include <common.h>
  11. #include <env.h>
  12. #include <i2c.h>
  13. #include <net.h>
  14. #include <asm/arch/hardware.h>
  15. #include <asm/ti-common/davinci_nand.h>
  16. #include <asm/io.h>
  17. #include <ns16550.h>
  18. #include <dm/platdata.h>
  19. #include <linux/errno.h>
  20. #include <asm/mach-types.h>
  21. #include <asm/arch/davinci_misc.h>
  22. #ifdef CONFIG_MMC_DAVINCI
  23. #include <mmc.h>
  24. #include <asm/arch/sdmmc_defs.h>
  25. #endif
  26. DECLARE_GLOBAL_DATA_PTR;
  27. #define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
  28. #ifdef CONFIG_MMC_DAVINCI
  29. /* MMC0 pin muxer settings */
  30. const struct pinmux_config mmc0_pins[] = {
  31. /* GP0[11] is required for SD to work on Rev 3 EVMs */
  32. { pinmux(0), 8, 4 }, /* GP0[11] */
  33. { pinmux(10), 2, 0 }, /* MMCSD0_CLK */
  34. { pinmux(10), 2, 1 }, /* MMCSD0_CMD */
  35. { pinmux(10), 2, 2 }, /* MMCSD0_DAT_0 */
  36. { pinmux(10), 2, 3 }, /* MMCSD0_DAT_1 */
  37. { pinmux(10), 2, 4 }, /* MMCSD0_DAT_2 */
  38. { pinmux(10), 2, 5 }, /* MMCSD0_DAT_3 */
  39. /* LCDK supports only 4-bit mode, remaining pins are not configured */
  40. };
  41. #endif
  42. /* UART pin muxer settings */
  43. static const struct pinmux_config uart_pins[] = {
  44. { pinmux(0), 4, 6 },
  45. { pinmux(0), 4, 7 },
  46. { pinmux(4), 2, 4 },
  47. { pinmux(4), 2, 5 }
  48. };
  49. #ifdef CONFIG_DRIVER_TI_EMAC
  50. static const struct pinmux_config emac_pins[] = {
  51. { pinmux(2), 8, 1 },
  52. { pinmux(2), 8, 2 },
  53. { pinmux(2), 8, 3 },
  54. { pinmux(2), 8, 4 },
  55. { pinmux(2), 8, 5 },
  56. { pinmux(2), 8, 6 },
  57. { pinmux(2), 8, 7 },
  58. { pinmux(3), 8, 0 },
  59. { pinmux(3), 8, 1 },
  60. { pinmux(3), 8, 2 },
  61. { pinmux(3), 8, 3 },
  62. { pinmux(3), 8, 4 },
  63. { pinmux(3), 8, 5 },
  64. { pinmux(3), 8, 6 },
  65. { pinmux(3), 8, 7 },
  66. { pinmux(4), 8, 0 },
  67. { pinmux(4), 8, 1 }
  68. };
  69. #endif /* CONFIG_DRIVER_TI_EMAC */
  70. /* I2C pin muxer settings */
  71. static const struct pinmux_config i2c_pins[] = {
  72. { pinmux(4), 2, 2 },
  73. { pinmux(4), 2, 3 }
  74. };
  75. #ifdef CONFIG_NAND_DAVINCI
  76. const struct pinmux_config nand_pins[] = {
  77. { pinmux(7), 1, 1 },
  78. { pinmux(7), 1, 2 },
  79. { pinmux(7), 1, 4 },
  80. { pinmux(7), 1, 5 },
  81. { pinmux(8), 1, 0 },
  82. { pinmux(8), 1, 1 },
  83. { pinmux(8), 1, 2 },
  84. { pinmux(8), 1, 3 },
  85. { pinmux(8), 1, 4 },
  86. { pinmux(8), 1, 5 },
  87. { pinmux(8), 1, 6 },
  88. { pinmux(8), 1, 7 },
  89. { pinmux(9), 1, 0 },
  90. { pinmux(9), 1, 1 },
  91. { pinmux(9), 1, 2 },
  92. { pinmux(9), 1, 3 },
  93. { pinmux(9), 1, 4 },
  94. { pinmux(9), 1, 5 },
  95. { pinmux(9), 1, 6 },
  96. { pinmux(9), 1, 7 },
  97. { pinmux(12), 1, 5 },
  98. { pinmux(12), 1, 6 }
  99. };
  100. #endif
  101. #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
  102. #define HAS_RMII 1
  103. #else
  104. #define HAS_RMII 0
  105. #endif
  106. const struct pinmux_resource pinmuxes[] = {
  107. PINMUX_ITEM(uart_pins),
  108. PINMUX_ITEM(i2c_pins),
  109. #ifdef CONFIG_NAND_DAVINCI
  110. PINMUX_ITEM(nand_pins),
  111. #endif
  112. };
  113. const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
  114. const struct lpsc_resource lpsc[] = {
  115. { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
  116. { DAVINCI_LPSC_SPI1 }, /* Serial Flash */
  117. { DAVINCI_LPSC_EMAC }, /* image download */
  118. { DAVINCI_LPSC_UART2 }, /* console */
  119. { DAVINCI_LPSC_GPIO },
  120. #ifdef CONFIG_MMC_DAVINCI
  121. { DAVINCI_LPSC_MMC_SD },
  122. #endif
  123. };
  124. const int lpsc_size = ARRAY_SIZE(lpsc);
  125. #ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
  126. #define CONFIG_DA850_EVM_MAX_CPU_CLK 456000000
  127. #endif
  128. /*
  129. * get_board_rev() - setup to pass kernel board revision information
  130. * Returns:
  131. * bit[0-3] Maximum cpu clock rate supported by onboard SoC
  132. * 0000b - 300 MHz
  133. * 0001b - 372 MHz
  134. * 0010b - 408 MHz
  135. * 0011b - 456 MHz
  136. */
  137. u32 get_board_rev(void)
  138. {
  139. return 0;
  140. }
  141. int board_early_init_f(void)
  142. {
  143. /*
  144. * Power on required peripherals
  145. * ARM does not have access by default to PSC0 and PSC1
  146. * assuming here that the DSP bootloader has set the IOPU
  147. * such that PSC access is available to ARM
  148. */
  149. if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
  150. return 1;
  151. return 0;
  152. }
  153. int board_init(void)
  154. {
  155. irq_init();
  156. /* arch number of the board */
  157. gd->bd->bi_arch_number = MACH_TYPE_OMAPL138_LCDK;
  158. /* address of boot parameters */
  159. gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
  160. /* setup the SUSPSRC for ARM to control emulation suspend */
  161. writel(readl(&davinci_syscfg_regs->suspsrc) &
  162. ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
  163. DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
  164. DAVINCI_SYSCFG_SUSPSRC_UART2),
  165. &davinci_syscfg_regs->suspsrc);
  166. /* configure pinmux settings */
  167. if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
  168. return 1;
  169. #ifdef CONFIG_NAND_DAVINCI
  170. /*
  171. * NAND CS setup - cycle counts based on da850evm NAND timings in the
  172. * Linux kernel @ 25MHz EMIFA
  173. */
  174. writel((DAVINCI_ABCR_WSETUP(15) |
  175. DAVINCI_ABCR_WSTROBE(63) |
  176. DAVINCI_ABCR_WHOLD(7) |
  177. DAVINCI_ABCR_RSETUP(15) |
  178. DAVINCI_ABCR_RSTROBE(63) |
  179. DAVINCI_ABCR_RHOLD(7) |
  180. DAVINCI_ABCR_TA(3) |
  181. DAVINCI_ABCR_ASIZE_16BIT),
  182. &davinci_emif_regs->ab2cr); /* CS3 */
  183. #endif
  184. #ifdef CONFIG_MMC_DAVINCI
  185. if (davinci_configure_pin_mux(mmc0_pins, ARRAY_SIZE(mmc0_pins)) != 0)
  186. return 1;
  187. #endif
  188. #ifdef CONFIG_DRIVER_TI_EMAC
  189. if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
  190. return 1;
  191. davinci_emac_mii_mode_sel(HAS_RMII);
  192. #endif /* CONFIG_DRIVER_TI_EMAC */
  193. /* enable the console UART */
  194. writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
  195. DAVINCI_UART_PWREMU_MGMT_UTRST),
  196. &davinci_uart2_ctrl_regs->pwremu_mgmt);
  197. return 0;
  198. }
  199. #ifdef CONFIG_DRIVER_TI_EMAC
  200. #endif /* CONFIG_DRIVER_TI_EMAC */
  201. #define CFG_MAC_ADDR_SPI_BUS 0
  202. #define CFG_MAC_ADDR_SPI_CS 0
  203. #define CFG_MAC_ADDR_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
  204. #define CFG_MAC_ADDR_SPI_MODE SPI_MODE_3
  205. #define CFG_MAC_ADDR_OFFSET (flash->size - SZ_64K)
  206. static int get_mac_addr(u8 *addr)
  207. {
  208. /* Need to find a way to get MAC ADDRESS */
  209. return 0;
  210. }
  211. void dsp_lpsc_on(unsigned domain, unsigned int id)
  212. {
  213. dv_reg_p mdstat, mdctl, ptstat, ptcmd;
  214. struct davinci_psc_regs *psc_regs;
  215. psc_regs = davinci_psc0_regs;
  216. mdstat = &psc_regs->psc0.mdstat[id];
  217. mdctl = &psc_regs->psc0.mdctl[id];
  218. ptstat = &psc_regs->ptstat;
  219. ptcmd = &psc_regs->ptcmd;
  220. while (*ptstat & (0x1 << domain))
  221. ;
  222. if ((*mdstat & 0x1f) == 0x03)
  223. return; /* Already on and enabled */
  224. *mdctl |= 0x03;
  225. *ptcmd = 0x1 << domain;
  226. while (*ptstat & (0x1 << domain))
  227. ;
  228. while ((*mdstat & 0x1f) != 0x03)
  229. ; /* Probably an overkill... */
  230. }
  231. static void dspwake(void)
  232. {
  233. unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE;
  234. /* if the device is ARM only, return */
  235. if ((REG(CHIP_REV_ID_REG) & 0x3f) == 0x10)
  236. return;
  237. if (!strcmp(env_get("dspwake"), "no"))
  238. return;
  239. *resetvect++ = 0x1E000; /* DSP Idle */
  240. /* clear out the next 10 words as NOP */
  241. memset(resetvect, 0, sizeof(unsigned) * 10);
  242. /* setup the DSP reset vector */
  243. REG(HOST1CFG) = DAVINCI_L3CBARAM_BASE;
  244. dsp_lpsc_on(1, DAVINCI_LPSC_GEM);
  245. REG(PSC0_MDCTL + (15 * 4)) |= 0x100;
  246. }
  247. #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
  248. /**
  249. * rmii_hw_init
  250. *
  251. */
  252. int rmii_hw_init(void)
  253. {
  254. return 0;
  255. }
  256. #endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
  257. int misc_init_r(void)
  258. {
  259. uint8_t tmp[20], addr[10];
  260. if (env_get("ethaddr") == NULL) {
  261. /* Read Ethernet MAC address from EEPROM */
  262. if (dvevm_read_mac_address(addr)) {
  263. /* Set Ethernet MAC address from EEPROM */
  264. davinci_sync_env_enetaddr(addr);
  265. } else {
  266. get_mac_addr(addr);
  267. }
  268. if (!is_multicast_ethaddr(addr) && !is_zero_ethaddr(addr)) {
  269. sprintf((char *)tmp, "%02x:%02x:%02x:%02x:%02x:%02x",
  270. addr[0], addr[1], addr[2], addr[3], addr[4],
  271. addr[5]);
  272. env_set("ethaddr", (char *)tmp);
  273. } else {
  274. printf("Invalid MAC address read.\n");
  275. }
  276. }
  277. #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
  278. /* Select RMII fucntion through the expander */
  279. if (rmii_hw_init())
  280. printf("RMII hardware init failed!!!\n");
  281. #endif
  282. dspwake();
  283. return 0;
  284. }
  285. #if !CONFIG_IS_ENABLED(DM_MMC)
  286. #ifdef CONFIG_MMC_DAVINCI
  287. static struct davinci_mmc mmc_sd0 = {
  288. .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
  289. .host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */
  290. .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
  291. .version = MMC_CTLR_VERSION_2,
  292. };
  293. int board_mmc_init(bd_t *bis)
  294. {
  295. mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID);
  296. /* Add slot-0 to mmc subsystem */
  297. return davinci_mmc_init(bis, &mmc_sd0);
  298. }
  299. #endif
  300. #endif
  301. #ifdef CONFIG_SPL_BUILD
  302. static const struct ns16550_platdata serial_pdata = {
  303. .base = DAVINCI_UART2_BASE,
  304. .reg_shift = 2,
  305. .clock = 228000000,
  306. .fcr = UART_FCR_DEFVAL,
  307. };
  308. U_BOOT_DEVICE(omapl138_uart) = {
  309. .name = "ns16550_serial",
  310. .platdata = &serial_pdata,
  311. };
  312. #endif