cm_t335.c 3.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Board functions for Compulab CM-T335 board
  4. *
  5. * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
  6. *
  7. * Author: Ilya Ledvich <ilya@compulab.co.il>
  8. */
  9. #include <common.h>
  10. #include <env.h>
  11. #include <environment.h>
  12. #include <errno.h>
  13. #include <miiphy.h>
  14. #include <cpsw.h>
  15. #include <asm/arch/sys_proto.h>
  16. #include <asm/arch/hardware_am33xx.h>
  17. #include <asm/io.h>
  18. #include <asm/gpio.h>
  19. #include "../common/eeprom.h"
  20. DECLARE_GLOBAL_DATA_PTR;
  21. /*
  22. * Basic board specific setup. Pinmux has been handled already.
  23. */
  24. int board_init(void)
  25. {
  26. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  27. gpmc_init();
  28. #if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
  29. status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_OFF);
  30. #endif
  31. return 0;
  32. }
  33. #if defined (CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)
  34. static void cpsw_control(int enabled)
  35. {
  36. /* VTP can be added here */
  37. return;
  38. }
  39. static struct cpsw_slave_data cpsw_slave = {
  40. .slave_reg_ofs = 0x208,
  41. .sliver_reg_ofs = 0xd80,
  42. .phy_addr = 0,
  43. .phy_if = PHY_INTERFACE_MODE_RGMII,
  44. };
  45. static struct cpsw_platform_data cpsw_data = {
  46. .mdio_base = CPSW_MDIO_BASE,
  47. .cpsw_base = CPSW_BASE,
  48. .mdio_div = 0xff,
  49. .channels = 8,
  50. .cpdma_reg_ofs = 0x800,
  51. .slaves = 1,
  52. .slave_data = &cpsw_slave,
  53. .ale_reg_ofs = 0xd00,
  54. .ale_entries = 1024,
  55. .host_port_reg_ofs = 0x108,
  56. .hw_stats_reg_ofs = 0x900,
  57. .bd_ram_ofs = 0x2000,
  58. .mac_control = (1 << 5),
  59. .control = cpsw_control,
  60. .host_port_num = 0,
  61. .version = CPSW_CTRL_VERSION_2,
  62. };
  63. /* PHY reset GPIO */
  64. #define GPIO_PHY_RST GPIO_PIN(3, 7)
  65. static void board_phy_init(void)
  66. {
  67. gpio_request(GPIO_PHY_RST, "phy_rst");
  68. gpio_direction_output(GPIO_PHY_RST, 0);
  69. mdelay(2);
  70. gpio_set_value(GPIO_PHY_RST, 1);
  71. mdelay(2);
  72. }
  73. static void get_efuse_mac_addr(uchar *enetaddr)
  74. {
  75. uint32_t mac_hi, mac_lo;
  76. struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  77. mac_lo = readl(&cdev->macid0l);
  78. mac_hi = readl(&cdev->macid0h);
  79. enetaddr[0] = mac_hi & 0xFF;
  80. enetaddr[1] = (mac_hi & 0xFF00) >> 8;
  81. enetaddr[2] = (mac_hi & 0xFF0000) >> 16;
  82. enetaddr[3] = (mac_hi & 0xFF000000) >> 24;
  83. enetaddr[4] = mac_lo & 0xFF;
  84. enetaddr[5] = (mac_lo & 0xFF00) >> 8;
  85. }
  86. /*
  87. * Routine: handle_mac_address
  88. * Description: prepare MAC address for on-board Ethernet.
  89. */
  90. static int handle_mac_address(void)
  91. {
  92. uchar enetaddr[6];
  93. int rv;
  94. rv = eth_env_get_enetaddr("ethaddr", enetaddr);
  95. if (rv)
  96. return 0;
  97. rv = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS);
  98. if (rv)
  99. get_efuse_mac_addr(enetaddr);
  100. if (!is_valid_ethaddr(enetaddr))
  101. return -1;
  102. return eth_env_set_enetaddr("ethaddr", enetaddr);
  103. }
  104. #define AR8051_PHY_DEBUG_ADDR_REG 0x1d
  105. #define AR8051_PHY_DEBUG_DATA_REG 0x1e
  106. #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
  107. #define AR8051_RGMII_TX_CLK_DLY 0x100
  108. int board_eth_init(bd_t *bis)
  109. {
  110. int rv, n = 0;
  111. const char *devname;
  112. struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  113. rv = handle_mac_address();
  114. if (rv)
  115. printf("No MAC address found!\n");
  116. writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel);
  117. board_phy_init();
  118. rv = cpsw_register(&cpsw_data);
  119. if (rv < 0)
  120. printf("Error %d registering CPSW switch\n", rv);
  121. else
  122. n += rv;
  123. /*
  124. * CPSW RGMII Internal Delay Mode is not supported in all PVT
  125. * operating points. So we must set the TX clock delay feature
  126. * in the AR8051 PHY. Since we only support a single ethernet
  127. * device, we only do this for the first instance.
  128. */
  129. devname = miiphy_get_current_dev();
  130. miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
  131. AR8051_DEBUG_RGMII_CLK_DLY_REG);
  132. miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
  133. AR8051_RGMII_TX_CLK_DLY);
  134. return n;
  135. }
  136. #endif /* CONFIG_DRIVER_TI_CPSW && !CONFIG_SPL_BUILD */