cm_fx6.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Board functions for Compulab CM-FX6 board
  4. *
  5. * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
  6. *
  7. * Author: Nikita Kiryanov <nikita@compulab.co.il>
  8. */
  9. #include <common.h>
  10. #include <ahci.h>
  11. #include <dm.h>
  12. #include <dwc_ahsata.h>
  13. #include <env.h>
  14. #include <environment.h>
  15. #include <fsl_esdhc_imx.h>
  16. #include <miiphy.h>
  17. #include <mtd_node.h>
  18. #include <netdev.h>
  19. #include <errno.h>
  20. #include <usb.h>
  21. #include <fdt_support.h>
  22. #include <sata.h>
  23. #include <splash.h>
  24. #include <asm/arch/crm_regs.h>
  25. #include <asm/arch/sys_proto.h>
  26. #include <asm/arch/iomux.h>
  27. #include <asm/arch/mxc_hdmi.h>
  28. #include <asm/mach-imx/mxc_i2c.h>
  29. #include <asm/mach-imx/sata.h>
  30. #include <asm/mach-imx/video.h>
  31. #include <asm/io.h>
  32. #include <asm/gpio.h>
  33. #include <dm/platform_data/serial_mxc.h>
  34. #include <dm/device-internal.h>
  35. #include <jffs2/load_kernel.h>
  36. #include "common.h"
  37. #include "../common/eeprom.h"
  38. #include "../common/common.h"
  39. DECLARE_GLOBAL_DATA_PTR;
  40. #ifdef CONFIG_SPLASH_SCREEN
  41. static struct splash_location cm_fx6_splash_locations[] = {
  42. {
  43. .name = "sf",
  44. .storage = SPLASH_STORAGE_SF,
  45. .flags = SPLASH_STORAGE_RAW,
  46. .offset = 0x100000,
  47. },
  48. {
  49. .name = "mmc_fs",
  50. .storage = SPLASH_STORAGE_MMC,
  51. .flags = SPLASH_STORAGE_FS,
  52. .devpart = "2:1",
  53. },
  54. {
  55. .name = "usb_fs",
  56. .storage = SPLASH_STORAGE_USB,
  57. .flags = SPLASH_STORAGE_FS,
  58. .devpart = "0:1",
  59. },
  60. {
  61. .name = "sata_fs",
  62. .storage = SPLASH_STORAGE_SATA,
  63. .flags = SPLASH_STORAGE_FS,
  64. .devpart = "0:1",
  65. },
  66. };
  67. int splash_screen_prepare(void)
  68. {
  69. return splash_source_load(cm_fx6_splash_locations,
  70. ARRAY_SIZE(cm_fx6_splash_locations));
  71. }
  72. #endif
  73. #ifdef CONFIG_IMX_HDMI
  74. static void cm_fx6_enable_hdmi(struct display_info_t const *dev)
  75. {
  76. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  77. imx_setup_hdmi();
  78. setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
  79. imx_enable_hdmi_phy();
  80. }
  81. static struct display_info_t preset_hdmi_1024X768 = {
  82. .bus = -1,
  83. .addr = 0,
  84. .pixfmt = IPU_PIX_FMT_RGB24,
  85. .enable = cm_fx6_enable_hdmi,
  86. .mode = {
  87. .name = "HDMI",
  88. .refresh = 60,
  89. .xres = 1024,
  90. .yres = 768,
  91. .pixclock = 40385,
  92. .left_margin = 220,
  93. .right_margin = 40,
  94. .upper_margin = 21,
  95. .lower_margin = 7,
  96. .hsync_len = 60,
  97. .vsync_len = 10,
  98. .sync = FB_SYNC_EXT,
  99. .vmode = FB_VMODE_NONINTERLACED,
  100. }
  101. };
  102. static void cm_fx6_setup_display(void)
  103. {
  104. struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  105. enable_ipu_clock();
  106. clrbits_le32(&iomuxc_regs->gpr[3], MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
  107. }
  108. int board_video_skip(void)
  109. {
  110. int ret;
  111. struct display_info_t *preset;
  112. char const *panel = env_get("displaytype");
  113. if (!panel) /* Also accept panel for backward compatibility */
  114. panel = env_get("panel");
  115. if (!panel)
  116. return -ENOENT;
  117. if (!strcmp(panel, "HDMI"))
  118. preset = &preset_hdmi_1024X768;
  119. else
  120. return -EINVAL;
  121. ret = ipuv3_fb_init(&preset->mode, 0, preset->pixfmt);
  122. if (ret) {
  123. printf("Can't init display %s: %d\n", preset->mode.name, ret);
  124. return ret;
  125. }
  126. preset->enable(preset);
  127. printf("Display: %s (%ux%u)\n", preset->mode.name, preset->mode.xres,
  128. preset->mode.yres);
  129. return 0;
  130. }
  131. #else
  132. static inline void cm_fx6_setup_display(void) {}
  133. #endif /* CONFIG_VIDEO_IPUV3 */
  134. #ifdef CONFIG_DWC_AHSATA
  135. static int cm_fx6_issd_gpios[] = {
  136. /* The order of the GPIOs in the array is important! */
  137. CM_FX6_SATA_LDO_EN,
  138. CM_FX6_SATA_PHY_SLP,
  139. CM_FX6_SATA_NRSTDLY,
  140. CM_FX6_SATA_PWREN,
  141. CM_FX6_SATA_NSTANDBY1,
  142. CM_FX6_SATA_NSTANDBY2,
  143. };
  144. static void cm_fx6_sata_power(int on)
  145. {
  146. int i;
  147. if (!on) { /* tell the iSSD that the power will be removed */
  148. gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 1);
  149. mdelay(10);
  150. }
  151. for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
  152. gpio_direction_output(cm_fx6_issd_gpios[i], on);
  153. udelay(100);
  154. }
  155. if (!on) /* for compatibility lower the power loss interrupt */
  156. gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
  157. }
  158. static iomux_v3_cfg_t const sata_pads[] = {
  159. /* SATA PWR */
  160. IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  161. IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  162. IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  163. IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  164. /* SATA CTRL */
  165. IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  166. IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  167. IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  168. IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  169. IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  170. };
  171. static int cm_fx6_setup_issd(void)
  172. {
  173. int ret, i;
  174. SETUP_IOMUX_PADS(sata_pads);
  175. for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
  176. ret = gpio_request(cm_fx6_issd_gpios[i], "sata");
  177. if (ret)
  178. return ret;
  179. }
  180. ret = gpio_request(CM_FX6_SATA_PWLOSS_INT, "sata_pwloss_int");
  181. if (ret)
  182. return ret;
  183. return 0;
  184. }
  185. #define CM_FX6_SATA_INIT_RETRIES 10
  186. #else
  187. static int cm_fx6_setup_issd(void) { return 0; }
  188. #endif
  189. #ifdef CONFIG_SYS_I2C_MXC
  190. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  191. PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  192. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  193. I2C_PADS(i2c0_pads,
  194. PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
  195. PAD_EIM_D21__GPIO3_IO21 | MUX_PAD_CTRL(I2C_PAD_CTRL),
  196. IMX_GPIO_NR(3, 21),
  197. PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
  198. PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(I2C_PAD_CTRL),
  199. IMX_GPIO_NR(3, 28));
  200. I2C_PADS(i2c1_pads,
  201. PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
  202. PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL),
  203. IMX_GPIO_NR(4, 12),
  204. PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
  205. PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL),
  206. IMX_GPIO_NR(4, 13));
  207. I2C_PADS(i2c2_pads,
  208. PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
  209. PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(I2C_PAD_CTRL),
  210. IMX_GPIO_NR(1, 3),
  211. PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
  212. PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL),
  213. IMX_GPIO_NR(1, 6));
  214. static int cm_fx6_setup_one_i2c(int busnum, struct i2c_pads_info *pads)
  215. {
  216. int ret;
  217. ret = setup_i2c(busnum, CONFIG_SYS_I2C_SPEED, 0x7f, pads);
  218. if (ret)
  219. printf("Warning: I2C%d setup failed: %d\n", busnum, ret);
  220. return ret;
  221. }
  222. static int cm_fx6_setup_i2c(void)
  223. {
  224. int ret = 0, err;
  225. /* i2c<x>_pads are wierd macro variables; we can't use an array */
  226. err = cm_fx6_setup_one_i2c(0, I2C_PADS_INFO(i2c0_pads));
  227. if (err)
  228. ret = err;
  229. err = cm_fx6_setup_one_i2c(1, I2C_PADS_INFO(i2c1_pads));
  230. if (err)
  231. ret = err;
  232. err = cm_fx6_setup_one_i2c(2, I2C_PADS_INFO(i2c2_pads));
  233. if (err)
  234. ret = err;
  235. return ret;
  236. }
  237. #else
  238. static int cm_fx6_setup_i2c(void) { return 0; }
  239. #endif
  240. #ifdef CONFIG_USB_EHCI_MX6
  241. #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
  242. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  243. PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  244. #define MX6_USBNC_BASEADDR 0x2184800
  245. #define USBNC_USB_H1_PWR_POL (1 << 9)
  246. static int cm_fx6_setup_usb_host(void)
  247. {
  248. int err;
  249. err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst");
  250. if (err)
  251. return err;
  252. SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL));
  253. SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL));
  254. return 0;
  255. }
  256. static int cm_fx6_setup_usb_otg(void)
  257. {
  258. int err;
  259. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  260. err = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr");
  261. if (err) {
  262. printf("USB OTG pwr gpio request failed: %d\n", err);
  263. return err;
  264. }
  265. SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL));
  266. SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID |
  267. MUX_PAD_CTRL(WEAK_PULLDOWN));
  268. clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK);
  269. /* disable ext. charger detect, or it'll affect signal quality at dp. */
  270. return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0);
  271. }
  272. int board_usb_phy_mode(int port)
  273. {
  274. return USB_INIT_HOST;
  275. }
  276. int board_ehci_hcd_init(int port)
  277. {
  278. int ret;
  279. u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4);
  280. /* Only 1 host controller in use. port 0 is OTG & needs no attention */
  281. if (port != 1)
  282. return 0;
  283. /* Set PWR polarity to match power switch's enable polarity */
  284. setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL);
  285. ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 0);
  286. if (ret)
  287. return ret;
  288. udelay(10);
  289. ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 1);
  290. if (ret)
  291. return ret;
  292. mdelay(1);
  293. return 0;
  294. }
  295. int board_ehci_power(int port, int on)
  296. {
  297. if (port == 0)
  298. return gpio_direction_output(SB_FX6_USB_OTG_PWR, on);
  299. return 0;
  300. }
  301. #else
  302. static int cm_fx6_setup_usb_otg(void) { return 0; }
  303. static int cm_fx6_setup_usb_host(void) { return 0; }
  304. #endif
  305. #ifdef CONFIG_FEC_MXC
  306. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  307. PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  308. static int mx6_rgmii_rework(struct phy_device *phydev)
  309. {
  310. unsigned short val;
  311. /* Ar8031 phy SmartEEE feature cause link status generates glitch,
  312. * which cause ethernet link down/up issue, so disable SmartEEE
  313. */
  314. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
  315. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
  316. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
  317. val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
  318. val &= ~(0x1 << 8);
  319. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
  320. /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
  321. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  322. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
  323. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
  324. val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
  325. val &= 0xffe3;
  326. val |= 0x18;
  327. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
  328. /* introduce tx clock delay */
  329. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
  330. val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
  331. val |= 0x0100;
  332. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
  333. return 0;
  334. }
  335. int board_phy_config(struct phy_device *phydev)
  336. {
  337. mx6_rgmii_rework(phydev);
  338. if (phydev->drv->config)
  339. return phydev->drv->config(phydev);
  340. return 0;
  341. }
  342. static iomux_v3_cfg_t const enet_pads[] = {
  343. IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  344. IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  345. IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  346. IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  347. IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  348. IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  349. IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  350. IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  351. IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  352. IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  353. IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  354. IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  355. IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  356. IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  357. IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(0x84)),
  358. IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
  359. MUX_PAD_CTRL(ENET_PAD_CTRL)),
  360. IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
  361. MUX_PAD_CTRL(ENET_PAD_CTRL)),
  362. IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
  363. MUX_PAD_CTRL(ENET_PAD_CTRL)),
  364. };
  365. static int handle_mac_address(char *env_var, uint eeprom_bus)
  366. {
  367. unsigned char enetaddr[6];
  368. int rc;
  369. rc = eth_env_get_enetaddr(env_var, enetaddr);
  370. if (rc)
  371. return 0;
  372. rc = cl_eeprom_read_mac_addr(enetaddr, eeprom_bus);
  373. if (rc)
  374. return rc;
  375. if (!is_valid_ethaddr(enetaddr))
  376. return -1;
  377. return eth_env_set_enetaddr(env_var, enetaddr);
  378. }
  379. #define SB_FX6_I2C_EEPROM_BUS 0
  380. #define NO_MAC_ADDR "No MAC address found for %s\n"
  381. int board_eth_init(bd_t *bis)
  382. {
  383. int err;
  384. if (handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS))
  385. printf(NO_MAC_ADDR, "primary NIC");
  386. if (handle_mac_address("eth1addr", SB_FX6_I2C_EEPROM_BUS))
  387. printf(NO_MAC_ADDR, "secondary NIC");
  388. SETUP_IOMUX_PADS(enet_pads);
  389. /* phy reset */
  390. err = gpio_request(CM_FX6_ENET_NRST, "enet_nrst");
  391. if (err)
  392. printf("Etnernet NRST gpio request failed: %d\n", err);
  393. gpio_direction_output(CM_FX6_ENET_NRST, 0);
  394. udelay(500);
  395. gpio_set_value(CM_FX6_ENET_NRST, 1);
  396. enable_enet_clk(1);
  397. return cpu_eth_init(bis);
  398. }
  399. #endif
  400. #ifdef CONFIG_NAND_MXS
  401. static iomux_v3_cfg_t const nand_pads[] = {
  402. IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
  403. IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
  404. IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  405. IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  406. IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  407. IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  408. IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  409. IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  410. IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  411. IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  412. IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  413. IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  414. IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  415. IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  416. };
  417. static void cm_fx6_setup_gpmi_nand(void)
  418. {
  419. SETUP_IOMUX_PADS(nand_pads);
  420. /* Enable clock roots */
  421. enable_usdhc_clk(1, 3);
  422. enable_usdhc_clk(1, 4);
  423. setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) |
  424. MXC_CCM_CS2CDR_ENFC_CLK_PRED(1) |
  425. MXC_CCM_CS2CDR_ENFC_CLK_SEL(0));
  426. }
  427. #else
  428. static void cm_fx6_setup_gpmi_nand(void) {}
  429. #endif
  430. #ifdef CONFIG_MXC_SPI
  431. int cm_fx6_setup_ecspi(void)
  432. {
  433. cm_fx6_set_ecspi_iomux();
  434. return gpio_request(CM_FX6_ECSPI_BUS0_CS0, "ecspi_bus0_cs0");
  435. }
  436. #else
  437. int cm_fx6_setup_ecspi(void) { return 0; }
  438. #endif
  439. #ifdef CONFIG_OF_BOARD_SETUP
  440. #define USDHC3_PATH "/soc/aips-bus@02100000/usdhc@02198000/"
  441. static const struct node_info nodes[] = {
  442. /*
  443. * Both entries target the same flash chip. The st,m25p compatible
  444. * is used in the vendor device trees, while upstream uses (the
  445. * documented) jedec,spi-nor compatible.
  446. */
  447. { "st,m25p", MTD_DEV_TYPE_NOR, },
  448. { "jedec,spi-nor", MTD_DEV_TYPE_NOR, },
  449. };
  450. int ft_board_setup(void *blob, bd_t *bd)
  451. {
  452. u32 baseboard_rev;
  453. int nodeoffset;
  454. uint8_t enetaddr[6];
  455. char baseboard_name[16];
  456. int err;
  457. fdt_shrink_to_minimum(blob, 0); /* Make room for new properties */
  458. /* MAC addr */
  459. if (eth_env_get_enetaddr("ethaddr", enetaddr)) {
  460. fdt_find_and_setprop(blob,
  461. "/soc/aips-bus@02100000/ethernet@02188000",
  462. "local-mac-address", enetaddr, 6, 1);
  463. }
  464. if (eth_env_get_enetaddr("eth1addr", enetaddr)) {
  465. fdt_find_and_setprop(blob, "/eth@pcie", "local-mac-address",
  466. enetaddr, 6, 1);
  467. }
  468. fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
  469. baseboard_rev = cl_eeprom_get_board_rev(0);
  470. err = cl_eeprom_get_product_name((uchar *)baseboard_name, 0);
  471. if (err || baseboard_rev == 0)
  472. return 0; /* Assume not an early revision SB-FX6m baseboard */
  473. if (!strncmp("SB-FX6m", baseboard_name, 7) && baseboard_rev <= 120) {
  474. nodeoffset = fdt_path_offset(blob, USDHC3_PATH);
  475. fdt_delprop(blob, nodeoffset, "cd-gpios");
  476. fdt_find_and_setprop(blob, USDHC3_PATH, "broken-cd",
  477. NULL, 0, 1);
  478. fdt_find_and_setprop(blob, USDHC3_PATH, "keep-power-in-suspend",
  479. NULL, 0, 1);
  480. }
  481. return 0;
  482. }
  483. #endif
  484. int board_init(void)
  485. {
  486. int ret;
  487. gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  488. cm_fx6_setup_gpmi_nand();
  489. ret = cm_fx6_setup_ecspi();
  490. if (ret)
  491. printf("Warning: ECSPI setup failed: %d\n", ret);
  492. ret = cm_fx6_setup_usb_otg();
  493. if (ret)
  494. printf("Warning: USB OTG setup failed: %d\n", ret);
  495. ret = cm_fx6_setup_usb_host();
  496. if (ret)
  497. printf("Warning: USB host setup failed: %d\n", ret);
  498. /*
  499. * cm-fx6 may have iSSD not assembled and in this case it has
  500. * bypasses for a (m)SATA socket on the baseboard. The socketed
  501. * device is not controlled by those GPIOs. So just print a warning
  502. * if the setup fails.
  503. */
  504. ret = cm_fx6_setup_issd();
  505. if (ret)
  506. printf("Warning: iSSD setup failed: %d\n", ret);
  507. /* Warn on failure but do not abort boot */
  508. ret = cm_fx6_setup_i2c();
  509. if (ret)
  510. printf("Warning: I2C setup failed: %d\n", ret);
  511. cm_fx6_setup_display();
  512. /* This should be done in the MMC driver when MX6 has a clock driver */
  513. #ifdef CONFIG_FSL_ESDHC_IMX
  514. if (IS_ENABLED(CONFIG_BLK)) {
  515. int i;
  516. cm_fx6_set_usdhc_iomux();
  517. for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++)
  518. enable_usdhc_clk(1, i);
  519. }
  520. #endif
  521. return 0;
  522. }
  523. int board_late_init(void)
  524. {
  525. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  526. char baseboard_name[16];
  527. int err;
  528. if (is_mx6dq())
  529. env_set("board_rev", "MX6Q");
  530. else if (is_mx6dl())
  531. env_set("board_rev", "MX6DL");
  532. err = cl_eeprom_get_product_name((uchar *)baseboard_name, 0);
  533. if (err)
  534. return 0;
  535. if (!strncmp("SB-FX6m", baseboard_name, 7))
  536. env_set("board_name", "Utilite");
  537. #endif
  538. return 0;
  539. }
  540. int checkboard(void)
  541. {
  542. puts("Board: CM-FX6\n");
  543. return 0;
  544. }
  545. int misc_init_r(void)
  546. {
  547. cl_print_pcb_info();
  548. return 0;
  549. }
  550. int dram_init_banksize(void)
  551. {
  552. gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  553. gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  554. switch (gd->ram_size) {
  555. case 0x10000000: /* DDR_16BIT_256MB */
  556. gd->bd->bi_dram[0].size = 0x10000000;
  557. gd->bd->bi_dram[1].size = 0;
  558. break;
  559. case 0x20000000: /* DDR_32BIT_512MB */
  560. gd->bd->bi_dram[0].size = 0x20000000;
  561. gd->bd->bi_dram[1].size = 0;
  562. break;
  563. case 0x40000000:
  564. if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */
  565. gd->bd->bi_dram[0].size = 0x20000000;
  566. gd->bd->bi_dram[1].size = 0x20000000;
  567. } else { /* DDR_64BIT_1GB */
  568. gd->bd->bi_dram[0].size = 0x40000000;
  569. gd->bd->bi_dram[1].size = 0;
  570. }
  571. break;
  572. case 0x80000000: /* DDR_64BIT_2GB */
  573. gd->bd->bi_dram[0].size = 0x40000000;
  574. gd->bd->bi_dram[1].size = 0x40000000;
  575. break;
  576. case 0xEFF00000: /* DDR_64BIT_4GB */
  577. gd->bd->bi_dram[0].size = 0x70000000;
  578. gd->bd->bi_dram[1].size = 0x7FF00000;
  579. break;
  580. }
  581. return 0;
  582. }
  583. int dram_init(void)
  584. {
  585. gd->ram_size = imx_ddr_size();
  586. switch (gd->ram_size) {
  587. case 0x10000000:
  588. case 0x20000000:
  589. case 0x40000000:
  590. case 0x80000000:
  591. break;
  592. case 0xF0000000:
  593. gd->ram_size -= 0x100000;
  594. break;
  595. default:
  596. printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size);
  597. return -1;
  598. }
  599. return 0;
  600. }
  601. u32 get_board_rev(void)
  602. {
  603. return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS);
  604. }
  605. static struct mxc_serial_platdata cm_fx6_mxc_serial_plat = {
  606. .reg = (struct mxc_uart *)UART4_BASE,
  607. };
  608. U_BOOT_DEVICE(cm_fx6_serial) = {
  609. .name = "serial_mxc",
  610. .platdata = &cm_fx6_mxc_serial_plat,
  611. };
  612. #if CONFIG_IS_ENABLED(AHCI)
  613. static int sata_imx_probe(struct udevice *dev)
  614. {
  615. int i, err;
  616. /* Make sure this gpio has logical 0 value */
  617. gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
  618. udelay(100);
  619. cm_fx6_sata_power(1);
  620. for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) {
  621. err = setup_sata();
  622. if (err) {
  623. printf("SATA setup failed: %d\n", err);
  624. return err;
  625. }
  626. udelay(100);
  627. err = dwc_ahsata_probe(dev);
  628. if (!err)
  629. break;
  630. /* There is no device on the SATA port */
  631. if (sata_dm_port_status(0, 0) == 0)
  632. break;
  633. /* There's a device, but link not established. Retry */
  634. device_remove(dev, DM_REMOVE_NORMAL);
  635. }
  636. return 0;
  637. }
  638. static int sata_imx_remove(struct udevice *dev)
  639. {
  640. cm_fx6_sata_power(0);
  641. mdelay(250);
  642. return 0;
  643. }
  644. struct ahci_ops sata_imx_ops = {
  645. .port_status = dwc_ahsata_port_status,
  646. .reset = dwc_ahsata_bus_reset,
  647. .scan = dwc_ahsata_scan,
  648. };
  649. static const struct udevice_id sata_imx_ids[] = {
  650. { .compatible = "fsl,imx6q-ahci" },
  651. { }
  652. };
  653. U_BOOT_DRIVER(sata_imx) = {
  654. .name = "dwc_ahci",
  655. .id = UCLASS_AHCI,
  656. .of_match = sata_imx_ids,
  657. .ops = &sata_imx_ops,
  658. .probe = sata_imx_probe,
  659. .remove = sata_imx_remove, /* reset bus to stop it */
  660. };
  661. #endif /* AHCI */