xpress.c 9.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
  4. */
  5. #include <asm/arch/clock.h>
  6. #include <asm/arch/iomux.h>
  7. #include <asm/arch/imx-regs.h>
  8. #include <asm/arch/crm_regs.h>
  9. #include <asm/arch/mx6ul_pins.h>
  10. #include <asm/arch/mx6-pins.h>
  11. #include <asm/arch/sys_proto.h>
  12. #include <asm/gpio.h>
  13. #include <asm/mach-imx/iomux-v3.h>
  14. #include <asm/mach-imx/boot_mode.h>
  15. #include <asm/mach-imx/mxc_i2c.h>
  16. #include <asm/io.h>
  17. #include <common.h>
  18. #include <env.h>
  19. #include <fsl_esdhc_imx.h>
  20. #include <i2c.h>
  21. #include <miiphy.h>
  22. #include <mmc.h>
  23. #include <netdev.h>
  24. #include <usb.h>
  25. #include <usb/ehci-ci.h>
  26. DECLARE_GLOBAL_DATA_PTR;
  27. #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  28. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  29. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  30. #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  31. PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
  32. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  33. #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  34. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  35. PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  36. PAD_CTL_ODE)
  37. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  38. PAD_CTL_SPEED_HIGH | \
  39. PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
  40. #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  41. PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
  42. #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  43. #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  44. PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
  45. #define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  46. PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
  47. PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
  48. PAD_CTL_SRE_FAST)
  49. #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  50. static struct i2c_pads_info i2c_pad_info1 = {
  51. .scl = {
  52. .i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC,
  53. .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC,
  54. .gp = IMX_GPIO_NR(1, 2),
  55. },
  56. .sda = {
  57. .i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC,
  58. .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC,
  59. .gp = IMX_GPIO_NR(1, 3),
  60. },
  61. };
  62. static struct i2c_pads_info i2c_pad_info2 = {
  63. .scl = {
  64. .i2c_mode = MX6_PAD_GPIO1_IO00__I2C2_SCL | PC,
  65. .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO00 | PC,
  66. .gp = IMX_GPIO_NR(1, 0),
  67. },
  68. .sda = {
  69. .i2c_mode = MX6_PAD_GPIO1_IO01__I2C2_SDA | PC,
  70. .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO01 | PC,
  71. .gp = IMX_GPIO_NR(1, 1),
  72. },
  73. };
  74. static struct i2c_pads_info i2c_pad_info4 = {
  75. .scl = {
  76. .i2c_mode = MX6_PAD_UART2_TX_DATA__I2C4_SCL | PC,
  77. .gpio_mode = MX6_PAD_UART2_TX_DATA__GPIO1_IO20 | PC,
  78. .gp = IMX_GPIO_NR(1, 20),
  79. },
  80. .sda = {
  81. .i2c_mode = MX6_PAD_UART2_RX_DATA__I2C4_SDA | PC,
  82. .gpio_mode = MX6_PAD_UART2_RX_DATA__GPIO1_IO21 | PC,
  83. .gp = IMX_GPIO_NR(1, 21),
  84. },
  85. };
  86. int dram_init(void)
  87. {
  88. gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  89. return 0;
  90. }
  91. static iomux_v3_cfg_t const uart1_pads[] = {
  92. MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  93. MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  94. MX6_PAD_UART1_CTS_B__UART1_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
  95. MX6_PAD_UART1_RTS_B__UART1_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
  96. };
  97. static iomux_v3_cfg_t const uart4_pads[] = {
  98. MX6_PAD_UART4_TX_DATA__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  99. MX6_PAD_UART4_RX_DATA__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  100. };
  101. static iomux_v3_cfg_t const uart5_pads[] = {
  102. MX6_PAD_GPIO1_IO04__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  103. MX6_PAD_GPIO1_IO05__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  104. MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
  105. MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
  106. };
  107. static iomux_v3_cfg_t const uart7_pads[] = {
  108. MX6_PAD_ENET2_RX_EN__UART7_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  109. MX6_PAD_ENET2_TX_DATA0__UART7_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  110. };
  111. static iomux_v3_cfg_t const uart8_pads[] = {
  112. MX6_PAD_LCD_DATA20__UART8_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  113. MX6_PAD_LCD_DATA21__UART8_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  114. };
  115. static void setup_iomux_uart(void)
  116. {
  117. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  118. imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
  119. imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
  120. imx_iomux_v3_setup_multiple_pads(uart7_pads, ARRAY_SIZE(uart7_pads));
  121. imx_iomux_v3_setup_multiple_pads(uart8_pads, ARRAY_SIZE(uart8_pads));
  122. }
  123. /* eMMC on USDHC2 */
  124. static iomux_v3_cfg_t const usdhc2_pads[] = {
  125. MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  126. MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  127. MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  128. MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  129. MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  130. MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  131. MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  132. MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  133. MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  134. MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  135. /*
  136. * RST_B
  137. */
  138. MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  139. };
  140. static struct fsl_esdhc_cfg usdhc_cfg = {
  141. .esdhc_base = USDHC2_BASE_ADDR,
  142. .max_bus_width = 8,
  143. };
  144. #define USDHC2_PWR_GPIO IMX_GPIO_NR(1, 9)
  145. int board_mmc_getcd(struct mmc *mmc)
  146. {
  147. /* eMMC is always present */
  148. return 1;
  149. }
  150. int board_mmc_init(bd_t *bis)
  151. {
  152. imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
  153. usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  154. return fsl_esdhc_initialize(bis, &usdhc_cfg);
  155. }
  156. #define USB_OTHERREGS_OFFSET 0x800
  157. #define UCTRL_PWR_POL (1 << 9)
  158. static iomux_v3_cfg_t const usb_otg_pads[] = {
  159. /* OTG1 */
  160. MX6_PAD_SD1_CMD__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
  161. MX6_PAD_SD1_DATA0__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL),
  162. /* OTG2 */
  163. MX6_PAD_SD1_DATA1__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
  164. MX6_PAD_SD1_DATA3__ANATOP_OTG2_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL),
  165. };
  166. static void setup_usb(void)
  167. {
  168. imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
  169. ARRAY_SIZE(usb_otg_pads));
  170. }
  171. int board_usb_phy_mode(int port)
  172. {
  173. if (port == 1)
  174. return USB_INIT_HOST;
  175. else
  176. return usb_phy_mode(port);
  177. }
  178. int board_ehci_hcd_init(int port)
  179. {
  180. u32 *usbnc_usb_ctrl;
  181. if (port > 1)
  182. return -EINVAL;
  183. usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
  184. port * 4);
  185. /* Set Power polarity */
  186. setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
  187. return 0;
  188. }
  189. static iomux_v3_cfg_t const fec1_pads[] = {
  190. MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
  191. MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  192. MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  193. MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  194. MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  195. MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
  196. MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  197. MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  198. MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
  199. MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  200. /* ENET1 reset */
  201. MX6_PAD_CSI_MCLK__GPIO4_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
  202. /* ENET1 interrupt */
  203. MX6_PAD_CSI_PIXCLK__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
  204. };
  205. #define ENET_PHY_RESET_GPIO IMX_GPIO_NR(4, 17)
  206. int board_eth_init(bd_t *bis)
  207. {
  208. int ret;
  209. imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
  210. /* Reset LAN8742 PHY */
  211. ret = gpio_request(ENET_PHY_RESET_GPIO, "phy-reset");
  212. if (!ret)
  213. gpio_direction_output(ENET_PHY_RESET_GPIO , 0);
  214. mdelay(10);
  215. gpio_set_value(ENET_PHY_RESET_GPIO, 1);
  216. mdelay(10);
  217. return cpu_eth_init(bis);
  218. }
  219. static int setup_fec(int fec_id)
  220. {
  221. struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  222. int ret;
  223. /*
  224. * Use 50M anatop loopback REF_CLK1 for ENET1,
  225. * clear gpr1[13], set gpr1[17].
  226. */
  227. clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
  228. IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
  229. ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
  230. if (ret)
  231. return ret;
  232. enable_enet_clk(1);
  233. return 0;
  234. }
  235. int board_phy_config(struct phy_device *phydev)
  236. {
  237. if (phydev->drv->config)
  238. phydev->drv->config(phydev);
  239. return 0;
  240. }
  241. int board_early_init_f(void)
  242. {
  243. setup_iomux_uart();
  244. return 0;
  245. }
  246. int board_init(void)
  247. {
  248. /* Address of boot parameters */
  249. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  250. setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  251. setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
  252. setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);
  253. setup_fec(CONFIG_FEC_ENET_DEV);
  254. setup_usb();
  255. return 0;
  256. }
  257. static const struct boot_mode board_boot_modes[] = {
  258. /* 8 bit bus width */
  259. {"emmc", MAKE_CFGVAL(0x60, 0x28, 0x00, 0x00)},
  260. { NULL, 0 },
  261. };
  262. int board_late_init(void)
  263. {
  264. add_board_boot_modes(board_boot_modes);
  265. env_set("board_name", "xpress");
  266. return 0;
  267. }
  268. int checkboard(void)
  269. {
  270. puts("Board: CCV-EVA xPress\n");
  271. return 0;
  272. }