xtfpga.c 2.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007 - 2013 Tensilica Inc.
  4. * (C) Copyright 2014 - 2016 Cadence Design Systems Inc.
  5. */
  6. #include <common.h>
  7. #include <command.h>
  8. #include <dm.h>
  9. #include <dm/platform_data/net_ethoc.h>
  10. #include <env.h>
  11. #include <linux/ctype.h>
  12. #include <linux/string.h>
  13. #include <linux/stringify.h>
  14. #include <asm/global_data.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. /*
  17. * Check board idendity.
  18. * (Print information about the board to stdout.)
  19. */
  20. #if defined(CONFIG_XTFPGA_LX60)
  21. const char *board = "XT_AV60";
  22. const char *description = "Avnet Xilinx LX60 FPGA Evaluation Board / ";
  23. #elif defined(CONFIG_XTFPGA_LX110)
  24. const char *board = "XT_AV110";
  25. const char *description = "Avnet Xilinx Virtex-5 LX110 Evaluation Kit / ";
  26. #elif defined(CONFIG_XTFPGA_LX200)
  27. const char *board = "XT_AV200";
  28. const char *description = "Avnet Xilinx Virtex-4 LX200 Evaluation Kit / ";
  29. #elif defined(CONFIG_XTFPGA_ML605)
  30. const char *board = "XT_ML605";
  31. const char *description = "Xilinx Virtex-6 FPGA ML605 Evaluation Kit / ";
  32. #elif defined(CONFIG_XTFPGA_KC705)
  33. const char *board = "XT_KC705";
  34. const char *description = "Xilinx Kintex-7 FPGA KC705 Evaluation Kit / ";
  35. #else
  36. const char *board = "<unknown>";
  37. const char *description = "";
  38. #endif
  39. int checkboard(void)
  40. {
  41. printf("Board: %s: %sTensilica bitstream\n", board, description);
  42. return 0;
  43. }
  44. int dram_init_banksize(void)
  45. {
  46. gd->bd->bi_memstart = PHYSADDR(CONFIG_SYS_SDRAM_BASE);
  47. gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
  48. return 0;
  49. }
  50. int board_postclk_init(void)
  51. {
  52. /*
  53. * Obtain CPU clock frequency from board and cache in global
  54. * data structure (Hz). Return 0 on success (OK to continue),
  55. * else non-zero (hang).
  56. */
  57. #ifdef CONFIG_SYS_FPGAREG_FREQ
  58. gd->cpu_clk = (*(volatile unsigned long *)CONFIG_SYS_FPGAREG_FREQ);
  59. #else
  60. /* early Tensilica bitstreams lack this reg, but most run at 50 MHz */
  61. gd->cpu_clk = 50000000UL;
  62. #endif
  63. return 0;
  64. }
  65. /*
  66. * Miscellaneous late initializations.
  67. * The environment has been set up, so we can set the Ethernet address.
  68. */
  69. int misc_init_r(void)
  70. {
  71. #ifdef CONFIG_CMD_NET
  72. /*
  73. * Initialize ethernet environment variables and board info.
  74. * Default MAC address comes from CONFIG_ETHADDR + DIP switches 1-6.
  75. */
  76. char *s = env_get("ethaddr");
  77. if (s == 0) {
  78. unsigned int x;
  79. char s[] = __stringify(CONFIG_ETHBASE);
  80. x = (*(volatile u32 *)CONFIG_SYS_FPGAREG_DIPSW)
  81. & FPGAREG_MAC_MASK;
  82. sprintf(&s[15], "%02x", x);
  83. env_set("ethaddr", s);
  84. }
  85. #endif /* CONFIG_CMD_NET */
  86. return 0;
  87. }
  88. U_BOOT_DEVICE(sysreset) = {
  89. .name = "xtfpga_sysreset",
  90. };
  91. static struct ethoc_eth_pdata ethoc_pdata = {
  92. .eth_pdata = {
  93. .iobase = CONFIG_SYS_ETHOC_BASE,
  94. },
  95. .packet_base = CONFIG_SYS_ETHOC_BUFFER_ADDR,
  96. };
  97. U_BOOT_DEVICE(ethoc) = {
  98. .name = "ethoc",
  99. .platdata = &ethoc_pdata,
  100. };