sama5d3xek.c 7.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 - 2013 Atmel Corporation
  4. * Bo Shen <voice.shen@atmel.com>
  5. */
  6. #include <common.h>
  7. #include <asm/io.h>
  8. #include <asm/arch/sama5d3_smc.h>
  9. #include <asm/arch/at91_common.h>
  10. #include <asm/arch/at91_rstc.h>
  11. #include <asm/arch/gpio.h>
  12. #include <asm/arch/clk.h>
  13. #include <debug_uart.h>
  14. #include <env.h>
  15. #include <linux/ctype.h>
  16. #include <phy.h>
  17. #include <micrel.h>
  18. #include <spl.h>
  19. #include <asm/arch/atmel_mpddrc.h>
  20. #include <asm/arch/at91_wdt.h>
  21. DECLARE_GLOBAL_DATA_PTR;
  22. /* ------------------------------------------------------------------------- */
  23. /*
  24. * Miscelaneous platform dependent initialisations
  25. */
  26. #ifdef CONFIG_NAND_ATMEL
  27. void sama5d3xek_nand_hw_init(void)
  28. {
  29. struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  30. at91_periph_clk_enable(ATMEL_ID_SMC);
  31. /* Configure SMC CS3 for NAND/SmartMedia */
  32. writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
  33. AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
  34. &smc->cs[3].setup);
  35. writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
  36. AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
  37. &smc->cs[3].pulse);
  38. writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
  39. &smc->cs[3].cycle);
  40. writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
  41. AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) |
  42. AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3)|
  43. AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
  44. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  45. AT91_SMC_MODE_EXNW_DISABLE |
  46. #ifdef CONFIG_SYS_NAND_DBW_16
  47. AT91_SMC_MODE_DBW_16 |
  48. #else /* CONFIG_SYS_NAND_DBW_8 */
  49. AT91_SMC_MODE_DBW_8 |
  50. #endif
  51. AT91_SMC_MODE_TDF_CYCLE(3),
  52. &smc->cs[3].mode);
  53. }
  54. #endif
  55. #ifdef CONFIG_MTD_NOR_FLASH
  56. static void sama5d3xek_nor_hw_init(void)
  57. {
  58. struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  59. at91_periph_clk_enable(ATMEL_ID_SMC);
  60. /* Configure SMC CS0 for NOR flash */
  61. writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  62. AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
  63. &smc->cs[0].setup);
  64. writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(11) |
  65. AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(11),
  66. &smc->cs[0].pulse);
  67. writel(AT91_SMC_CYCLE_NWE(11) | AT91_SMC_CYCLE_NRD(14),
  68. &smc->cs[0].cycle);
  69. writel(AT91_SMC_TIMINGS_TCLR(0) | AT91_SMC_TIMINGS_TADL(0) |
  70. AT91_SMC_TIMINGS_TAR(0) | AT91_SMC_TIMINGS_TRR(0) |
  71. AT91_SMC_TIMINGS_TWB(0) | AT91_SMC_TIMINGS_RBNSEL(0)|
  72. AT91_SMC_TIMINGS_NFSEL(0), &smc->cs[0].timings);
  73. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  74. AT91_SMC_MODE_EXNW_DISABLE |
  75. AT91_SMC_MODE_DBW_16 |
  76. AT91_SMC_MODE_TDF_CYCLE(1),
  77. &smc->cs[0].mode);
  78. /* Address pin (A1 ~ A23) configuration */
  79. at91_pio3_set_a_periph(AT91_PIO_PORTE, 1, 0);
  80. at91_pio3_set_a_periph(AT91_PIO_PORTE, 2, 0);
  81. at91_pio3_set_a_periph(AT91_PIO_PORTE, 3, 0);
  82. at91_pio3_set_a_periph(AT91_PIO_PORTE, 4, 0);
  83. at91_pio3_set_a_periph(AT91_PIO_PORTE, 5, 0);
  84. at91_pio3_set_a_periph(AT91_PIO_PORTE, 6, 0);
  85. at91_pio3_set_a_periph(AT91_PIO_PORTE, 7, 0);
  86. at91_pio3_set_a_periph(AT91_PIO_PORTE, 8, 0);
  87. at91_pio3_set_a_periph(AT91_PIO_PORTE, 9, 0);
  88. at91_pio3_set_a_periph(AT91_PIO_PORTE, 10, 0);
  89. at91_pio3_set_a_periph(AT91_PIO_PORTE, 11, 0);
  90. at91_pio3_set_a_periph(AT91_PIO_PORTE, 12, 0);
  91. at91_pio3_set_a_periph(AT91_PIO_PORTE, 13, 0);
  92. at91_pio3_set_a_periph(AT91_PIO_PORTE, 14, 0);
  93. at91_pio3_set_a_periph(AT91_PIO_PORTE, 15, 0);
  94. at91_pio3_set_a_periph(AT91_PIO_PORTE, 16, 0);
  95. at91_pio3_set_a_periph(AT91_PIO_PORTE, 17, 0);
  96. at91_pio3_set_a_periph(AT91_PIO_PORTE, 18, 0);
  97. at91_pio3_set_a_periph(AT91_PIO_PORTE, 19, 0);
  98. at91_pio3_set_a_periph(AT91_PIO_PORTE, 20, 0);
  99. at91_pio3_set_a_periph(AT91_PIO_PORTE, 21, 0);
  100. at91_pio3_set_a_periph(AT91_PIO_PORTE, 22, 0);
  101. at91_pio3_set_a_periph(AT91_PIO_PORTE, 23, 0);
  102. /* CS0 pin configuration */
  103. at91_pio3_set_a_periph(AT91_PIO_PORTE, 26, 0);
  104. }
  105. #endif
  106. #ifdef CONFIG_CMD_USB
  107. static void sama5d3xek_usb_hw_init(void)
  108. {
  109. at91_set_pio_output(AT91_PIO_PORTD, 25, 0);
  110. at91_set_pio_output(AT91_PIO_PORTD, 26, 0);
  111. at91_set_pio_output(AT91_PIO_PORTD, 27, 0);
  112. }
  113. #endif
  114. #ifdef CONFIG_GENERIC_ATMEL_MCI
  115. static void sama5d3xek_mci_hw_init(void)
  116. {
  117. at91_set_pio_output(AT91_PIO_PORTB, 10, 0); /* MCI0 Power */
  118. }
  119. #endif
  120. #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  121. void board_debug_uart_init(void)
  122. {
  123. at91_seriald_hw_init();
  124. }
  125. #endif
  126. #ifdef CONFIG_BOARD_EARLY_INIT_F
  127. int board_early_init_f(void)
  128. {
  129. #ifdef CONFIG_DEBUG_UART
  130. debug_uart_init();
  131. #endif
  132. return 0;
  133. }
  134. #endif
  135. int board_init(void)
  136. {
  137. /* adress of boot parameters */
  138. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  139. #ifdef CONFIG_NAND_ATMEL
  140. sama5d3xek_nand_hw_init();
  141. #endif
  142. #ifdef CONFIG_MTD_NOR_FLASH
  143. sama5d3xek_nor_hw_init();
  144. #endif
  145. #ifdef CONFIG_CMD_USB
  146. sama5d3xek_usb_hw_init();
  147. #endif
  148. #ifdef CONFIG_GENERIC_ATMEL_MCI
  149. sama5d3xek_mci_hw_init();
  150. #endif
  151. return 0;
  152. }
  153. int dram_init(void)
  154. {
  155. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  156. CONFIG_SYS_SDRAM_SIZE);
  157. return 0;
  158. }
  159. #ifdef CONFIG_BOARD_LATE_INIT
  160. int board_late_init(void)
  161. {
  162. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  163. const int MAX_STR_LEN = 32;
  164. char name[MAX_STR_LEN], *p;
  165. int i;
  166. strncpy(name, get_cpu_name(), MAX_STR_LEN);
  167. for (i = 0, p = name; (*p) && (i < MAX_STR_LEN); p++, i++)
  168. *p = tolower(*p);
  169. strcat(name, "ek.dtb");
  170. env_set("dtb_name", name);
  171. #endif
  172. #ifdef CONFIG_DM_VIDEO
  173. at91_video_show_board_info();
  174. #endif
  175. return 0;
  176. }
  177. #endif
  178. /* SPL */
  179. #ifdef CONFIG_SPL_BUILD
  180. void spl_board_init(void)
  181. {
  182. #if CONFIG_NAND_BOOT
  183. sama5d3xek_nand_hw_init();
  184. #endif
  185. }
  186. static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
  187. {
  188. ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
  189. ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
  190. ATMEL_MPDDRC_CR_NR_ROW_14 |
  191. ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
  192. ATMEL_MPDDRC_CR_ENRDM_ON |
  193. ATMEL_MPDDRC_CR_NB_8BANKS |
  194. ATMEL_MPDDRC_CR_NDQS_DISABLED |
  195. ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
  196. ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
  197. /*
  198. * As the DDR2-SDRAm device requires a refresh time is 7.8125us
  199. * when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks
  200. */
  201. ddr2->rtr = 0x411;
  202. ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
  203. 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
  204. 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
  205. 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
  206. 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
  207. 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
  208. 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
  209. 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
  210. ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
  211. 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
  212. 28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
  213. 26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
  214. ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
  215. 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
  216. 2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
  217. 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
  218. 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
  219. }
  220. void mem_init(void)
  221. {
  222. struct atmel_mpddrc_config ddr2;
  223. ddr2_conf(&ddr2);
  224. /* Enable MPDDR clock */
  225. at91_periph_clk_enable(ATMEL_ID_MPDDRC);
  226. at91_system_clk_enable(AT91_PMC_DDR);
  227. /* DDRAM2 Controller initialize */
  228. ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
  229. }
  230. void at91_pmc_init(void)
  231. {
  232. u32 tmp;
  233. tmp = AT91_PMC_PLLAR_29 |
  234. AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
  235. AT91_PMC_PLLXR_MUL(43) |
  236. AT91_PMC_PLLXR_DIV(1);
  237. at91_plla_init(tmp);
  238. at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3));
  239. tmp = AT91_PMC_MCKR_MDIV_4 |
  240. AT91_PMC_MCKR_CSS_PLLA;
  241. at91_mck_init(tmp);
  242. }
  243. #endif