integrator.c 4.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  5. * Marius Groeger <mgroeger@sysgo.de>
  6. *
  7. * (C) Copyright 2002
  8. * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
  9. *
  10. * (C) Copyright 2003
  11. * Texas Instruments, <www.ti.com>
  12. * Kshitij Gupta <Kshitij@ti.com>
  13. *
  14. * (C) Copyright 2004
  15. * ARM Ltd.
  16. * Philippe Robin, <philippe.robin@arm.com>
  17. */
  18. #include <common.h>
  19. #include <dm.h>
  20. #include <env.h>
  21. #include <netdev.h>
  22. #include <asm/io.h>
  23. #include <dm/platform_data/serial_pl01x.h>
  24. #include "arm-ebi.h"
  25. #include "integrator-sc.h"
  26. #include <asm/mach-types.h>
  27. DECLARE_GLOBAL_DATA_PTR;
  28. static const struct pl01x_serial_platdata serial_platdata = {
  29. .base = 0x16000000,
  30. #ifdef CONFIG_ARCH_CINTEGRATOR
  31. .type = TYPE_PL011,
  32. .clock = 14745600,
  33. #else
  34. .type = TYPE_PL010,
  35. .clock = 0, /* Not used for PL010 */
  36. #endif
  37. };
  38. U_BOOT_DEVICE(integrator_serials) = {
  39. .name = "serial_pl01x",
  40. .platdata = &serial_platdata,
  41. };
  42. void peripheral_power_enable (void);
  43. #if defined(CONFIG_SHOW_BOOT_PROGRESS)
  44. void show_boot_progress(int progress)
  45. {
  46. printf("Boot reached stage %d\n", progress);
  47. }
  48. #endif
  49. #define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
  50. /*
  51. * Miscellaneous platform dependent initialisations
  52. */
  53. int board_init (void)
  54. {
  55. u32 val;
  56. /* arch number of Integrator Board */
  57. #ifdef CONFIG_ARCH_CINTEGRATOR
  58. gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR;
  59. #else
  60. gd->bd->bi_arch_number = MACH_TYPE_INTEGRATOR;
  61. #endif
  62. /* adress of boot parameters */
  63. gd->bd->bi_boot_params = 0x00000100;
  64. #ifdef CONFIG_CM_REMAP
  65. extern void cm_remap(void);
  66. cm_remap(); /* remaps writeable memory to 0x00000000 */
  67. #endif
  68. #ifdef CONFIG_ARCH_CINTEGRATOR
  69. /*
  70. * Flash protection on the Integrator/CP is in a simple register
  71. */
  72. val = readl(CP_FLASHPROG);
  73. val |= (CP_FLASHPROG_FLVPPEN | CP_FLASHPROG_FLWREN);
  74. writel(val, CP_FLASHPROG);
  75. #else
  76. /*
  77. * The Integrator/AP has some special protection mechanisms
  78. * for the external memories, first the External Bus Interface (EBI)
  79. * then the system controller (SC).
  80. *
  81. * The system comes up with the flash memory non-writable and
  82. * configuration locked. If we want U-Boot to be used for flash
  83. * access we cannot have the flash memory locked.
  84. */
  85. writel(EBI_UNLOCK_MAGIC, EBI_BASE + EBI_LOCK_REG);
  86. val = readl(EBI_BASE + EBI_CSR1_REG);
  87. val &= EBI_CSR_WREN_MASK;
  88. val |= EBI_CSR_WREN_ENABLE;
  89. writel(val, EBI_BASE + EBI_CSR1_REG);
  90. writel(0, EBI_BASE + EBI_LOCK_REG);
  91. /*
  92. * Set up the system controller to remove write protection from
  93. * the flash memory and enable Vpp
  94. */
  95. writel(SC_CTRL_FLASHVPP | SC_CTRL_FLASHWP, SC_CTRLS);
  96. #endif
  97. icache_enable ();
  98. return 0;
  99. }
  100. int misc_init_r (void)
  101. {
  102. env_set("verify", "n");
  103. return (0);
  104. }
  105. /*
  106. * The Integrator remaps the Flash memory to 0x00000000 and executes U-Boot
  107. * from there, which means we cannot test the RAM underneath the ROM at this
  108. * point. It will be unmapped later on, when we are executing from the
  109. * relocated in RAM U-Boot. We simply assume that this RAM is usable if the
  110. * RAM on higher addresses works fine.
  111. */
  112. #define REMAPPED_FLASH_SZ 0x40000
  113. int dram_init (void)
  114. {
  115. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  116. #ifdef CONFIG_CM_SPD_DETECT
  117. {
  118. extern void dram_query(void);
  119. u32 cm_reg_sdram;
  120. u32 sdram_shift;
  121. dram_query(); /* Assembler accesses to CM registers */
  122. /* Queries the SPD values */
  123. /* Obtain the SDRAM size from the CM SDRAM register */
  124. cm_reg_sdram = readl(CM_BASE + OS_SDRAM);
  125. /* Register SDRAM size
  126. *
  127. * 0xXXXXXXbbb000bb 16 MB
  128. * 0xXXXXXXbbb001bb 32 MB
  129. * 0xXXXXXXbbb010bb 64 MB
  130. * 0xXXXXXXbbb011bb 128 MB
  131. * 0xXXXXXXbbb100bb 256 MB
  132. *
  133. */
  134. sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
  135. gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
  136. REMAPPED_FLASH_SZ,
  137. 0x01000000 << sdram_shift);
  138. }
  139. #else
  140. gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
  141. REMAPPED_FLASH_SZ,
  142. PHYS_SDRAM_1_SIZE);
  143. #endif /* CM_SPD_DETECT */
  144. /* We only have one bank of RAM, set it to whatever was detected */
  145. gd->bd->bi_dram[0].size = gd->ram_size;
  146. return 0;
  147. }
  148. #ifdef CONFIG_CMD_NET
  149. int board_eth_init(bd_t *bis)
  150. {
  151. int rc = 0;
  152. #ifdef CONFIG_SMC91111
  153. rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
  154. #endif
  155. rc += pci_eth_init(bis);
  156. return rc;
  157. }
  158. #endif