aristainetos-v2.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2015
  4. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  5. *
  6. * Based on:
  7. * Copyright (C) 2012 Freescale Semiconductor, Inc.
  8. *
  9. * Author: Fabio Estevam <fabio.estevam@freescale.com>
  10. */
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/imx-regs.h>
  13. #include <asm/arch/iomux.h>
  14. #include <asm/arch/mx6-pins.h>
  15. #include <env.h>
  16. #include <linux/errno.h>
  17. #include <asm/gpio.h>
  18. #include <asm/mach-imx/iomux-v3.h>
  19. #include <asm/mach-imx/boot_mode.h>
  20. #include <asm/mach-imx/mxc_i2c.h>
  21. #include <asm/mach-imx/video.h>
  22. #include <mmc.h>
  23. #include <fsl_esdhc_imx.h>
  24. #include <miiphy.h>
  25. #include <netdev.h>
  26. #include <asm/arch/mxc_hdmi.h>
  27. #include <asm/arch/crm_regs.h>
  28. #include <linux/fb.h>
  29. #include <ipu_pixfmt.h>
  30. #include <asm/io.h>
  31. #include <asm/arch/sys_proto.h>
  32. #include <pwm.h>
  33. #include <micrel.h>
  34. #include <spi.h>
  35. #include <video.h>
  36. #include <../drivers/video/imx/ipu.h>
  37. #if defined(CONFIG_VIDEO_BMP_LOGO)
  38. #include <bmp_logo.h>
  39. #endif
  40. #define USDHC2_PAD_CTRL (PAD_CTL_SPEED_LOW | \
  41. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  42. #if (CONFIG_SYS_BOARD_VERSION == 2)
  43. /* 4.3 display controller */
  44. #define ECSPI1_CS0 IMX_GPIO_NR(4, 9)
  45. #define ECSPI4_CS0 IMX_GPIO_NR(3, 29)
  46. #elif (CONFIG_SYS_BOARD_VERSION == 3)
  47. #define ECSPI1_CS0 IMX_GPIO_NR(2, 30) /* NOR flash */
  48. /* 4.3 display controller */
  49. #define ECSPI1_CS1 IMX_GPIO_NR(4, 10)
  50. #endif
  51. #define SOFT_RESET_GPIO IMX_GPIO_NR(7, 13)
  52. #define SD2_DRIVER_ENABLE IMX_GPIO_NR(7, 8)
  53. struct i2c_pads_info i2c_pad_info3 = {
  54. .scl = {
  55. .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
  56. .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC,
  57. .gp = IMX_GPIO_NR(1, 5)
  58. },
  59. .sda = {
  60. .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
  61. .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC,
  62. .gp = IMX_GPIO_NR(1, 6)
  63. }
  64. };
  65. struct i2c_pads_info i2c_pad_info4 = {
  66. .scl = {
  67. .i2c_mode = MX6_PAD_GPIO_7__I2C4_SCL | PC,
  68. .gpio_mode = MX6_PAD_GPIO_7__GPIO1_IO07 | PC,
  69. .gp = IMX_GPIO_NR(1, 7)
  70. },
  71. .sda = {
  72. .i2c_mode = MX6_PAD_GPIO_8__I2C4_SDA | PC,
  73. .gpio_mode = MX6_PAD_GPIO_8__GPIO1_IO08 | PC,
  74. .gp = IMX_GPIO_NR(1, 8)
  75. }
  76. };
  77. iomux_v3_cfg_t const uart1_pads[] = {
  78. MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  79. MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  80. MX6_PAD_EIM_D19__UART1_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  81. MX6_PAD_EIM_D20__UART1_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  82. };
  83. iomux_v3_cfg_t const uart2_pads[] = {
  84. MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  85. MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  86. };
  87. iomux_v3_cfg_t const uart3_pads[] = {
  88. MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  89. MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  90. MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  91. MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  92. };
  93. iomux_v3_cfg_t const uart4_pads[] = {
  94. MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  95. MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  96. };
  97. iomux_v3_cfg_t const gpio_pads[] = {
  98. /* LED enable*/
  99. MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
  100. /* LED yellow */
  101. MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL),
  102. /* LED red */
  103. #if (CONFIG_SYS_BOARD_VERSION == 2)
  104. MX6_PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
  105. #elif (CONFIG_SYS_BOARD_VERSION == 3)
  106. MX6_PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
  107. #endif
  108. /* LED green */
  109. MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
  110. /* LED blue */
  111. MX6_PAD_EIM_EB1__GPIO2_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
  112. /* spi flash WP protect */
  113. MX6_PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
  114. /* spi CS 0 */
  115. MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
  116. /* spi bus #2 SS driver enable */
  117. MX6_PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
  118. /* RST_LOC# PHY reset input (has pull-down!)*/
  119. MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
  120. /* SD 2 level shifter output enable */
  121. MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
  122. /* SD1 card detect input */
  123. MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
  124. /* SD1 write protect input */
  125. MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
  126. /* SD2 card detect input */
  127. MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
  128. /* SD2 write protect input */
  129. MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
  130. /* Touchscreen IRQ */
  131. MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
  132. };
  133. static iomux_v3_cfg_t const misc_pads[] = {
  134. /* USB_OTG_ID = GPIO1_24*/
  135. MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
  136. /* H1 Power enable = GPIO1_0*/
  137. MX6_PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
  138. /* OTG Power enable = GPIO4_15*/
  139. MX6_PAD_KEY_ROW4__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
  140. };
  141. iomux_v3_cfg_t const enet_pads[] = {
  142. MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  143. MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  144. MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  145. MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  146. MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  147. MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  148. MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  149. MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  150. MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  151. MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  152. MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  153. MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  154. MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  155. MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  156. MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  157. };
  158. static iomux_v3_cfg_t const backlight_pads[] = {
  159. /* backlight PWM brightness control */
  160. MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
  161. /* backlight enable */
  162. MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
  163. /* LCD power enable */
  164. MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
  165. };
  166. static iomux_v3_cfg_t const ecspi1_pads[] = {
  167. MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
  168. MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
  169. MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
  170. #if (CONFIG_SYS_BOARD_VERSION == 2)
  171. MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(SPI_PAD_CTRL),
  172. #elif (CONFIG_SYS_BOARD_VERSION == 3)
  173. MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(SPI_PAD_CTRL),
  174. MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
  175. #endif
  176. };
  177. static void setup_iomux_enet(void)
  178. {
  179. imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
  180. }
  181. #if (CONFIG_SYS_BOARD_VERSION == 2)
  182. iomux_v3_cfg_t const ecspi4_pads[] = {
  183. MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL),
  184. MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL),
  185. MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL),
  186. MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
  187. MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
  188. };
  189. #endif
  190. static iomux_v3_cfg_t const display_pads[] = {
  191. MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL),
  192. MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
  193. MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
  194. MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
  195. MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
  196. MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
  197. MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
  198. MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
  199. MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
  200. MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
  201. MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
  202. MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
  203. MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
  204. MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
  205. MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
  206. MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
  207. MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
  208. MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
  209. MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
  210. MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
  211. MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
  212. MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
  213. MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
  214. MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
  215. MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
  216. MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
  217. MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
  218. MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
  219. };
  220. int board_spi_cs_gpio(unsigned bus, unsigned cs)
  221. {
  222. if (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
  223. #if (CONFIG_SYS_BOARD_VERSION == 2)
  224. return IMX_GPIO_NR(5, 2);
  225. if (bus == 0 && cs == 0)
  226. return IMX_GPIO_NR(4, 9);
  227. #elif (CONFIG_SYS_BOARD_VERSION == 3)
  228. return ECSPI1_CS0;
  229. if (bus == 0 && cs == 1)
  230. return ECSPI1_CS1;
  231. #endif
  232. return -1;
  233. }
  234. static void setup_spi(void)
  235. {
  236. int i;
  237. imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
  238. #if (CONFIG_SYS_BOARD_VERSION == 2)
  239. imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
  240. #endif
  241. for (i = 0; i < 4; i++)
  242. enable_spi_clk(true, i);
  243. gpio_direction_output(ECSPI1_CS0, 1);
  244. #if (CONFIG_SYS_BOARD_VERSION == 2)
  245. gpio_direction_output(ECSPI4_CS1, 0);
  246. /* set cs0 to high (second device on spi bus #4) */
  247. gpio_direction_output(ECSPI4_CS0, 1);
  248. #elif (CONFIG_SYS_BOARD_VERSION == 3)
  249. gpio_direction_output(ECSPI1_CS1, 1);
  250. #endif
  251. }
  252. static void setup_iomux_uart(void)
  253. {
  254. switch (CONFIG_MXC_UART_BASE) {
  255. case UART1_BASE:
  256. imx_iomux_v3_setup_multiple_pads(uart1_pads,
  257. ARRAY_SIZE(uart1_pads));
  258. break;
  259. case UART2_BASE:
  260. imx_iomux_v3_setup_multiple_pads(uart2_pads,
  261. ARRAY_SIZE(uart2_pads));
  262. break;
  263. case UART3_BASE:
  264. imx_iomux_v3_setup_multiple_pads(uart3_pads,
  265. ARRAY_SIZE(uart3_pads));
  266. break;
  267. case UART4_BASE:
  268. imx_iomux_v3_setup_multiple_pads(uart4_pads,
  269. ARRAY_SIZE(uart4_pads));
  270. break;
  271. }
  272. }
  273. int board_phy_config(struct phy_device *phydev)
  274. {
  275. /* control data pad skew - devaddr = 0x02, register = 0x04 */
  276. ksz9031_phy_extended_write(phydev, 0x02,
  277. MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
  278. MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  279. /* rx data pad skew - devaddr = 0x02, register = 0x05 */
  280. ksz9031_phy_extended_write(phydev, 0x02,
  281. MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
  282. MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  283. /* tx data pad skew - devaddr = 0x02, register = 0x06 */
  284. ksz9031_phy_extended_write(phydev, 0x02,
  285. MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
  286. MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  287. /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
  288. ksz9031_phy_extended_write(phydev, 0x02,
  289. MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
  290. MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
  291. if (phydev->drv->config)
  292. phydev->drv->config(phydev);
  293. return 0;
  294. }
  295. int board_eth_init(bd_t *bis)
  296. {
  297. setup_iomux_enet();
  298. return cpu_eth_init(bis);
  299. }
  300. static int rotate_logo_one(unsigned char *out, unsigned char *in)
  301. {
  302. int i, j;
  303. for (i = 0; i < BMP_LOGO_WIDTH; i++)
  304. for (j = 0; j < BMP_LOGO_HEIGHT; j++)
  305. out[j * BMP_LOGO_WIDTH + BMP_LOGO_HEIGHT - 1 - i] =
  306. in[i * BMP_LOGO_WIDTH + j];
  307. return 0;
  308. }
  309. /*
  310. * Rotate the BMP_LOGO (only)
  311. * Will only work, if the logo is square, as
  312. * BMP_LOGO_HEIGHT and BMP_LOGO_WIDTH are defines, not variables
  313. */
  314. void rotate_logo(int rotations)
  315. {
  316. unsigned char out_logo[BMP_LOGO_WIDTH * BMP_LOGO_HEIGHT];
  317. unsigned char *in_logo;
  318. int i, j;
  319. if (BMP_LOGO_WIDTH != BMP_LOGO_HEIGHT)
  320. return;
  321. in_logo = bmp_logo_bitmap;
  322. /* one 90 degree rotation */
  323. if (rotations == 1 || rotations == 2 || rotations == 3)
  324. rotate_logo_one(out_logo, in_logo);
  325. /* second 90 degree rotation */
  326. if (rotations == 2 || rotations == 3)
  327. rotate_logo_one(in_logo, out_logo);
  328. /* third 90 degree rotation */
  329. if (rotations == 3)
  330. rotate_logo_one(out_logo, in_logo);
  331. /* copy result back to original array */
  332. if (rotations == 1 || rotations == 3)
  333. for (i = 0; i < BMP_LOGO_WIDTH; i++)
  334. for (j = 0; j < BMP_LOGO_HEIGHT; j++)
  335. in_logo[i * BMP_LOGO_WIDTH + j] =
  336. out_logo[i * BMP_LOGO_WIDTH + j];
  337. }
  338. static void enable_display_power(void)
  339. {
  340. imx_iomux_v3_setup_multiple_pads(backlight_pads,
  341. ARRAY_SIZE(backlight_pads));
  342. /* backlight enable */
  343. gpio_direction_output(IMX_GPIO_NR(6, 31), 1);
  344. /* LCD power enable */
  345. gpio_direction_output(IMX_GPIO_NR(6, 15), 1);
  346. /* enable backlight PWM 1 */
  347. if (pwm_init(0, 0, 0))
  348. goto error;
  349. /* duty cycle 500ns, period: 3000ns */
  350. if (pwm_config(0, 50000, 300000))
  351. goto error;
  352. if (pwm_enable(0))
  353. goto error;
  354. return;
  355. error:
  356. puts("error init pwm for backlight\n");
  357. return;
  358. }
  359. static void enable_lvds(struct display_info_t const *dev)
  360. {
  361. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  362. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  363. int reg;
  364. s32 timeout = 100000;
  365. /* set PLL5 clock */
  366. reg = readl(&ccm->analog_pll_video);
  367. reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
  368. writel(reg, &ccm->analog_pll_video);
  369. /* set PLL5 to 232720000Hz */
  370. reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
  371. reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x26);
  372. reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
  373. reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
  374. writel(reg, &ccm->analog_pll_video);
  375. writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xC0238),
  376. &ccm->analog_pll_video_num);
  377. writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xF4240),
  378. &ccm->analog_pll_video_denom);
  379. reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
  380. writel(reg, &ccm->analog_pll_video);
  381. while (timeout--)
  382. if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
  383. break;
  384. if (timeout < 0)
  385. printf("Warning: video pll lock timeout!\n");
  386. reg = readl(&ccm->analog_pll_video);
  387. reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
  388. reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
  389. writel(reg, &ccm->analog_pll_video);
  390. /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
  391. reg = readl(&ccm->cs2cdr);
  392. reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
  393. | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
  394. reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
  395. | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
  396. writel(reg, &ccm->cs2cdr);
  397. reg = readl(&ccm->cscmr2);
  398. reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
  399. writel(reg, &ccm->cscmr2);
  400. reg = readl(&ccm->chsccdr);
  401. reg |= (CHSCCDR_CLK_SEL_LDB_DI0
  402. << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  403. writel(reg, &ccm->chsccdr);
  404. reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
  405. | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
  406. | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
  407. | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
  408. | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
  409. | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
  410. | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
  411. writel(reg, &iomux->gpr[2]);
  412. reg = readl(&iomux->gpr[3]);
  413. reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
  414. | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
  415. << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
  416. writel(reg, &iomux->gpr[3]);
  417. return;
  418. }
  419. static void enable_spi_display(struct display_info_t const *dev)
  420. {
  421. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  422. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  423. int reg;
  424. s32 timeout = 100000;
  425. #if defined(CONFIG_VIDEO_BMP_LOGO)
  426. rotate_logo(3); /* portrait display in landscape mode */
  427. #endif
  428. /*
  429. * set ldb clock to 28341000 Hz calculated through the formula:
  430. * (XRES + LEFT_M + RIGHT_M + HSYNC_LEN) *
  431. * (YRES + UPPER_M + LOWER_M + VSYNC_LEN) * REFRESH)
  432. * see:
  433. * https://community.freescale.com/thread/308170
  434. */
  435. ipu_set_ldb_clock(28341000);
  436. reg = readl(&ccm->cs2cdr);
  437. /* select pll 5 clock */
  438. reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
  439. | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
  440. writel(reg, &ccm->cs2cdr);
  441. /* set PLL5 to 197994996Hz */
  442. reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
  443. reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x21);
  444. reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
  445. reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
  446. writel(reg, &ccm->analog_pll_video);
  447. writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xfbf4),
  448. &ccm->analog_pll_video_num);
  449. writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xf4240),
  450. &ccm->analog_pll_video_denom);
  451. reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
  452. writel(reg, &ccm->analog_pll_video);
  453. while (timeout--)
  454. if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
  455. break;
  456. if (timeout < 0)
  457. printf("Warning: video pll lock timeout!\n");
  458. reg = readl(&ccm->analog_pll_video);
  459. reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
  460. reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
  461. writel(reg, &ccm->analog_pll_video);
  462. /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
  463. reg = readl(&ccm->cs2cdr);
  464. reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
  465. | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
  466. reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
  467. | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
  468. writel(reg, &ccm->cs2cdr);
  469. reg = readl(&ccm->cscmr2);
  470. reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
  471. writel(reg, &ccm->cscmr2);
  472. reg = readl(&ccm->chsccdr);
  473. reg |= (CHSCCDR_CLK_SEL_LDB_DI0
  474. << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  475. reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK;
  476. reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET);
  477. reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK;
  478. reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
  479. writel(reg, &ccm->chsccdr);
  480. reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
  481. | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
  482. | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
  483. | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
  484. | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
  485. | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
  486. | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
  487. writel(reg, &iomux->gpr[2]);
  488. reg = readl(&iomux->gpr[3]);
  489. reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
  490. | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
  491. << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
  492. writel(reg, &iomux->gpr[3]);
  493. imx_iomux_v3_setup_multiple_pads(
  494. display_pads,
  495. ARRAY_SIZE(display_pads));
  496. return;
  497. }
  498. static void setup_display(void)
  499. {
  500. enable_ipu_clock();
  501. enable_display_power();
  502. }
  503. static void setup_iomux_gpio(void)
  504. {
  505. imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
  506. }
  507. static void set_gpr_register(void)
  508. {
  509. struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  510. writel(IOMUXC_GPR1_APP_CLK_REQ_N | IOMUXC_GPR1_PCIE_RDY_L23 |
  511. IOMUXC_GPR1_EXC_MON_SLVE |
  512. (2 << IOMUXC_GPR1_ADDRS0_OFFSET) |
  513. IOMUXC_GPR1_ACT_CS0,
  514. &iomuxc_regs->gpr[1]);
  515. writel(0x0, &iomuxc_regs->gpr[8]);
  516. writel(IOMUXC_GPR12_ARMP_IPG_CLK_EN | IOMUXC_GPR12_ARMP_AHB_CLK_EN |
  517. IOMUXC_GPR12_ARMP_ATB_CLK_EN | IOMUXC_GPR12_ARMP_APB_CLK_EN,
  518. &iomuxc_regs->gpr[12]);
  519. }
  520. int board_early_init_f(void)
  521. {
  522. setup_iomux_uart();
  523. setup_iomux_gpio();
  524. gpio_direction_output(SOFT_RESET_GPIO, 1);
  525. gpio_direction_output(SD2_DRIVER_ENABLE, 1);
  526. setup_display();
  527. set_gpr_register();
  528. return 0;
  529. }
  530. static void setup_i2c4(void)
  531. {
  532. setup_i2c(3, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
  533. &i2c_pad_info4);
  534. }
  535. static void setup_board_gpio(void)
  536. {
  537. /* enable all LEDs */
  538. gpio_request(IMX_GPIO_NR(2, 13), "LED ena"); /* 25 */
  539. gpio_direction_output(IMX_GPIO_NR(1, 25), 0);
  540. /* switch off Status LEDs */
  541. #if (CONFIG_SYS_BOARD_VERSION == 2)
  542. gpio_request(IMX_GPIO_NR(6, 16), "LED yellow"); /* 176 */
  543. gpio_direction_output(IMX_GPIO_NR(6, 16), 1);
  544. gpio_request(IMX_GPIO_NR(2, 28), "LED red"); /* 60 */
  545. gpio_direction_output(IMX_GPIO_NR(2, 28), 1);
  546. gpio_request(IMX_GPIO_NR(5, 4), "LED green"); /* 132 */
  547. gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
  548. gpio_request(IMX_GPIO_NR(2, 29), "LED blue"); /* 61 */
  549. gpio_direction_output(IMX_GPIO_NR(2, 29), 1);
  550. #elif (CONFIG_SYS_BOARD_VERSION == 3)
  551. gpio_request(IMX_GPIO_NR(6, 16), "LED yellow"); /* 176 */
  552. gpio_direction_output(IMX_GPIO_NR(6, 16), 0);
  553. gpio_request(IMX_GPIO_NR(5, 0), "LED red"); /* 128 */
  554. gpio_direction_output(IMX_GPIO_NR(5, 0), 0);
  555. gpio_request(IMX_GPIO_NR(5, 4), "LED green"); /* 132 */
  556. gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
  557. gpio_request(IMX_GPIO_NR(2, 29), "LED blue"); /* 61 */
  558. gpio_direction_output(IMX_GPIO_NR(2, 29), 0);
  559. #endif
  560. }
  561. static void setup_board_spi(void)
  562. {
  563. /* enable spi bus #2 SS drivers (and spi bus #4 SS1 for rev2b) */
  564. gpio_direction_output(IMX_GPIO_NR(6, 6), 1);
  565. }
  566. int board_late_init(void)
  567. {
  568. char *my_bootdelay;
  569. char bootmode = 0;
  570. char const *panel = env_get("panel");
  571. /*
  572. * Check the boot-source. If booting from NOR Flash,
  573. * disable bootdelay
  574. */
  575. gpio_request(IMX_GPIO_NR(7, 6), "bootsel0");
  576. gpio_direction_input(IMX_GPIO_NR(7, 6));
  577. gpio_request(IMX_GPIO_NR(7, 7), "bootsel1");
  578. gpio_direction_input(IMX_GPIO_NR(7, 7));
  579. gpio_request(IMX_GPIO_NR(7, 1), "bootsel2");
  580. gpio_direction_input(IMX_GPIO_NR(7, 1));
  581. bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 6)) ? 1 : 0) << 0;
  582. bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 7)) ? 1 : 0) << 1;
  583. bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 1)) ? 1 : 0) << 2;
  584. if (bootmode == 7) {
  585. my_bootdelay = env_get("nor_bootdelay");
  586. if (my_bootdelay != NULL)
  587. env_set("bootdelay", my_bootdelay);
  588. else
  589. env_set("bootdelay", "-2");
  590. }
  591. /* if we have the lg panel, we can initialze it now */
  592. if (panel)
  593. if (!strcmp(panel, displays[1].mode.name))
  594. lg4573_spi_startup(CONFIG_LG4573_BUS,
  595. CONFIG_LG4573_CS,
  596. 10000000, SPI_MODE_0);
  597. return 0;
  598. }