x530.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Allied Telesis Labs
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <dm.h>
  8. #include <env.h>
  9. #include <i2c.h>
  10. #include <wdt.h>
  11. #include <asm/gpio.h>
  12. #include <linux/mbus.h>
  13. #include <linux/io.h>
  14. #include <asm/arch/cpu.h>
  15. #include <asm/arch/soc.h>
  16. #include "../common/gpio_hog.h"
  17. #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
  18. #include <../serdes/a38x/high_speed_env_spec.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. #define MVEBU_DEV_BUS_BASE (MVEBU_REGISTER(0x10400))
  21. #define CONFIG_NVS_LOCATION 0xf4800000
  22. #define CONFIG_NVS_SIZE (512 << 10)
  23. static struct serdes_map board_serdes_map[] = {
  24. {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  25. {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  26. {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  27. {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  28. {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  29. {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}
  30. };
  31. int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
  32. {
  33. *serdes_map_array = board_serdes_map;
  34. *count = ARRAY_SIZE(board_serdes_map);
  35. return 0;
  36. }
  37. /*
  38. * Define the DDR layout / topology here in the board file. This will
  39. * be used by the DDR3 init code in the SPL U-Boot version to configure
  40. * the DDR3 controller.
  41. */
  42. static struct mv_ddr_topology_map board_topology_map = {
  43. DEBUG_LEVEL_ERROR,
  44. 0x1, /* active interfaces */
  45. /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
  46. { { { {0x1, 0, 0, 0},
  47. {0x1, 0, 0, 0},
  48. {0x1, 0, 0, 0},
  49. {0x1, 0, 0, 0},
  50. {0x1, 0, 0, 0} },
  51. SPEED_BIN_DDR_1866M, /* speed_bin */
  52. MV_DDR_DEV_WIDTH_16BIT, /* sdram device width */
  53. MV_DDR_DIE_CAP_4GBIT, /* die capacity */
  54. MV_DDR_FREQ_SAR, /* frequency */
  55. 0, 0, /* cas_l cas_wl */
  56. MV_DDR_TEMP_LOW, /* temperature */
  57. MV_DDR_TIM_2T} }, /* timing */
  58. BUS_MASK_32BIT_ECC, /* subphys mask */
  59. MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
  60. { {0} }, /* raw spd data */
  61. {0} /* timing parameters */
  62. };
  63. struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
  64. {
  65. /* Return the board topology as defined in the board code */
  66. return &board_topology_map;
  67. }
  68. int board_early_init_f(void)
  69. {
  70. /* Configure MPP */
  71. writel(0x00001111, MVEBU_MPP_BASE + 0x00);
  72. writel(0x00000000, MVEBU_MPP_BASE + 0x04);
  73. writel(0x55000000, MVEBU_MPP_BASE + 0x08);
  74. writel(0x55550550, MVEBU_MPP_BASE + 0x0c);
  75. writel(0x55555555, MVEBU_MPP_BASE + 0x10);
  76. writel(0x00100565, MVEBU_MPP_BASE + 0x14);
  77. writel(0x40000000, MVEBU_MPP_BASE + 0x18);
  78. writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
  79. return 0;
  80. }
  81. void spl_board_init(void)
  82. {
  83. }
  84. int board_init(void)
  85. {
  86. /* address of boot parameters */
  87. gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  88. /* window for NVS */
  89. mbus_dt_setup_win(&mbus_state, CONFIG_NVS_LOCATION, CONFIG_NVS_SIZE,
  90. CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS1);
  91. /* DEV_READYn is not needed for NVS, ignore it when accessing CS1 */
  92. writel(0x00004001, MVEBU_DEV_BUS_BASE + 0xc8);
  93. spl_board_init();
  94. return 0;
  95. }
  96. void arch_preboot_os(void)
  97. {
  98. #ifdef CONFIG_WATCHDOG
  99. wdt_stop(gd->watchdog_dev);
  100. #endif
  101. }
  102. static int led_7seg_init(unsigned int segments)
  103. {
  104. int node;
  105. int ret;
  106. int i;
  107. struct gpio_desc desc[8];
  108. node = fdt_node_offset_by_compatible(gd->fdt_blob, 0,
  109. "atl,of-led-7seg");
  110. if (node < 0)
  111. return -ENODEV;
  112. ret = gpio_request_list_by_name_nodev(offset_to_ofnode(node),
  113. "segment-gpios", desc,
  114. ARRAY_SIZE(desc), GPIOD_IS_OUT);
  115. if (ret < 0)
  116. return ret;
  117. for (i = 0; i < ARRAY_SIZE(desc); i++) {
  118. ret = dm_gpio_set_value(&desc[i], !(segments & BIT(i)));
  119. if (ret)
  120. return ret;
  121. }
  122. return 0;
  123. }
  124. #ifdef CONFIG_MISC_INIT_R
  125. int misc_init_r(void)
  126. {
  127. static struct gpio_desc usb_en = {}, nand_wp = {}, phy_reset[2] = {},
  128. led_en = {};
  129. gpio_hog(&usb_en, "atl,usb-enable", "enable-gpio", 1);
  130. gpio_hog(&nand_wp, "atl,nand-protect", "protect-gpio", 1);
  131. gpio_hog_list(phy_reset, ARRAY_SIZE(phy_reset), "atl,phy-reset", "reset-gpio", 0);
  132. gpio_hog(&led_en, "atl,led-enable", "enable-gpio", 1);
  133. #ifdef MTDPARTS_MTDOOPS
  134. env_set("mtdoops", MTDPARTS_MTDOOPS);
  135. #endif
  136. led_7seg_init(0xff);
  137. return 0;
  138. }
  139. #endif
  140. #ifdef CONFIG_DISPLAY_BOARDINFO
  141. int checkboard(void)
  142. {
  143. puts("Board: " CONFIG_SYS_BOARD "\n");
  144. return 0;
  145. }
  146. #endif