board2.c 9.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2010,2011
  4. * NVIDIA Corporation <www.nvidia.com>
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <efi_loader.h>
  9. #include <env.h>
  10. #include <errno.h>
  11. #include <ns16550.h>
  12. #include <usb.h>
  13. #include <asm/io.h>
  14. #include <asm/arch-tegra/ap.h>
  15. #include <asm/arch-tegra/board.h>
  16. #include <asm/arch-tegra/cboot.h>
  17. #include <asm/arch-tegra/clk_rst.h>
  18. #include <asm/arch-tegra/pmc.h>
  19. #include <asm/arch-tegra/pmu.h>
  20. #include <asm/arch-tegra/sys_proto.h>
  21. #include <asm/arch-tegra/uart.h>
  22. #include <asm/arch-tegra/warmboot.h>
  23. #include <asm/arch-tegra/gpu.h>
  24. #include <asm/arch-tegra/usb.h>
  25. #include <asm/arch-tegra/xusb-padctl.h>
  26. #if IS_ENABLED(CONFIG_TEGRA_CLKRST)
  27. #include <asm/arch/clock.h>
  28. #endif
  29. #if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
  30. #include <asm/arch/funcmux.h>
  31. #include <asm/arch/pinmux.h>
  32. #endif
  33. #include <asm/arch/tegra.h>
  34. #ifdef CONFIG_TEGRA_CLOCK_SCALING
  35. #include <asm/arch/emc.h>
  36. #endif
  37. #include "emc.h"
  38. DECLARE_GLOBAL_DATA_PTR;
  39. #ifdef CONFIG_SPL_BUILD
  40. /* TODO(sjg@chromium.org): Remove once SPL supports device tree */
  41. U_BOOT_DEVICE(tegra_gpios) = {
  42. "gpio_tegra"
  43. };
  44. #endif
  45. __weak void pinmux_init(void) {}
  46. __weak void pin_mux_usb(void) {}
  47. __weak void pin_mux_spi(void) {}
  48. __weak void pin_mux_mmc(void) {}
  49. __weak void gpio_early_init_uart(void) {}
  50. __weak void pin_mux_display(void) {}
  51. __weak void start_cpu_fan(void) {}
  52. __weak void cboot_late_init(void) {}
  53. #if defined(CONFIG_TEGRA_NAND)
  54. __weak void pin_mux_nand(void)
  55. {
  56. funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT);
  57. }
  58. #endif
  59. /*
  60. * Routine: power_det_init
  61. * Description: turn off power detects
  62. */
  63. static void power_det_init(void)
  64. {
  65. #if defined(CONFIG_TEGRA20)
  66. struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
  67. /* turn off power detects */
  68. writel(0, &pmc->pmc_pwr_det_latch);
  69. writel(0, &pmc->pmc_pwr_det);
  70. #endif
  71. }
  72. __weak int tegra_board_id(void)
  73. {
  74. return -1;
  75. }
  76. #ifdef CONFIG_DISPLAY_BOARDINFO
  77. int checkboard(void)
  78. {
  79. int board_id = tegra_board_id();
  80. printf("Board: %s", CONFIG_TEGRA_BOARD_STRING);
  81. if (board_id != -1)
  82. printf(", ID: %d\n", board_id);
  83. printf("\n");
  84. return 0;
  85. }
  86. #endif /* CONFIG_DISPLAY_BOARDINFO */
  87. __weak int tegra_lcd_pmic_init(int board_it)
  88. {
  89. return 0;
  90. }
  91. __weak int nvidia_board_init(void)
  92. {
  93. return 0;
  94. }
  95. /*
  96. * Routine: board_init
  97. * Description: Early hardware init.
  98. */
  99. int board_init(void)
  100. {
  101. __maybe_unused int err;
  102. __maybe_unused int board_id;
  103. /* Do clocks and UART first so that printf() works */
  104. #if IS_ENABLED(CONFIG_TEGRA_CLKRST)
  105. clock_init();
  106. clock_verify();
  107. #endif
  108. tegra_gpu_config();
  109. #ifdef CONFIG_TEGRA_SPI
  110. pin_mux_spi();
  111. #endif
  112. #ifdef CONFIG_MMC_SDHCI_TEGRA
  113. pin_mux_mmc();
  114. #endif
  115. /* Init is handled automatically in the driver-model case */
  116. #if defined(CONFIG_DM_VIDEO)
  117. pin_mux_display();
  118. #endif
  119. /* boot param addr */
  120. gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
  121. power_det_init();
  122. #ifdef CONFIG_SYS_I2C_TEGRA
  123. # ifdef CONFIG_TEGRA_PMU
  124. if (pmu_set_nominal())
  125. debug("Failed to select nominal voltages\n");
  126. # ifdef CONFIG_TEGRA_CLOCK_SCALING
  127. err = board_emc_init();
  128. if (err)
  129. debug("Memory controller init failed: %d\n", err);
  130. # endif
  131. # endif /* CONFIG_TEGRA_PMU */
  132. #endif /* CONFIG_SYS_I2C_TEGRA */
  133. #ifdef CONFIG_USB_EHCI_TEGRA
  134. pin_mux_usb();
  135. #endif
  136. #if defined(CONFIG_DM_VIDEO)
  137. board_id = tegra_board_id();
  138. err = tegra_lcd_pmic_init(board_id);
  139. if (err) {
  140. debug("Failed to set up LCD PMIC\n");
  141. return err;
  142. }
  143. #endif
  144. #ifdef CONFIG_TEGRA_NAND
  145. pin_mux_nand();
  146. #endif
  147. tegra_xusb_padctl_init();
  148. #ifdef CONFIG_TEGRA_LP0
  149. /* save Sdram params to PMC 2, 4, and 24 for WB0 */
  150. warmboot_save_sdram_params();
  151. /* prepare the WB code to LP0 location */
  152. warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
  153. #endif
  154. return nvidia_board_init();
  155. }
  156. #ifdef CONFIG_BOARD_EARLY_INIT_F
  157. static void __gpio_early_init(void)
  158. {
  159. }
  160. void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init")));
  161. int board_early_init_f(void)
  162. {
  163. #if IS_ENABLED(CONFIG_TEGRA_CLKRST)
  164. if (!clock_early_init_done())
  165. clock_early_init();
  166. #endif
  167. #if defined(CONFIG_TEGRA_DISCONNECT_UDC_ON_BOOT)
  168. #define USBCMD_FS2 (1 << 15)
  169. {
  170. struct usb_ctlr *usbctlr = (struct usb_ctlr *)0x7d000000;
  171. writel(USBCMD_FS2, &usbctlr->usb_cmd);
  172. }
  173. #endif
  174. /* Do any special system timer/TSC setup */
  175. #if IS_ENABLED(CONFIG_TEGRA_CLKRST)
  176. # if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
  177. if (!tegra_cpu_is_non_secure())
  178. # endif
  179. arch_timer_init();
  180. #endif
  181. pinmux_init();
  182. board_init_uart_f();
  183. /* Initialize periph GPIOs */
  184. gpio_early_init();
  185. gpio_early_init_uart();
  186. return 0;
  187. }
  188. #endif /* EARLY_INIT */
  189. int board_late_init(void)
  190. {
  191. #if CONFIG_IS_ENABLED(EFI_LOADER)
  192. if (gd->bd->bi_dram[1].start) {
  193. /*
  194. * Only bank 0 is below board_get_usable_ram_top(), so all of
  195. * bank 1 is not mapped by the U-Boot MMU configuration, and so
  196. * we must prevent EFI from using it.
  197. */
  198. efi_add_memory_map(gd->bd->bi_dram[1].start,
  199. gd->bd->bi_dram[1].size >> EFI_PAGE_SHIFT,
  200. EFI_BOOT_SERVICES_DATA, false);
  201. }
  202. #endif
  203. #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
  204. if (tegra_cpu_is_non_secure()) {
  205. printf("CPU is in NS mode\n");
  206. env_set("cpu_ns_mode", "1");
  207. } else {
  208. env_set("cpu_ns_mode", "");
  209. }
  210. #endif
  211. start_cpu_fan();
  212. cboot_late_init();
  213. return 0;
  214. }
  215. /*
  216. * In some SW environments, a memory carve-out exists to house a secure
  217. * monitor, a trusted OS, and/or various statically allocated media buffers.
  218. *
  219. * This carveout exists at the highest possible address that is within a
  220. * 32-bit physical address space.
  221. *
  222. * This function returns the total size of this carve-out. At present, the
  223. * returned value is hard-coded for simplicity. In the future, it may be
  224. * possible to determine the carve-out size:
  225. * - By querying some run-time information source, such as:
  226. * - A structure passed to U-Boot by earlier boot software.
  227. * - SoC registers.
  228. * - A call into the secure monitor.
  229. * - In the per-board U-Boot configuration header, based on knowledge of the
  230. * SW environment that U-Boot is being built for.
  231. *
  232. * For now, we support two configurations in U-Boot:
  233. * - 32-bit ports without any form of carve-out.
  234. * - 64 bit ports which are assumed to use a carve-out of a conservatively
  235. * hard-coded size.
  236. */
  237. static ulong carveout_size(void)
  238. {
  239. #ifdef CONFIG_ARM64
  240. return SZ_512M;
  241. #elif defined(CONFIG_ARMV7_SECURE_RESERVE_SIZE)
  242. // BASE+SIZE might not == 4GB. If so, we want the carveout to cover
  243. // from BASE to 4GB, not BASE to BASE+SIZE.
  244. return (0 - CONFIG_ARMV7_SECURE_BASE) & ~(SZ_2M - 1);
  245. #else
  246. return 0;
  247. #endif
  248. }
  249. /*
  250. * Determine the amount of usable RAM below 4GiB, taking into account any
  251. * carve-out that may be assigned.
  252. */
  253. static ulong usable_ram_size_below_4g(void)
  254. {
  255. ulong total_size_below_4g;
  256. ulong usable_size_below_4g;
  257. /*
  258. * The total size of RAM below 4GiB is the lesser address of:
  259. * (a) 2GiB itself (RAM starts at 2GiB, and 4GiB - 2GiB == 2GiB).
  260. * (b) The size RAM physically present in the system.
  261. */
  262. if (gd->ram_size < SZ_2G)
  263. total_size_below_4g = gd->ram_size;
  264. else
  265. total_size_below_4g = SZ_2G;
  266. /* Calculate usable RAM by subtracting out any carve-out size */
  267. usable_size_below_4g = total_size_below_4g - carveout_size();
  268. return usable_size_below_4g;
  269. }
  270. /*
  271. * Represent all available RAM in either one or two banks.
  272. *
  273. * The first bank describes any usable RAM below 4GiB.
  274. * The second bank describes any RAM above 4GiB.
  275. *
  276. * This split is driven by the following requirements:
  277. * - The NVIDIA L4T kernel requires separate entries in the DT /memory/reg
  278. * property for memory below and above the 4GiB boundary. The layout of that
  279. * DT property is directly driven by the entries in the U-Boot bank array.
  280. * - The potential existence of a carve-out at the end of RAM below 4GiB can
  281. * only be represented using multiple banks.
  282. *
  283. * Explicitly removing the carve-out RAM from the bank entries makes the RAM
  284. * layout a bit more obvious, e.g. when running "bdinfo" at the U-Boot
  285. * command-line.
  286. *
  287. * This does mean that the DT U-Boot passes to the Linux kernel will not
  288. * include this RAM in /memory/reg at all. An alternative would be to include
  289. * all RAM in the U-Boot banks (and hence DT), and add a /memreserve/ node
  290. * into DT to stop the kernel from using the RAM. IIUC, I don't /think/ the
  291. * Linux kernel will ever need to access any RAM in* the carve-out via a CPU
  292. * mapping, so either way is acceptable.
  293. *
  294. * On 32-bit systems, we never define a bank for RAM above 4GiB, since the
  295. * start address of that bank cannot be represented in the 32-bit .size
  296. * field.
  297. */
  298. int dram_init_banksize(void)
  299. {
  300. int err;
  301. /* try to compute DRAM bank size based on cboot DTB first */
  302. err = cboot_dram_init_banksize();
  303. if (err == 0)
  304. return err;
  305. /* fall back to default DRAM bank size computation */
  306. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  307. gd->bd->bi_dram[0].size = usable_ram_size_below_4g();
  308. #ifdef CONFIG_PCI
  309. gd->pci_ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
  310. #endif
  311. #ifdef CONFIG_PHYS_64BIT
  312. if (gd->ram_size > SZ_2G) {
  313. gd->bd->bi_dram[1].start = 0x100000000;
  314. gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G;
  315. } else
  316. #endif
  317. {
  318. gd->bd->bi_dram[1].start = 0;
  319. gd->bd->bi_dram[1].size = 0;
  320. }
  321. return 0;
  322. }
  323. /*
  324. * Most hardware on 64-bit Tegra is still restricted to DMA to the lower
  325. * 32-bits of the physical address space. Cap the maximum usable RAM area
  326. * at 4 GiB to avoid DMA buffers from being allocated beyond the 32-bit
  327. * boundary that most devices can address. Also, don't let U-Boot use any
  328. * carve-out, as mentioned above.
  329. *
  330. * This function is called before dram_init_banksize(), so we can't simply
  331. * return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size.
  332. */
  333. ulong board_get_usable_ram_top(ulong total_size)
  334. {
  335. ulong ram_top;
  336. /* try to get top of usable RAM based on cboot DTB first */
  337. ram_top = cboot_get_usable_ram_top(total_size);
  338. if (ram_top > 0)
  339. return ram_top;
  340. /* fall back to default usable RAM computation */
  341. return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g();
  342. }