misc_s10.c 3.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
  4. *
  5. */
  6. #include <altera.h>
  7. #include <common.h>
  8. #include <env.h>
  9. #include <errno.h>
  10. #include <fdtdec.h>
  11. #include <miiphy.h>
  12. #include <netdev.h>
  13. #include <asm/io.h>
  14. #include <asm/arch/reset_manager.h>
  15. #include <asm/arch/system_manager.h>
  16. #include <asm/arch/misc.h>
  17. #include <asm/pl310.h>
  18. #include <linux/libfdt.h>
  19. #include <asm/arch/mailbox_s10.h>
  20. #include <dt-bindings/reset/altr,rst-mgr-s10.h>
  21. DECLARE_GLOBAL_DATA_PTR;
  22. static struct socfpga_system_manager *sysmgr_regs =
  23. (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  24. /*
  25. * FPGA programming support for SoC FPGA Stratix 10
  26. */
  27. static Altera_desc altera_fpga[] = {
  28. {
  29. /* Family */
  30. Intel_FPGA_Stratix10,
  31. /* Interface type */
  32. secure_device_manager_mailbox,
  33. /* No limitation as additional data will be ignored */
  34. -1,
  35. /* No device function table */
  36. NULL,
  37. /* Base interface address specified in driver */
  38. NULL,
  39. /* No cookie implementation */
  40. 0
  41. },
  42. };
  43. /*
  44. * DesignWare Ethernet initialization
  45. */
  46. #ifdef CONFIG_ETH_DESIGNWARE
  47. static u32 socfpga_phymode_setup(u32 gmac_index, const char *phymode)
  48. {
  49. u32 modereg;
  50. if (!phymode)
  51. return -EINVAL;
  52. if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii") ||
  53. !strcmp(phymode, "sgmii"))
  54. modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
  55. else if (!strcmp(phymode, "rgmii"))
  56. modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
  57. else if (!strcmp(phymode, "rmii"))
  58. modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
  59. else
  60. return -EINVAL;
  61. clrsetbits_le32(&sysmgr_regs->emac0 + gmac_index,
  62. SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
  63. modereg);
  64. return 0;
  65. }
  66. static int socfpga_set_phymode(void)
  67. {
  68. const void *fdt = gd->fdt_blob;
  69. struct fdtdec_phandle_args args;
  70. const char *phy_mode;
  71. u32 gmac_index;
  72. int nodes[3]; /* Max. 3 GMACs */
  73. int ret, count;
  74. int i, node;
  75. count = fdtdec_find_aliases_for_id(fdt, "ethernet",
  76. COMPAT_ALTERA_SOCFPGA_DWMAC,
  77. nodes, ARRAY_SIZE(nodes));
  78. for (i = 0; i < count; i++) {
  79. node = nodes[i];
  80. if (node <= 0)
  81. continue;
  82. ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
  83. "#reset-cells", 1, 0,
  84. &args);
  85. if (ret || args.args_count != 1) {
  86. debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
  87. continue;
  88. }
  89. gmac_index = args.args[0] - EMAC0_RESET;
  90. phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
  91. ret = socfpga_phymode_setup(gmac_index, phy_mode);
  92. if (ret) {
  93. debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
  94. continue;
  95. }
  96. }
  97. return 0;
  98. }
  99. #else
  100. static int socfpga_set_phymode(void)
  101. {
  102. return 0;
  103. };
  104. #endif
  105. /*
  106. * Print CPU information
  107. */
  108. #if defined(CONFIG_DISPLAY_CPUINFO)
  109. int print_cpuinfo(void)
  110. {
  111. puts("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)\n");
  112. return 0;
  113. }
  114. #endif
  115. #ifdef CONFIG_ARCH_MISC_INIT
  116. int arch_misc_init(void)
  117. {
  118. char qspi_string[13];
  119. sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
  120. env_set("qspi_clock", qspi_string);
  121. socfpga_set_phymode();
  122. return 0;
  123. }
  124. #endif
  125. int arch_early_init_r(void)
  126. {
  127. socfpga_fpga_add(&altera_fpga[0]);
  128. return 0;
  129. }
  130. void do_bridge_reset(int enable, unsigned int mask)
  131. {
  132. /* Check FPGA status before bridge enable */
  133. if (enable) {
  134. int ret = mbox_get_fpga_config_status(MBOX_RECONFIG_STATUS);
  135. if (ret && ret != MBOX_CFGSTAT_STATE_CONFIG)
  136. ret = mbox_get_fpga_config_status(MBOX_CONFIG_STATUS);
  137. if (ret)
  138. return;
  139. }
  140. socfpga_bridges_reset(enable);
  141. }