misc_gen5.c 6.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
  4. */
  5. #include <common.h>
  6. #include <asm/io.h>
  7. #include <env.h>
  8. #include <errno.h>
  9. #include <fdtdec.h>
  10. #include <linux/libfdt.h>
  11. #include <altera.h>
  12. #include <miiphy.h>
  13. #include <netdev.h>
  14. #include <watchdog.h>
  15. #include <asm/arch/misc.h>
  16. #include <asm/arch/reset_manager.h>
  17. #include <asm/arch/scan_manager.h>
  18. #include <asm/arch/sdram.h>
  19. #include <asm/arch/system_manager.h>
  20. #include <asm/arch/nic301.h>
  21. #include <asm/arch/scu.h>
  22. #include <asm/pl310.h>
  23. #include <dt-bindings/reset/altr,rst-mgr.h>
  24. DECLARE_GLOBAL_DATA_PTR;
  25. static struct pl310_regs *const pl310 =
  26. (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  27. static struct socfpga_system_manager *sysmgr_regs =
  28. (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  29. static struct nic301_registers *nic301_regs =
  30. (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
  31. static struct scu_registers *scu_regs =
  32. (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
  33. /*
  34. * FPGA programming support for SoC FPGA Cyclone V
  35. */
  36. static Altera_desc altera_fpga[] = {
  37. {
  38. /* Family */
  39. Altera_SoCFPGA,
  40. /* Interface type */
  41. fast_passive_parallel,
  42. /* No limitation as additional data will be ignored */
  43. -1,
  44. /* No device function table */
  45. NULL,
  46. /* Base interface address specified in driver */
  47. NULL,
  48. /* No cookie implementation */
  49. 0
  50. },
  51. };
  52. static const struct {
  53. const u16 pn;
  54. const char *name;
  55. const char *var;
  56. } socfpga_fpga_model[] = {
  57. /* Cyclone V E */
  58. { 0x2b15, "Cyclone V, E/A2", "cv_e_a2" },
  59. { 0x2b05, "Cyclone V, E/A4", "cv_e_a4" },
  60. { 0x2b22, "Cyclone V, E/A5", "cv_e_a5" },
  61. { 0x2b13, "Cyclone V, E/A7", "cv_e_a7" },
  62. { 0x2b14, "Cyclone V, E/A9", "cv_e_a9" },
  63. /* Cyclone V GX/GT */
  64. { 0x2b01, "Cyclone V, GX/C3", "cv_gx_c3" },
  65. { 0x2b12, "Cyclone V, GX/C4", "cv_gx_c4" },
  66. { 0x2b02, "Cyclone V, GX/C5 or GT/D5", "cv_gx_c5" },
  67. { 0x2b03, "Cyclone V, GX/C7 or GT/D7", "cv_gx_c7" },
  68. { 0x2b04, "Cyclone V, GX/C9 or GT/D9", "cv_gx_c9" },
  69. /* Cyclone V SE/SX/ST */
  70. { 0x2d11, "Cyclone V, SE/A2 or SX/C2", "cv_se_a2" },
  71. { 0x2d01, "Cyclone V, SE/A4 or SX/C4", "cv_se_a4" },
  72. { 0x2d12, "Cyclone V, SE/A5 or SX/C5 or ST/D5", "cv_se_a5" },
  73. { 0x2d02, "Cyclone V, SE/A6 or SX/C6 or ST/D6", "cv_se_a6" },
  74. /* Arria V */
  75. { 0x2d03, "Arria V, D5", "av_d5" },
  76. };
  77. static int socfpga_fpga_id(const bool print_id)
  78. {
  79. const u32 altera_mi = 0x6e;
  80. const u32 id = scan_mgr_get_fpga_id();
  81. const u32 lsb = id & 0x00000001;
  82. const u32 mi = (id >> 1) & 0x000007ff;
  83. const u32 pn = (id >> 12) & 0x0000ffff;
  84. const u32 version = (id >> 28) & 0x0000000f;
  85. int i;
  86. if ((mi != altera_mi) || (lsb != 1)) {
  87. printf("FPGA: Not Altera chip ID\n");
  88. return -EINVAL;
  89. }
  90. for (i = 0; i < ARRAY_SIZE(socfpga_fpga_model); i++)
  91. if (pn == socfpga_fpga_model[i].pn)
  92. break;
  93. if (i == ARRAY_SIZE(socfpga_fpga_model)) {
  94. printf("FPGA: Unknown Altera chip, ID 0x%08x\n", id);
  95. return -EINVAL;
  96. }
  97. if (print_id)
  98. printf("FPGA: Altera %s, version 0x%01x\n",
  99. socfpga_fpga_model[i].name, version);
  100. return i;
  101. }
  102. /*
  103. * Print CPU information
  104. */
  105. #if defined(CONFIG_DISPLAY_CPUINFO)
  106. int print_cpuinfo(void)
  107. {
  108. const u32 bsel =
  109. SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo));
  110. puts("CPU: Altera SoCFPGA Platform\n");
  111. socfpga_fpga_id(1);
  112. printf("BOOT: %s\n", bsel_str[bsel].name);
  113. return 0;
  114. }
  115. #endif
  116. #ifdef CONFIG_ARCH_MISC_INIT
  117. int arch_misc_init(void)
  118. {
  119. const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
  120. const int fpga_id = socfpga_fpga_id(0);
  121. env_set("bootmode", bsel_str[bsel].mode);
  122. if (fpga_id >= 0)
  123. env_set("fpgatype", socfpga_fpga_model[fpga_id].var);
  124. return 0;
  125. }
  126. #endif
  127. /*
  128. * Convert all NIC-301 AMBA slaves from secure to non-secure
  129. */
  130. static void socfpga_nic301_slave_ns(void)
  131. {
  132. writel(0x1, &nic301_regs->lwhps2fpgaregs);
  133. writel(0x1, &nic301_regs->hps2fpgaregs);
  134. writel(0x1, &nic301_regs->acp);
  135. writel(0x1, &nic301_regs->rom);
  136. writel(0x1, &nic301_regs->ocram);
  137. writel(0x1, &nic301_regs->sdrdata);
  138. }
  139. void socfpga_sdram_remap_zero(void)
  140. {
  141. u32 remap;
  142. socfpga_nic301_slave_ns();
  143. /*
  144. * Private components security:
  145. * U-Boot : configure private timer, global timer and cpu component
  146. * access as non secure for kernel stage (as required by Linux)
  147. */
  148. setbits_le32(&scu_regs->sacr, 0xfff);
  149. /* Configure the L2 controller to make SDRAM start at 0 */
  150. remap = 0x1; /* remap.mpuzero */
  151. /* Keep fpga bridge enabled when running from FPGA onchip RAM */
  152. if (socfpga_is_booting_from_fpga())
  153. remap |= 0x8; /* remap.hps2fpga */
  154. writel(remap, &nic301_regs->remap);
  155. writel(0x1, &pl310->pl310_addr_filter_start);
  156. }
  157. static u32 iswgrp_handoff[8];
  158. int arch_early_init_r(void)
  159. {
  160. int i;
  161. /*
  162. * Write magic value into magic register to unlock support for
  163. * issuing warm reset. The ancient kernel code expects this
  164. * value to be written into the register by the bootloader, so
  165. * to support that old code, we write it here instead of in the
  166. * reset_cpu() function just before resetting the CPU.
  167. */
  168. writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable);
  169. for (i = 0; i < 8; i++) /* Cache initial SW setting regs */
  170. iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
  171. socfpga_bridges_reset(1);
  172. socfpga_sdram_remap_zero();
  173. /* Add device descriptor to FPGA device table */
  174. socfpga_fpga_add(&altera_fpga[0]);
  175. return 0;
  176. }
  177. #ifndef CONFIG_SPL_BUILD
  178. static struct socfpga_reset_manager *reset_manager_base =
  179. (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
  180. static struct socfpga_sdr_ctrl *sdr_ctrl =
  181. (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
  182. void do_bridge_reset(int enable, unsigned int mask)
  183. {
  184. int i;
  185. if (enable) {
  186. socfpga_bridges_set_handoff_regs(!(mask & BIT(0)),
  187. !(mask & BIT(1)),
  188. !(mask & BIT(2)));
  189. for (i = 0; i < 2; i++) { /* Reload SW setting cache */
  190. iswgrp_handoff[i] =
  191. readl(&sysmgr_regs->iswgrp_handoff[i]);
  192. }
  193. writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
  194. writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
  195. writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
  196. writel(iswgrp_handoff[1], &nic301_regs->remap);
  197. } else {
  198. writel(0, &sysmgr_regs->fpgaintfgrp_module);
  199. writel(0, &sdr_ctrl->fpgaport_rst);
  200. writel(0, &reset_manager_base->brg_mod_reset);
  201. writel(1, &nic301_regs->remap);
  202. }
  203. }
  204. #endif