rk3288.c 4.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2016 Rockchip Electronics Co., Ltd
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <env.h>
  8. #include <clk.h>
  9. #include <asm/armv7.h>
  10. #include <asm/io.h>
  11. #include <asm/arch-rockchip/bootrom.h>
  12. #include <asm/arch-rockchip/clock.h>
  13. #include <asm/arch-rockchip/cru_rk3288.h>
  14. #include <asm/arch-rockchip/hardware.h>
  15. #include <asm/arch-rockchip/grf_rk3288.h>
  16. #include <asm/arch-rockchip/pmu_rk3288.h>
  17. #include <asm/arch-rockchip/qos_rk3288.h>
  18. #include <asm/arch-rockchip/sdram_common.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. #define GRF_BASE 0xff770000
  21. const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
  22. [BROM_BOOTSOURCE_EMMC] = "dwmmc@ff0f0000",
  23. [BROM_BOOTSOURCE_SD] = "dwmmc@ff0c0000",
  24. };
  25. #ifdef CONFIG_SPL_BUILD
  26. static void configure_l2ctlr(void)
  27. {
  28. u32 l2ctlr;
  29. l2ctlr = read_l2ctlr();
  30. l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
  31. /*
  32. * Data RAM write latency: 2 cycles
  33. * Data RAM read latency: 2 cycles
  34. * Data RAM setup latency: 1 cycle
  35. * Tag RAM write latency: 1 cycle
  36. * Tag RAM read latency: 1 cycle
  37. * Tag RAM setup latency: 1 cycle
  38. */
  39. l2ctlr |= (1 << 3 | 1 << 0);
  40. write_l2ctlr(l2ctlr);
  41. }
  42. #endif
  43. int rk3288_qos_init(void)
  44. {
  45. int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT;
  46. /* set vop qos to higher priority */
  47. writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS);
  48. writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS);
  49. if (!fdt_node_check_compatible(gd->fdt_blob, 0,
  50. "rockchip,rk3288-tinker")) {
  51. /* set isp qos to higher priority */
  52. writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS);
  53. writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS);
  54. writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS);
  55. }
  56. return 0;
  57. }
  58. int arch_cpu_init(void)
  59. {
  60. #ifdef CONFIG_SPL_BUILD
  61. configure_l2ctlr();
  62. #else
  63. /* We do some SoC one time setting here. */
  64. struct rk3288_grf * const grf = (void *)GRF_BASE;
  65. /* Use rkpwm by default */
  66. rk_setreg(&grf->soc_con2, 1 << 0);
  67. /*
  68. * Disable JTAG on sdmmc0 IO. The SDMMC won't work until this bit is
  69. * cleared
  70. */
  71. rk_clrreg(&grf->soc_con0, 1 << 12);
  72. rk3288_qos_init();
  73. #endif
  74. return 0;
  75. }
  76. #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  77. void board_debug_uart_init(void)
  78. {
  79. /* Enable early UART on the RK3288 */
  80. struct rk3288_grf * const grf = (void *)GRF_BASE;
  81. rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
  82. GPIO7C6_MASK << GPIO7C6_SHIFT,
  83. GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
  84. GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
  85. }
  86. #endif
  87. static void rk3288_detect_reset_reason(void)
  88. {
  89. struct rk3288_cru *cru = rockchip_get_cru();
  90. const char *reason;
  91. if (IS_ERR(cru))
  92. return;
  93. switch (cru->cru_glb_rst_st) {
  94. case GLB_POR_RST:
  95. reason = "POR";
  96. break;
  97. case FST_GLB_RST_ST:
  98. case SND_GLB_RST_ST:
  99. reason = "RST";
  100. break;
  101. case FST_GLB_TSADC_RST_ST:
  102. case SND_GLB_TSADC_RST_ST:
  103. reason = "THERMAL";
  104. break;
  105. case FST_GLB_WDT_RST_ST:
  106. case SND_GLB_WDT_RST_ST:
  107. reason = "WDOG";
  108. break;
  109. default:
  110. reason = "unknown reset";
  111. }
  112. env_set("reset_reason", reason);
  113. /*
  114. * Clear cru_glb_rst_st, so we can determine the last reset cause
  115. * for following resets.
  116. */
  117. rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK);
  118. }
  119. __weak int rk3288_board_late_init(void)
  120. {
  121. return 0;
  122. }
  123. int rk_board_late_init(void)
  124. {
  125. rk3288_detect_reset_reason();
  126. return rk3288_board_late_init();
  127. }
  128. static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc,
  129. char * const argv[])
  130. {
  131. static const struct {
  132. char *name;
  133. int id;
  134. } clks[] = {
  135. { "osc", CLK_OSC },
  136. { "apll", CLK_ARM },
  137. { "dpll", CLK_DDR },
  138. { "cpll", CLK_CODEC },
  139. { "gpll", CLK_GENERAL },
  140. #ifdef CONFIG_ROCKCHIP_RK3036
  141. { "mpll", CLK_NEW },
  142. #else
  143. { "npll", CLK_NEW },
  144. #endif
  145. };
  146. int ret, i;
  147. struct udevice *dev;
  148. ret = rockchip_get_clk(&dev);
  149. if (ret) {
  150. printf("clk-uclass not found\n");
  151. return 0;
  152. }
  153. for (i = 0; i < ARRAY_SIZE(clks); i++) {
  154. struct clk clk;
  155. ulong rate;
  156. clk.id = clks[i].id;
  157. ret = clk_request(dev, &clk);
  158. if (ret < 0)
  159. continue;
  160. rate = clk_get_rate(&clk);
  161. printf("%s: %lu\n", clks[i].name, rate);
  162. clk_free(&clk);
  163. }
  164. return 0;
  165. }
  166. U_BOOT_CMD(
  167. clock, 2, 1, do_clock,
  168. "display information about clocks",
  169. ""
  170. );