soc.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014-2015 Freescale Semiconductor
  4. * Copyright 2019 NXP
  5. */
  6. #include <common.h>
  7. #include <env.h>
  8. #include <fsl_immap.h>
  9. #include <fsl_ifc.h>
  10. #include <asm/arch/fsl_serdes.h>
  11. #include <asm/arch/soc.h>
  12. #include <asm/io.h>
  13. #include <asm/global_data.h>
  14. #include <asm/arch-fsl-layerscape/config.h>
  15. #include <asm/arch-fsl-layerscape/ns_access.h>
  16. #include <asm/arch-fsl-layerscape/fsl_icid.h>
  17. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  18. #include <fsl_csu.h>
  19. #endif
  20. #ifdef CONFIG_SYS_FSL_DDR
  21. #include <fsl_ddr_sdram.h>
  22. #include <fsl_ddr.h>
  23. #endif
  24. #ifdef CONFIG_CHAIN_OF_TRUST
  25. #include <fsl_validate.h>
  26. #endif
  27. #include <fsl_immap.h>
  28. #ifdef CONFIG_TFABOOT
  29. #include <environment.h>
  30. DECLARE_GLOBAL_DATA_PTR;
  31. #endif
  32. bool soc_has_dp_ddr(void)
  33. {
  34. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  35. u32 svr = gur_in32(&gur->svr);
  36. /* LS2085A, LS2088A, LS2048A has DP_DDR */
  37. if ((SVR_SOC_VER(svr) == SVR_LS2085A) ||
  38. (SVR_SOC_VER(svr) == SVR_LS2088A) ||
  39. (SVR_SOC_VER(svr) == SVR_LS2048A))
  40. return true;
  41. return false;
  42. }
  43. bool soc_has_aiop(void)
  44. {
  45. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  46. u32 svr = gur_in32(&gur->svr);
  47. /* LS2085A has AIOP */
  48. if (SVR_SOC_VER(svr) == SVR_LS2085A)
  49. return true;
  50. return false;
  51. }
  52. static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)
  53. {
  54. scfg_clrsetbits32(scfg + offset / 4,
  55. 0xF << 6,
  56. SCFG_USB_TXVREFTUNE << 6);
  57. }
  58. static void erratum_a009008(void)
  59. {
  60. #ifdef CONFIG_SYS_FSL_ERRATUM_A009008
  61. u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
  62. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  63. defined(CONFIG_ARCH_LS1012A)
  64. set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);
  65. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  66. set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2);
  67. set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3);
  68. #endif
  69. #elif defined(CONFIG_ARCH_LS2080A)
  70. set_usb_txvreftune(scfg, SCFG_USB3PRM1CR);
  71. #endif
  72. #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
  73. }
  74. static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset)
  75. {
  76. scfg_clrbits32(scfg + offset / 4,
  77. SCFG_USB_SQRXTUNE_MASK << 23);
  78. }
  79. static void erratum_a009798(void)
  80. {
  81. #ifdef CONFIG_SYS_FSL_ERRATUM_A009798
  82. u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
  83. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  84. defined(CONFIG_ARCH_LS1012A)
  85. set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1);
  86. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  87. set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2);
  88. set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3);
  89. #endif
  90. #elif defined(CONFIG_ARCH_LS2080A)
  91. set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR);
  92. #endif
  93. #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
  94. }
  95. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  96. defined(CONFIG_ARCH_LS1012A)
  97. static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset)
  98. {
  99. scfg_clrsetbits32(scfg + offset / 4,
  100. 0x7F << 9,
  101. SCFG_USB_PCSTXSWINGFULL << 9);
  102. }
  103. #endif
  104. static void erratum_a008997(void)
  105. {
  106. #ifdef CONFIG_SYS_FSL_ERRATUM_A008997
  107. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  108. defined(CONFIG_ARCH_LS1012A)
  109. u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
  110. set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1);
  111. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  112. set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2);
  113. set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3);
  114. #endif
  115. #elif defined(CONFIG_ARCH_LS1028A)
  116. clrsetbits_le32(DCSR_BASE + DCSR_USB_IOCR1,
  117. 0x7F << 11,
  118. DCSR_USB_PCSTXSWINGFULL << 11);
  119. #endif
  120. #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
  121. }
  122. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  123. defined(CONFIG_ARCH_LS1012A)
  124. #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
  125. out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
  126. out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
  127. out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
  128. out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
  129. #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
  130. defined(CONFIG_ARCH_LS1028A)
  131. #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
  132. out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
  133. out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
  134. out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
  135. out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
  136. #endif
  137. static void erratum_a009007(void)
  138. {
  139. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  140. defined(CONFIG_ARCH_LS1012A)
  141. void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1;
  142. PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
  143. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  144. usb_phy = (void __iomem *)SCFG_USB_PHY2;
  145. PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
  146. usb_phy = (void __iomem *)SCFG_USB_PHY3;
  147. PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
  148. #endif
  149. #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
  150. defined(CONFIG_ARCH_LS1028A)
  151. void __iomem *dcsr = (void __iomem *)DCSR_BASE;
  152. PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
  153. PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
  154. #endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
  155. }
  156. #if defined(CONFIG_FSL_LSCH3)
  157. /*
  158. * This erratum requires setting a value to eddrtqcr1 to
  159. * optimal the DDR performance.
  160. */
  161. static void erratum_a008336(void)
  162. {
  163. #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
  164. u32 *eddrtqcr1;
  165. #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
  166. eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
  167. if (fsl_ddr_get_version(0) == 0x50200)
  168. out_le32(eddrtqcr1, 0x63b30002);
  169. #endif
  170. #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
  171. eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
  172. if (fsl_ddr_get_version(0) == 0x50200)
  173. out_le32(eddrtqcr1, 0x63b30002);
  174. #endif
  175. #endif
  176. }
  177. /*
  178. * This erratum requires a register write before being Memory
  179. * controller 3 being enabled.
  180. */
  181. static void erratum_a008514(void)
  182. {
  183. #ifdef CONFIG_SYS_FSL_ERRATUM_A008514
  184. u32 *eddrtqcr1;
  185. #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
  186. eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
  187. out_le32(eddrtqcr1, 0x63b20002);
  188. #endif
  189. #endif
  190. }
  191. #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
  192. #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
  193. static unsigned long get_internval_val_mhz(void)
  194. {
  195. char *interval = env_get(PLATFORM_CYCLE_ENV_VAR);
  196. /*
  197. * interval is the number of platform cycles(MHz) between
  198. * wake up events generated by EPU.
  199. */
  200. ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
  201. if (interval)
  202. interval_mhz = simple_strtoul(interval, NULL, 10);
  203. return interval_mhz;
  204. }
  205. void erratum_a009635(void)
  206. {
  207. u32 val;
  208. unsigned long interval_mhz = get_internval_val_mhz();
  209. if (!interval_mhz)
  210. return;
  211. val = in_le32(DCSR_CGACRE5);
  212. writel(val | 0x00000200, DCSR_CGACRE5);
  213. val = in_le32(EPU_EPCMPR5);
  214. writel(interval_mhz, EPU_EPCMPR5);
  215. val = in_le32(EPU_EPCCR5);
  216. writel(val | 0x82820000, EPU_EPCCR5);
  217. val = in_le32(EPU_EPSMCR5);
  218. writel(val | 0x002f0000, EPU_EPSMCR5);
  219. val = in_le32(EPU_EPECR5);
  220. writel(val | 0x20000000, EPU_EPECR5);
  221. val = in_le32(EPU_EPGCR);
  222. writel(val | 0x80000000, EPU_EPGCR);
  223. }
  224. #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */
  225. static void erratum_rcw_src(void)
  226. {
  227. #if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT)
  228. u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
  229. u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
  230. u32 val;
  231. val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
  232. val &= ~DCFG_PORSR1_RCW_SRC;
  233. val |= DCFG_PORSR1_RCW_SRC_NOR;
  234. out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
  235. #endif
  236. }
  237. #define I2C_DEBUG_REG 0x6
  238. #define I2C_GLITCH_EN 0x8
  239. /*
  240. * This erratum requires setting glitch_en bit to enable
  241. * digital glitch filter to improve clock stability.
  242. */
  243. #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
  244. static void erratum_a009203(void)
  245. {
  246. #ifdef CONFIG_SYS_I2C
  247. u8 __iomem *ptr;
  248. #ifdef I2C1_BASE_ADDR
  249. ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
  250. writeb(I2C_GLITCH_EN, ptr);
  251. #endif
  252. #ifdef I2C2_BASE_ADDR
  253. ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
  254. writeb(I2C_GLITCH_EN, ptr);
  255. #endif
  256. #ifdef I2C3_BASE_ADDR
  257. ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
  258. writeb(I2C_GLITCH_EN, ptr);
  259. #endif
  260. #ifdef I2C4_BASE_ADDR
  261. ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
  262. writeb(I2C_GLITCH_EN, ptr);
  263. #endif
  264. #endif
  265. }
  266. #endif
  267. void bypass_smmu(void)
  268. {
  269. u32 val;
  270. val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
  271. out_le32(SMMU_SCR0, val);
  272. val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
  273. out_le32(SMMU_NSCR0, val);
  274. }
  275. void fsl_lsch3_early_init_f(void)
  276. {
  277. erratum_rcw_src();
  278. #ifdef CONFIG_FSL_IFC
  279. init_early_memctl_regs(); /* tighten IFC timing */
  280. #endif
  281. #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
  282. erratum_a009203();
  283. #endif
  284. erratum_a008514();
  285. erratum_a008336();
  286. erratum_a009008();
  287. erratum_a009798();
  288. erratum_a008997();
  289. erratum_a009007();
  290. #ifdef CONFIG_CHAIN_OF_TRUST
  291. /* In case of Secure Boot, the IBR configures the SMMU
  292. * to allow only Secure transactions.
  293. * SMMU must be reset in bypass mode.
  294. * Set the ClientPD bit and Clear the USFCFG Bit
  295. */
  296. if (fsl_check_boot_mode_secure() == 1)
  297. bypass_smmu();
  298. #endif
  299. }
  300. /* Get VDD in the unit mV from voltage ID */
  301. int get_core_volt_from_fuse(void)
  302. {
  303. struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  304. int vdd;
  305. u32 fusesr;
  306. u8 vid;
  307. /* get the voltage ID from fuse status register */
  308. fusesr = in_le32(&gur->dcfg_fusesr);
  309. debug("%s: fusesr = 0x%x\n", __func__, fusesr);
  310. vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
  311. FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
  312. if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
  313. vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
  314. FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
  315. }
  316. debug("%s: VID = 0x%x\n", __func__, vid);
  317. switch (vid) {
  318. case 0x00: /* VID isn't supported */
  319. vdd = -EINVAL;
  320. debug("%s: The VID feature is not supported\n", __func__);
  321. break;
  322. case 0x08: /* 0.9V silicon */
  323. vdd = 900;
  324. break;
  325. case 0x10: /* 1.0V silicon */
  326. vdd = 1000;
  327. break;
  328. default: /* Other core voltage */
  329. vdd = -EINVAL;
  330. debug("%s: The VID(%x) isn't supported\n", __func__, vid);
  331. break;
  332. }
  333. debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
  334. return vdd;
  335. }
  336. #elif defined(CONFIG_FSL_LSCH2)
  337. static void erratum_a009929(void)
  338. {
  339. #ifdef CONFIG_SYS_FSL_ERRATUM_A009929
  340. struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  341. u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR;
  342. u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);
  343. rstrqmr1 |= 0x00000400;
  344. gur_out32(&gur->rstrqmr1, rstrqmr1);
  345. writel(0x01000000, dcsr_cop_ccp);
  346. #endif
  347. }
  348. /*
  349. * This erratum requires setting a value to eddrtqcr1 to optimal
  350. * the DDR performance. The eddrtqcr1 register is in SCFG space
  351. * of LS1043A and the offset is 0x157_020c.
  352. */
  353. #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
  354. && defined(CONFIG_SYS_FSL_ERRATUM_A008514)
  355. #error A009660 and A008514 can not be both enabled.
  356. #endif
  357. static void erratum_a009660(void)
  358. {
  359. #ifdef CONFIG_SYS_FSL_ERRATUM_A009660
  360. u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
  361. out_be32(eddrtqcr1, 0x63b20042);
  362. #endif
  363. }
  364. static void erratum_a008850_early(void)
  365. {
  366. #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
  367. /* part 1 of 2 */
  368. struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
  369. CONFIG_SYS_CCI400_OFFSET);
  370. struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  371. /* Skip if running at lower exception level */
  372. if (current_el() < 3)
  373. return;
  374. /* disables propagation of barrier transactions to DDRC from CCI400 */
  375. out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
  376. /* disable the re-ordering in DDRC */
  377. ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
  378. #endif
  379. }
  380. void erratum_a008850_post(void)
  381. {
  382. #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
  383. /* part 2 of 2 */
  384. struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
  385. CONFIG_SYS_CCI400_OFFSET);
  386. struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  387. u32 tmp;
  388. /* Skip if running at lower exception level */
  389. if (current_el() < 3)
  390. return;
  391. /* enable propagation of barrier transactions to DDRC from CCI400 */
  392. out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
  393. /* enable the re-ordering in DDRC */
  394. tmp = ddr_in32(&ddr->eor);
  395. tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
  396. ddr_out32(&ddr->eor, tmp);
  397. #endif
  398. }
  399. #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
  400. void erratum_a010315(void)
  401. {
  402. int i;
  403. for (i = PCIE1; i <= PCIE4; i++)
  404. if (!is_serdes_configured(i)) {
  405. debug("PCIe%d: disabled all R/W permission!\n", i);
  406. set_pcie_ns_access(i, 0);
  407. }
  408. }
  409. #endif
  410. static void erratum_a010539(void)
  411. {
  412. #if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
  413. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  414. u32 porsr1;
  415. porsr1 = in_be32(&gur->porsr1);
  416. porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
  417. out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
  418. porsr1);
  419. out_be32((void *)(CONFIG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
  420. #endif
  421. }
  422. /* Get VDD in the unit mV from voltage ID */
  423. int get_core_volt_from_fuse(void)
  424. {
  425. struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  426. int vdd;
  427. u32 fusesr;
  428. u8 vid;
  429. fusesr = in_be32(&gur->dcfg_fusesr);
  430. debug("%s: fusesr = 0x%x\n", __func__, fusesr);
  431. vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
  432. FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
  433. if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
  434. vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
  435. FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
  436. }
  437. debug("%s: VID = 0x%x\n", __func__, vid);
  438. switch (vid) {
  439. case 0x00: /* VID isn't supported */
  440. vdd = -EINVAL;
  441. debug("%s: The VID feature is not supported\n", __func__);
  442. break;
  443. case 0x08: /* 0.9V silicon */
  444. vdd = 900;
  445. break;
  446. case 0x10: /* 1.0V silicon */
  447. vdd = 1000;
  448. break;
  449. default: /* Other core voltage */
  450. vdd = -EINVAL;
  451. printf("%s: The VID(%x) isn't supported\n", __func__, vid);
  452. break;
  453. }
  454. debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
  455. return vdd;
  456. }
  457. __weak int board_switch_core_volt(u32 vdd)
  458. {
  459. return 0;
  460. }
  461. static int setup_core_volt(u32 vdd)
  462. {
  463. return board_setup_core_volt(vdd);
  464. }
  465. #ifdef CONFIG_SYS_FSL_DDR
  466. static void ddr_enable_0v9_volt(bool en)
  467. {
  468. struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  469. u32 tmp;
  470. tmp = ddr_in32(&ddr->ddr_cdr1);
  471. if (en)
  472. tmp |= DDR_CDR1_V0PT9_EN;
  473. else
  474. tmp &= ~DDR_CDR1_V0PT9_EN;
  475. ddr_out32(&ddr->ddr_cdr1, tmp);
  476. }
  477. #endif
  478. int setup_chip_volt(void)
  479. {
  480. int vdd;
  481. vdd = get_core_volt_from_fuse();
  482. /* Nothing to do for silicons doesn't support VID */
  483. if (vdd < 0)
  484. return vdd;
  485. if (setup_core_volt(vdd))
  486. printf("%s: Switch core VDD to %dmV failed\n", __func__, vdd);
  487. #ifdef CONFIG_SYS_HAS_SERDES
  488. if (setup_serdes_volt(vdd))
  489. printf("%s: Switch SVDD to %dmV failed\n", __func__, vdd);
  490. #endif
  491. #ifdef CONFIG_SYS_FSL_DDR
  492. if (vdd == 900)
  493. ddr_enable_0v9_volt(true);
  494. #endif
  495. return 0;
  496. }
  497. #ifdef CONFIG_FSL_PFE
  498. void init_pfe_scfg_dcfg_regs(void)
  499. {
  500. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  501. u32 ecccr2;
  502. out_be32(&scfg->pfeasbcr,
  503. in_be32(&scfg->pfeasbcr) | SCFG_PFEASBCR_AWCACHE0);
  504. out_be32(&scfg->pfebsbcr,
  505. in_be32(&scfg->pfebsbcr) | SCFG_PFEASBCR_AWCACHE0);
  506. /* CCI-400 QoS settings for PFE */
  507. out_be32(&scfg->wr_qos1, (unsigned int)(SCFG_WR_QOS1_PFE1_QOS
  508. | SCFG_WR_QOS1_PFE2_QOS));
  509. out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS
  510. | SCFG_RD_QOS1_PFE2_QOS));
  511. ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
  512. out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
  513. ecccr2 | (unsigned int)DISABLE_PFE_ECC);
  514. }
  515. #endif
  516. void fsl_lsch2_early_init_f(void)
  517. {
  518. struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
  519. CONFIG_SYS_CCI400_OFFSET);
  520. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  521. #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
  522. enum boot_src src;
  523. #endif
  524. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  525. enable_layerscape_ns_access();
  526. #endif
  527. #ifdef CONFIG_FSL_IFC
  528. init_early_memctl_regs(); /* tighten IFC timing */
  529. #endif
  530. #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
  531. src = get_boot_src();
  532. if (src != BOOT_SOURCE_QSPI_NOR)
  533. out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
  534. #else
  535. #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
  536. out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
  537. #endif
  538. #endif
  539. /* Make SEC reads and writes snoopable */
  540. setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
  541. SCFG_SNPCNFGCR_SECWRSNP |
  542. SCFG_SNPCNFGCR_SATARDSNP |
  543. SCFG_SNPCNFGCR_SATAWRSNP);
  544. /*
  545. * Enable snoop requests and DVM message requests for
  546. * Slave insterface S4 (A53 core cluster)
  547. */
  548. if (current_el() == 3) {
  549. out_le32(&cci->slave[4].snoop_ctrl,
  550. CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
  551. }
  552. /*
  553. * Program Central Security Unit (CSU) to grant access
  554. * permission for USB 2.0 controller
  555. */
  556. #if defined(CONFIG_ARCH_LS1012A) && defined(CONFIG_USB_EHCI_FSL)
  557. if (current_el() == 3)
  558. set_devices_ns_access(CSU_CSLX_USB_2, CSU_ALL_RW);
  559. #endif
  560. /* Erratum */
  561. erratum_a008850_early(); /* part 1 of 2 */
  562. erratum_a009929();
  563. erratum_a009660();
  564. erratum_a010539();
  565. erratum_a009008();
  566. erratum_a009798();
  567. erratum_a008997();
  568. erratum_a009007();
  569. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  570. set_icids();
  571. #endif
  572. }
  573. #endif
  574. #ifdef CONFIG_QSPI_AHB_INIT
  575. /* Enable 4bytes address support and fast read */
  576. int qspi_ahb_init(void)
  577. {
  578. u32 *qspi_lut, lut_key, *qspi_key;
  579. qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300;
  580. qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310;
  581. lut_key = in_be32(qspi_key);
  582. if (lut_key == 0x5af05af0) {
  583. /* That means the register is BE */
  584. out_be32(qspi_key, 0x5af05af0);
  585. /* Unlock the lut table */
  586. out_be32(qspi_key + 1, 0x00000002);
  587. out_be32(qspi_lut, 0x0820040c);
  588. out_be32(qspi_lut + 1, 0x1c080c08);
  589. out_be32(qspi_lut + 2, 0x00002400);
  590. /* Lock the lut table */
  591. out_be32(qspi_key, 0x5af05af0);
  592. out_be32(qspi_key + 1, 0x00000001);
  593. } else {
  594. /* That means the register is LE */
  595. out_le32(qspi_key, 0x5af05af0);
  596. /* Unlock the lut table */
  597. out_le32(qspi_key + 1, 0x00000002);
  598. out_le32(qspi_lut, 0x0820040c);
  599. out_le32(qspi_lut + 1, 0x1c080c08);
  600. out_le32(qspi_lut + 2, 0x00002400);
  601. /* Lock the lut table */
  602. out_le32(qspi_key, 0x5af05af0);
  603. out_le32(qspi_key + 1, 0x00000001);
  604. }
  605. return 0;
  606. }
  607. #endif
  608. #ifdef CONFIG_TFABOOT
  609. #define MAX_BOOTCMD_SIZE 512
  610. int fsl_setenv_bootcmd(void)
  611. {
  612. int ret;
  613. enum boot_src src = get_boot_src();
  614. char bootcmd_str[MAX_BOOTCMD_SIZE];
  615. switch (src) {
  616. #ifdef IFC_NOR_BOOTCOMMAND
  617. case BOOT_SOURCE_IFC_NOR:
  618. sprintf(bootcmd_str, IFC_NOR_BOOTCOMMAND);
  619. break;
  620. #endif
  621. #ifdef QSPI_NOR_BOOTCOMMAND
  622. case BOOT_SOURCE_QSPI_NOR:
  623. sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
  624. break;
  625. #endif
  626. #ifdef XSPI_NOR_BOOTCOMMAND
  627. case BOOT_SOURCE_XSPI_NOR:
  628. sprintf(bootcmd_str, XSPI_NOR_BOOTCOMMAND);
  629. break;
  630. #endif
  631. #ifdef IFC_NAND_BOOTCOMMAND
  632. case BOOT_SOURCE_IFC_NAND:
  633. sprintf(bootcmd_str, IFC_NAND_BOOTCOMMAND);
  634. break;
  635. #endif
  636. #ifdef QSPI_NAND_BOOTCOMMAND
  637. case BOOT_SOURCE_QSPI_NAND:
  638. sprintf(bootcmd_str, QSPI_NAND_BOOTCOMMAND);
  639. break;
  640. #endif
  641. #ifdef XSPI_NAND_BOOTCOMMAND
  642. case BOOT_SOURCE_XSPI_NAND:
  643. sprintf(bootcmd_str, XSPI_NAND_BOOTCOMMAND);
  644. break;
  645. #endif
  646. #ifdef SD_BOOTCOMMAND
  647. case BOOT_SOURCE_SD_MMC:
  648. sprintf(bootcmd_str, SD_BOOTCOMMAND);
  649. break;
  650. #endif
  651. #ifdef SD2_BOOTCOMMAND
  652. case BOOT_SOURCE_SD_MMC2:
  653. sprintf(bootcmd_str, SD2_BOOTCOMMAND);
  654. break;
  655. #endif
  656. default:
  657. #ifdef QSPI_NOR_BOOTCOMMAND
  658. sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
  659. #endif
  660. break;
  661. }
  662. ret = env_set("bootcmd", bootcmd_str);
  663. if (ret) {
  664. printf("Failed to set bootcmd: ret = %d\n", ret);
  665. return ret;
  666. }
  667. return 0;
  668. }
  669. int fsl_setenv_mcinitcmd(void)
  670. {
  671. int ret = 0;
  672. enum boot_src src = get_boot_src();
  673. switch (src) {
  674. #ifdef IFC_MC_INIT_CMD
  675. case BOOT_SOURCE_IFC_NAND:
  676. case BOOT_SOURCE_IFC_NOR:
  677. ret = env_set("mcinitcmd", IFC_MC_INIT_CMD);
  678. break;
  679. #endif
  680. #ifdef QSPI_MC_INIT_CMD
  681. case BOOT_SOURCE_QSPI_NAND:
  682. case BOOT_SOURCE_QSPI_NOR:
  683. ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
  684. break;
  685. #endif
  686. #ifdef XSPI_MC_INIT_CMD
  687. case BOOT_SOURCE_XSPI_NAND:
  688. case BOOT_SOURCE_XSPI_NOR:
  689. ret = env_set("mcinitcmd", XSPI_MC_INIT_CMD);
  690. break;
  691. #endif
  692. #ifdef SD_MC_INIT_CMD
  693. case BOOT_SOURCE_SD_MMC:
  694. ret = env_set("mcinitcmd", SD_MC_INIT_CMD);
  695. break;
  696. #endif
  697. #ifdef SD2_MC_INIT_CMD
  698. case BOOT_SOURCE_SD_MMC2:
  699. ret = env_set("mcinitcmd", SD2_MC_INIT_CMD);
  700. break;
  701. #endif
  702. default:
  703. #ifdef QSPI_MC_INIT_CMD
  704. ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
  705. #endif
  706. break;
  707. }
  708. if (ret) {
  709. printf("Failed to set mcinitcmd: ret = %d\n", ret);
  710. return ret;
  711. }
  712. return 0;
  713. }
  714. #endif
  715. #ifdef CONFIG_BOARD_LATE_INIT
  716. int board_late_init(void)
  717. {
  718. #ifdef CONFIG_CHAIN_OF_TRUST
  719. fsl_setenv_chain_of_trust();
  720. #endif
  721. #ifdef CONFIG_TFABOOT
  722. /*
  723. * check if gd->env_addr is default_environment; then setenv bootcmd
  724. * and mcinitcmd.
  725. */
  726. #if !defined(CONFIG_ENV_ADDR) || defined(ENV_IS_EMBEDDED)
  727. if (gd->env_addr == (ulong)&default_environment[0]) {
  728. #else
  729. if (gd->env_addr + gd->reloc_off == (ulong)&default_environment[0]) {
  730. #endif
  731. fsl_setenv_bootcmd();
  732. fsl_setenv_mcinitcmd();
  733. }
  734. /*
  735. * If the boot mode is secure, default environment is not present then
  736. * setenv command needs to be run by default
  737. */
  738. #ifdef CONFIG_CHAIN_OF_TRUST
  739. if ((fsl_check_boot_mode_secure() == 1)) {
  740. fsl_setenv_bootcmd();
  741. fsl_setenv_mcinitcmd();
  742. }
  743. #endif
  744. #endif
  745. #ifdef CONFIG_QSPI_AHB_INIT
  746. qspi_ahb_init();
  747. #endif
  748. return 0;
  749. }
  750. #endif