generic.c 8.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2013 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <asm/io.h>
  7. #include <asm/arch/imx-regs.h>
  8. #include <asm/arch/clock.h>
  9. #include <asm/arch/crm_regs.h>
  10. #include <asm/mach-imx/sys_proto.h>
  11. #include <env.h>
  12. #include <netdev.h>
  13. #ifdef CONFIG_FSL_ESDHC_IMX
  14. #include <fsl_esdhc_imx.h>
  15. #endif
  16. #ifdef CONFIG_FSL_ESDHC_IMX
  17. DECLARE_GLOBAL_DATA_PTR;
  18. #endif
  19. static char soc_type[] = "xx0";
  20. #ifdef CONFIG_MXC_OCOTP
  21. void enable_ocotp_clk(unsigned char enable)
  22. {
  23. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  24. u32 reg;
  25. reg = readl(&ccm->ccgr6);
  26. if (enable)
  27. reg |= CCM_CCGR6_OCOTP_CTRL_MASK;
  28. else
  29. reg &= ~CCM_CCGR6_OCOTP_CTRL_MASK;
  30. writel(reg, &ccm->ccgr6);
  31. }
  32. #endif
  33. static u32 get_mcu_main_clk(void)
  34. {
  35. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  36. u32 ccm_ccsr, ccm_cacrr, armclk_div;
  37. u32 sysclk_sel, pll_pfd_sel = 0;
  38. u32 freq = 0;
  39. ccm_ccsr = readl(&ccm->ccsr);
  40. sysclk_sel = ccm_ccsr & CCM_CCSR_SYS_CLK_SEL_MASK;
  41. sysclk_sel >>= CCM_CCSR_SYS_CLK_SEL_OFFSET;
  42. ccm_cacrr = readl(&ccm->cacrr);
  43. armclk_div = ccm_cacrr & CCM_CACRR_ARM_CLK_DIV_MASK;
  44. armclk_div >>= CCM_CACRR_ARM_CLK_DIV_OFFSET;
  45. armclk_div += 1;
  46. switch (sysclk_sel) {
  47. case 0:
  48. freq = FASE_CLK_FREQ;
  49. break;
  50. case 1:
  51. freq = SLOW_CLK_FREQ;
  52. break;
  53. case 2:
  54. pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL2_PFD_CLK_SEL_MASK;
  55. pll_pfd_sel >>= CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET;
  56. if (pll_pfd_sel == 0)
  57. freq = PLL2_MAIN_FREQ;
  58. else if (pll_pfd_sel == 1)
  59. freq = PLL2_PFD1_FREQ;
  60. else if (pll_pfd_sel == 2)
  61. freq = PLL2_PFD2_FREQ;
  62. else if (pll_pfd_sel == 3)
  63. freq = PLL2_PFD3_FREQ;
  64. else if (pll_pfd_sel == 4)
  65. freq = PLL2_PFD4_FREQ;
  66. break;
  67. case 3:
  68. freq = PLL2_MAIN_FREQ;
  69. break;
  70. case 4:
  71. pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL1_PFD_CLK_SEL_MASK;
  72. pll_pfd_sel >>= CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET;
  73. if (pll_pfd_sel == 0)
  74. freq = PLL1_MAIN_FREQ;
  75. else if (pll_pfd_sel == 1)
  76. freq = PLL1_PFD1_FREQ;
  77. else if (pll_pfd_sel == 2)
  78. freq = PLL1_PFD2_FREQ;
  79. else if (pll_pfd_sel == 3)
  80. freq = PLL1_PFD3_FREQ;
  81. else if (pll_pfd_sel == 4)
  82. freq = PLL1_PFD4_FREQ;
  83. break;
  84. case 5:
  85. freq = PLL3_MAIN_FREQ;
  86. break;
  87. default:
  88. printf("unsupported system clock select\n");
  89. }
  90. return freq / armclk_div;
  91. }
  92. static u32 get_bus_clk(void)
  93. {
  94. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  95. u32 ccm_cacrr, busclk_div;
  96. ccm_cacrr = readl(&ccm->cacrr);
  97. busclk_div = ccm_cacrr & CCM_CACRR_BUS_CLK_DIV_MASK;
  98. busclk_div >>= CCM_CACRR_BUS_CLK_DIV_OFFSET;
  99. busclk_div += 1;
  100. return get_mcu_main_clk() / busclk_div;
  101. }
  102. static u32 get_ipg_clk(void)
  103. {
  104. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  105. u32 ccm_cacrr, ipgclk_div;
  106. ccm_cacrr = readl(&ccm->cacrr);
  107. ipgclk_div = ccm_cacrr & CCM_CACRR_IPG_CLK_DIV_MASK;
  108. ipgclk_div >>= CCM_CACRR_IPG_CLK_DIV_OFFSET;
  109. ipgclk_div += 1;
  110. return get_bus_clk() / ipgclk_div;
  111. }
  112. static u32 get_uart_clk(void)
  113. {
  114. return get_ipg_clk();
  115. }
  116. static u32 get_sdhc_clk(void)
  117. {
  118. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  119. u32 ccm_cscmr1, ccm_cscdr2, sdhc_clk_sel, sdhc_clk_div;
  120. u32 freq = 0;
  121. ccm_cscmr1 = readl(&ccm->cscmr1);
  122. sdhc_clk_sel = ccm_cscmr1 & CCM_CSCMR1_ESDHC1_CLK_SEL_MASK;
  123. sdhc_clk_sel >>= CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET;
  124. ccm_cscdr2 = readl(&ccm->cscdr2);
  125. sdhc_clk_div = ccm_cscdr2 & CCM_CSCDR2_ESDHC1_CLK_DIV_MASK;
  126. sdhc_clk_div >>= CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET;
  127. sdhc_clk_div += 1;
  128. switch (sdhc_clk_sel) {
  129. case 0:
  130. freq = PLL3_MAIN_FREQ;
  131. break;
  132. case 1:
  133. freq = PLL3_PFD3_FREQ;
  134. break;
  135. case 2:
  136. freq = PLL1_PFD3_FREQ;
  137. break;
  138. case 3:
  139. freq = get_bus_clk();
  140. break;
  141. }
  142. return freq / sdhc_clk_div;
  143. }
  144. u32 get_fec_clk(void)
  145. {
  146. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  147. u32 ccm_cscmr2, rmii_clk_sel;
  148. u32 freq = 0;
  149. ccm_cscmr2 = readl(&ccm->cscmr2);
  150. rmii_clk_sel = ccm_cscmr2 & CCM_CSCMR2_RMII_CLK_SEL_MASK;
  151. rmii_clk_sel >>= CCM_CSCMR2_RMII_CLK_SEL_OFFSET;
  152. switch (rmii_clk_sel) {
  153. case 0:
  154. freq = ENET_EXTERNAL_CLK;
  155. break;
  156. case 1:
  157. freq = AUDIO_EXTERNAL_CLK;
  158. break;
  159. case 2:
  160. freq = PLL5_MAIN_FREQ;
  161. break;
  162. case 3:
  163. freq = PLL5_MAIN_FREQ / 2;
  164. break;
  165. }
  166. return freq;
  167. }
  168. static u32 get_i2c_clk(void)
  169. {
  170. return get_ipg_clk();
  171. }
  172. static u32 get_dspi_clk(void)
  173. {
  174. return get_ipg_clk();
  175. }
  176. u32 get_lpuart_clk(void)
  177. {
  178. return get_uart_clk();
  179. }
  180. unsigned int mxc_get_clock(enum mxc_clock clk)
  181. {
  182. switch (clk) {
  183. case MXC_ARM_CLK:
  184. return get_mcu_main_clk();
  185. case MXC_BUS_CLK:
  186. return get_bus_clk();
  187. case MXC_IPG_CLK:
  188. return get_ipg_clk();
  189. case MXC_UART_CLK:
  190. return get_uart_clk();
  191. case MXC_ESDHC_CLK:
  192. return get_sdhc_clk();
  193. case MXC_FEC_CLK:
  194. return get_fec_clk();
  195. case MXC_I2C_CLK:
  196. return get_i2c_clk();
  197. case MXC_DSPI_CLK:
  198. return get_dspi_clk();
  199. default:
  200. break;
  201. }
  202. return -1;
  203. }
  204. /* Dump some core clocks */
  205. int do_vf610_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
  206. char * const argv[])
  207. {
  208. printf("\n");
  209. printf("cpu clock : %8d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
  210. printf("bus clock : %8d MHz\n", mxc_get_clock(MXC_BUS_CLK) / 1000000);
  211. printf("ipg clock : %8d MHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000000);
  212. return 0;
  213. }
  214. U_BOOT_CMD(
  215. clocks, CONFIG_SYS_MAXARGS, 1, do_vf610_showclocks,
  216. "display clocks",
  217. ""
  218. );
  219. #ifdef CONFIG_FEC_MXC
  220. __weak void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
  221. {
  222. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  223. struct fuse_bank *bank = &ocotp->bank[4];
  224. struct fuse_bank4_regs *fuse =
  225. (struct fuse_bank4_regs *)bank->fuse_regs;
  226. u32 value = readl(&fuse->mac_addr0);
  227. mac[0] = (value >> 8);
  228. mac[1] = value;
  229. value = readl(&fuse->mac_addr1);
  230. mac[2] = value >> 24;
  231. mac[3] = value >> 16;
  232. mac[4] = value >> 8;
  233. mac[5] = value;
  234. }
  235. #endif
  236. u32 get_cpu_rev(void)
  237. {
  238. return MXC_CPU_VF610 << 12;
  239. }
  240. #if defined(CONFIG_DISPLAY_CPUINFO)
  241. static char *get_reset_cause(void)
  242. {
  243. u32 cause;
  244. struct src *src_regs = (struct src *)SRC_BASE_ADDR;
  245. cause = readl(&src_regs->srsr);
  246. writel(cause, &src_regs->srsr);
  247. if (cause & SRC_SRSR_POR_RST)
  248. return "POWER ON RESET";
  249. else if (cause & SRC_SRSR_WDOG_A5)
  250. return "WDOG A5";
  251. else if (cause & SRC_SRSR_WDOG_M4)
  252. return "WDOG M4";
  253. else if (cause & SRC_SRSR_JTAG_RST)
  254. return "JTAG HIGH-Z";
  255. else if (cause & SRC_SRSR_SW_RST)
  256. return "SW RESET";
  257. else if (cause & SRC_SRSR_RESETB)
  258. return "EXTERNAL RESET";
  259. else
  260. return "unknown reset";
  261. }
  262. int print_cpuinfo(void)
  263. {
  264. printf("CPU: Freescale Vybrid VF%s at %d MHz\n",
  265. soc_type, mxc_get_clock(MXC_ARM_CLK) / 1000000);
  266. printf("Reset cause: %s\n", get_reset_cause());
  267. return 0;
  268. }
  269. #endif
  270. int arch_cpu_init(void)
  271. {
  272. struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR;
  273. soc_type[0] = mscm->cpxcount ? '6' : '5'; /*Dual Core => VF6x0 */
  274. soc_type[1] = mscm->cpxcfg1 ? '1' : '0'; /* L2 Cache => VFx10 */
  275. return 0;
  276. }
  277. #ifdef CONFIG_ARCH_MISC_INIT
  278. int arch_misc_init(void)
  279. {
  280. char soc[6];
  281. strcpy(soc, "vf");
  282. strcat(soc, soc_type);
  283. env_set("soc", soc);
  284. return 0;
  285. }
  286. #endif
  287. int cpu_eth_init(bd_t *bis)
  288. {
  289. int rc = -ENODEV;
  290. #if defined(CONFIG_FEC_MXC)
  291. rc = fecmxc_initialize(bis);
  292. #endif
  293. return rc;
  294. }
  295. #ifdef CONFIG_FSL_ESDHC_IMX
  296. int cpu_mmc_init(bd_t *bis)
  297. {
  298. return fsl_esdhc_mmc_init(bis);
  299. }
  300. #endif
  301. int get_clocks(void)
  302. {
  303. #ifdef CONFIG_FSL_ESDHC_IMX
  304. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  305. #endif
  306. return 0;
  307. }
  308. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  309. void enable_caches(void)
  310. {
  311. #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
  312. enum dcache_option option = DCACHE_WRITETHROUGH;
  313. #else
  314. enum dcache_option option = DCACHE_WRITEBACK;
  315. #endif
  316. dcache_enable();
  317. icache_enable();
  318. /* Enable caching on OCRAM */
  319. mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR, IRAM_SIZE, option);
  320. }
  321. #endif
  322. #ifdef CONFIG_SYS_I2C_MXC
  323. /* i2c_num can be from 0 - 3 */
  324. int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
  325. {
  326. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  327. switch (i2c_num) {
  328. case 0:
  329. clrsetbits_le32(&ccm->ccgr4, CCM_CCGR4_I2C0_CTRL_MASK,
  330. CCM_CCGR4_I2C0_CTRL_MASK);
  331. case 2:
  332. clrsetbits_le32(&ccm->ccgr10, CCM_CCGR10_I2C2_CTRL_MASK,
  333. CCM_CCGR10_I2C2_CTRL_MASK);
  334. break;
  335. default:
  336. return -EINVAL;
  337. }
  338. return 0;
  339. }
  340. #endif