spl.c 4.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2016 Google, Inc
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <debug_uart.h>
  8. #include <dm.h>
  9. #include <malloc.h>
  10. #include <spl.h>
  11. #include <syscon.h>
  12. #include <asm/cpu.h>
  13. #include <asm/cpu_common.h>
  14. #include <asm/mrccache.h>
  15. #include <asm/mtrr.h>
  16. #include <asm/pci.h>
  17. #include <asm/processor.h>
  18. #include <asm/spl.h>
  19. #include <asm-generic/sections.h>
  20. DECLARE_GLOBAL_DATA_PTR;
  21. __weak int arch_cpu_init_dm(void)
  22. {
  23. return 0;
  24. }
  25. #ifdef CONFIG_TPL
  26. static int set_max_freq(void)
  27. {
  28. if (cpu_get_burst_mode_state() == BURST_MODE_UNAVAILABLE) {
  29. /*
  30. * Burst Mode has been factory-configured as disabled and is not
  31. * available in this physical processor package
  32. */
  33. debug("Burst Mode is factory-disabled\n");
  34. return -ENOENT;
  35. }
  36. /* Enable burst mode */
  37. cpu_set_burst_mode(true);
  38. /* Enable speed step */
  39. cpu_set_eist(true);
  40. /* Set P-State ratio */
  41. cpu_set_p_state_to_turbo_ratio();
  42. return 0;
  43. }
  44. #endif
  45. static int x86_spl_init(void)
  46. {
  47. #ifndef CONFIG_TPL
  48. /*
  49. * TODO(sjg@chromium.org): We use this area of RAM for the stack
  50. * and global_data in SPL. Once U-Boot starts up and releocates it
  51. * is not needed. We could make this a CONFIG option or perhaps
  52. * place it immediately below CONFIG_SYS_TEXT_BASE.
  53. */
  54. char *ptr = (char *)0x110000;
  55. #else
  56. struct udevice *punit;
  57. #endif
  58. int ret;
  59. debug("%s starting\n", __func__);
  60. if (IS_ENABLED(TPL))
  61. ret = x86_cpu_reinit_f();
  62. else
  63. ret = x86_cpu_init_f();
  64. ret = spl_init();
  65. if (ret) {
  66. debug("%s: spl_init() failed\n", __func__);
  67. return ret;
  68. }
  69. ret = arch_cpu_init();
  70. if (ret) {
  71. debug("%s: arch_cpu_init() failed\n", __func__);
  72. return ret;
  73. }
  74. #ifndef CONFIG_TPL
  75. ret = arch_cpu_init_dm();
  76. if (ret) {
  77. debug("%s: arch_cpu_init_dm() failed\n", __func__);
  78. return ret;
  79. }
  80. #endif
  81. preloader_console_init();
  82. #ifndef CONFIG_TPL
  83. ret = print_cpuinfo();
  84. if (ret) {
  85. debug("%s: print_cpuinfo() failed\n", __func__);
  86. return ret;
  87. }
  88. #endif
  89. ret = dram_init();
  90. if (ret) {
  91. debug("%s: dram_init() failed\n", __func__);
  92. return ret;
  93. }
  94. if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) {
  95. ret = mrccache_spl_save();
  96. if (ret)
  97. debug("%s: Failed to write to mrccache (err=%d)\n",
  98. __func__, ret);
  99. }
  100. #ifndef CONFIG_TPL
  101. memset(&__bss_start, 0, (ulong)&__bss_end - (ulong)&__bss_start);
  102. /* TODO(sjg@chromium.org): Consider calling cpu_init_r() here */
  103. ret = interrupt_init();
  104. if (ret) {
  105. debug("%s: interrupt_init() failed\n", __func__);
  106. return ret;
  107. }
  108. /*
  109. * The stack grows down from ptr. Put the global data at ptr. This
  110. * will only be used for SPL. Once SPL loads U-Boot proper it will
  111. * set up its own stack.
  112. */
  113. gd->new_gd = (struct global_data *)ptr;
  114. memcpy(gd->new_gd, gd, sizeof(*gd));
  115. arch_setup_gd(gd->new_gd);
  116. gd->start_addr_sp = (ulong)ptr;
  117. /* Cache the SPI flash. Otherwise copying the code to RAM takes ages */
  118. ret = mtrr_add_request(MTRR_TYPE_WRBACK,
  119. (1ULL << 32) - CONFIG_XIP_ROM_SIZE,
  120. CONFIG_XIP_ROM_SIZE);
  121. if (ret) {
  122. debug("%s: SPI cache setup failed (err=%d)\n", __func__, ret);
  123. return ret;
  124. }
  125. mtrr_commit(true);
  126. #else
  127. ret = syscon_get_by_driver_data(X86_SYSCON_PUNIT, &punit);
  128. if (ret)
  129. debug("Could not find PUNIT (err=%d)\n", ret);
  130. ret = set_max_freq();
  131. if (ret)
  132. debug("Failed to set CPU frequency (err=%d)\n", ret);
  133. #endif
  134. return 0;
  135. }
  136. void board_init_f(ulong flags)
  137. {
  138. int ret;
  139. ret = x86_spl_init();
  140. if (ret) {
  141. debug("Error %d\n", ret);
  142. panic("x86_spl_init fail");
  143. }
  144. #ifdef CONFIG_TPL
  145. gd->bd = malloc(sizeof(*gd->bd));
  146. if (!gd->bd) {
  147. printf("Out of memory for bd_info size %x\n", sizeof(*gd->bd));
  148. hang();
  149. }
  150. board_init_r(gd, 0);
  151. #else
  152. /* Uninit CAR and jump to board_init_f_r() */
  153. board_init_f_r_trampoline(gd->start_addr_sp);
  154. #endif
  155. }
  156. void board_init_f_r(void)
  157. {
  158. init_cache_f_r();
  159. gd->flags &= ~GD_FLG_SERIAL_READY;
  160. debug("cache status %d\n", dcache_status());
  161. board_init_r(gd, 0);
  162. }
  163. u32 spl_boot_device(void)
  164. {
  165. return BOOT_DEVICE_SPI_MMAP;
  166. }
  167. int spl_start_uboot(void)
  168. {
  169. return 0;
  170. }
  171. void spl_board_announce_boot_device(void)
  172. {
  173. printf("SPI flash");
  174. }
  175. static int spl_board_load_image(struct spl_image_info *spl_image,
  176. struct spl_boot_device *bootdev)
  177. {
  178. spl_image->size = CONFIG_SYS_MONITOR_LEN;
  179. spl_image->entry_point = CONFIG_SYS_TEXT_BASE;
  180. spl_image->load_addr = CONFIG_SYS_TEXT_BASE;
  181. spl_image->os = IH_OS_U_BOOT;
  182. spl_image->name = "U-Boot";
  183. debug("Loading to %lx\n", spl_image->load_addr);
  184. return 0;
  185. }
  186. SPL_LOAD_IMAGE_METHOD("SPI", 5, BOOT_DEVICE_SPI_MMAP, spl_board_load_image);
  187. int spl_spi_load_image(void)
  188. {
  189. return -EPERM;
  190. }
  191. #ifdef CONFIG_X86_RUN_64BIT
  192. void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
  193. {
  194. int ret;
  195. printf("Jumping to 64-bit U-Boot: Note many features are missing\n");
  196. ret = cpu_jump_to_64bit_uboot(spl_image->entry_point);
  197. debug("ret=%d\n", ret);
  198. hang();
  199. }
  200. #endif
  201. void spl_board_init(void)
  202. {
  203. #ifndef CONFIG_TPL
  204. preloader_console_init();
  205. #endif
  206. }