cache.c 4.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2003
  4. * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <asm/cacheops.h>
  9. #ifdef CONFIG_MIPS_L2_CACHE
  10. #include <asm/cm.h>
  11. #endif
  12. #include <asm/io.h>
  13. #include <asm/mipsregs.h>
  14. #include <asm/system.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. static void probe_l2(void)
  17. {
  18. #ifdef CONFIG_MIPS_L2_CACHE
  19. unsigned long conf2, sl;
  20. bool l2c = false;
  21. if (!(read_c0_config1() & MIPS_CONF_M))
  22. return;
  23. conf2 = read_c0_config2();
  24. if (__mips_isa_rev >= 6) {
  25. l2c = conf2 & MIPS_CONF_M;
  26. if (l2c)
  27. l2c = read_c0_config3() & MIPS_CONF_M;
  28. if (l2c)
  29. l2c = read_c0_config4() & MIPS_CONF_M;
  30. if (l2c)
  31. l2c = read_c0_config5() & MIPS_CONF5_L2C;
  32. }
  33. if (l2c && config_enabled(CONFIG_MIPS_CM)) {
  34. gd->arch.l2_line_size = mips_cm_l2_line_size();
  35. } else if (l2c) {
  36. /* We don't know how to retrieve L2 config on this system */
  37. BUG();
  38. } else {
  39. sl = (conf2 & MIPS_CONF2_SL) >> MIPS_CONF2_SL_SHF;
  40. gd->arch.l2_line_size = sl ? (2 << sl) : 0;
  41. }
  42. #endif
  43. }
  44. void mips_cache_probe(void)
  45. {
  46. #ifdef CONFIG_SYS_CACHE_SIZE_AUTO
  47. unsigned long conf1, il, dl;
  48. conf1 = read_c0_config1();
  49. il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF;
  50. dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF;
  51. gd->arch.l1i_line_size = il ? (2 << il) : 0;
  52. gd->arch.l1d_line_size = dl ? (2 << dl) : 0;
  53. #endif
  54. probe_l2();
  55. }
  56. static inline unsigned long icache_line_size(void)
  57. {
  58. #ifdef CONFIG_SYS_CACHE_SIZE_AUTO
  59. return gd->arch.l1i_line_size;
  60. #else
  61. return CONFIG_SYS_ICACHE_LINE_SIZE;
  62. #endif
  63. }
  64. static inline unsigned long dcache_line_size(void)
  65. {
  66. #ifdef CONFIG_SYS_CACHE_SIZE_AUTO
  67. return gd->arch.l1d_line_size;
  68. #else
  69. return CONFIG_SYS_DCACHE_LINE_SIZE;
  70. #endif
  71. }
  72. static inline unsigned long scache_line_size(void)
  73. {
  74. #ifdef CONFIG_MIPS_L2_CACHE
  75. return gd->arch.l2_line_size;
  76. #else
  77. return CONFIG_SYS_SCACHE_LINE_SIZE;
  78. #endif
  79. }
  80. #define cache_loop(start, end, lsize, ops...) do { \
  81. const void *addr = (const void *)(start & ~(lsize - 1)); \
  82. const void *aend = (const void *)((end - 1) & ~(lsize - 1)); \
  83. const unsigned int cache_ops[] = { ops }; \
  84. unsigned int i; \
  85. \
  86. if (!lsize) \
  87. break; \
  88. \
  89. for (; addr <= aend; addr += lsize) { \
  90. for (i = 0; i < ARRAY_SIZE(cache_ops); i++) \
  91. mips_cache(cache_ops[i], addr); \
  92. } \
  93. } while (0)
  94. void flush_cache(ulong start_addr, ulong size)
  95. {
  96. unsigned long ilsize = icache_line_size();
  97. unsigned long dlsize = dcache_line_size();
  98. unsigned long slsize = scache_line_size();
  99. /* aend will be miscalculated when size is zero, so we return here */
  100. if (size == 0)
  101. return;
  102. if ((ilsize == dlsize) && !slsize) {
  103. /* flush I-cache & D-cache simultaneously */
  104. cache_loop(start_addr, start_addr + size, ilsize,
  105. HIT_WRITEBACK_INV_D, HIT_INVALIDATE_I);
  106. goto ops_done;
  107. }
  108. /* flush D-cache */
  109. cache_loop(start_addr, start_addr + size, dlsize, HIT_WRITEBACK_INV_D);
  110. /* flush L2 cache */
  111. cache_loop(start_addr, start_addr + size, slsize, HIT_WRITEBACK_INV_SD);
  112. /* flush I-cache */
  113. cache_loop(start_addr, start_addr + size, ilsize, HIT_INVALIDATE_I);
  114. ops_done:
  115. /* ensure cache ops complete before any further memory accesses */
  116. sync();
  117. /* ensure the pipeline doesn't contain now-invalid instructions */
  118. instruction_hazard_barrier();
  119. }
  120. void flush_dcache_range(ulong start_addr, ulong stop)
  121. {
  122. unsigned long lsize = dcache_line_size();
  123. unsigned long slsize = scache_line_size();
  124. /* aend will be miscalculated when size is zero, so we return here */
  125. if (start_addr == stop)
  126. return;
  127. cache_loop(start_addr, stop, lsize, HIT_WRITEBACK_INV_D);
  128. /* flush L2 cache */
  129. cache_loop(start_addr, stop, slsize, HIT_WRITEBACK_INV_SD);
  130. /* ensure cache ops complete before any further memory accesses */
  131. sync();
  132. }
  133. void invalidate_dcache_range(ulong start_addr, ulong stop)
  134. {
  135. unsigned long lsize = dcache_line_size();
  136. unsigned long slsize = scache_line_size();
  137. /* aend will be miscalculated when size is zero, so we return here */
  138. if (start_addr == stop)
  139. return;
  140. /* invalidate L2 cache */
  141. cache_loop(start_addr, stop, slsize, HIT_INVALIDATE_SD);
  142. cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D);
  143. /* ensure cache ops complete before any further memory accesses */
  144. sync();
  145. }
  146. int dcache_status(void)
  147. {
  148. unsigned int cca = read_c0_config() & CONF_CM_CMASK;
  149. return cca != CONF_CM_UNCACHED;
  150. }
  151. void dcache_enable(void)
  152. {
  153. puts("Not supported!\n");
  154. }
  155. void dcache_disable(void)
  156. {
  157. /* change CCA to uncached */
  158. change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
  159. /* ensure the pipeline doesn't contain now-invalid instructions */
  160. instruction_hazard_barrier();
  161. }