cpu_init.c 4.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
  4. *
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <watchdog.h>
  9. #include <asm/immap.h>
  10. #include <asm/io.h>
  11. #if defined(CONFIG_M5307)
  12. /*
  13. * Simple mcf5307 chip select module init.
  14. *
  15. * Note: this chip has an issue reported in the device "errata":
  16. * MCF5307ER Rev 4.2 reports @ section 35:
  17. * Corrupted Return PC in Exception Stack Frame
  18. * When processing an autovectored interrupt an error can occur that
  19. * causes 0xFFFFFFFF to be written as the return PC value in the
  20. * exception stack frame. The problem is caused by a conflict between
  21. * an internal autovector access and a chip select mapped to the IACK
  22. * address space (0xFFFFXXXX).
  23. * Workaround:
  24. * Set the C/I bit in the chip select mask register (CSMR) for the
  25. * chip select that is mapped to 0xFFFFXXXX.
  26. * This will prevent the chip select from asserting for IACK accesses.
  27. */
  28. #define MCF5307_SP_ERR_FIX(cs_base, mask) \
  29. do { \
  30. if (((cs_base<<16)+(in_be32(&mask)&0xffff0000)) >= \
  31. 0xffff0000) \
  32. setbits_be32(&mask, CSMR_CI); \
  33. } while (0)
  34. void init_csm(void)
  35. {
  36. csm_t *csm = (csm_t *)(MMAP_CSM);
  37. #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && \
  38. defined(CONFIG_SYS_CS0_CTRL))
  39. out_be16(&csm->csar0, CONFIG_SYS_CS0_BASE);
  40. out_be32(&csm->csmr0, CONFIG_SYS_CS0_MASK);
  41. out_be16(&csm->cscr0, CONFIG_SYS_CS0_CTRL);
  42. MCF5307_SP_ERR_FIX(CONFIG_SYS_CS0_BASE, csm->csmr0);
  43. #else
  44. #warning "Chip Select 0 are not initialized/used"
  45. #endif
  46. #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && \
  47. defined(CONFIG_SYS_CS1_CTRL))
  48. out_be16(&csm->csar1, CONFIG_SYS_CS1_BASE);
  49. out_be32(&csm->csmr1, CONFIG_SYS_CS1_MASK);
  50. out_be16(&csm->cscr1, CONFIG_SYS_CS1_CTRL);
  51. MCF5307_SP_ERR_FIX(CONFIG_SYS_CS1_BASE, csm->csmr1);
  52. #endif
  53. #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && \
  54. defined(CONFIG_SYS_CS2_CTRL))
  55. out_be16(&csm->csar2, CONFIG_SYS_CS2_BASE);
  56. out_be32(&csm->csmr2, CONFIG_SYS_CS2_MASK);
  57. out_be16(&csm->cscr2, CONFIG_SYS_CS2_CTRL);
  58. MCF5307_SP_ERR_FIX(CONFIG_SYS_CS2_BASE, csm->csmr2);
  59. #endif
  60. #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && \
  61. defined(CONFIG_SYS_CS3_CTRL))
  62. out_be16(&csm->csar3, CONFIG_SYS_CS3_BASE);
  63. out_be32(&csm->csmr3, CONFIG_SYS_CS3_MASK);
  64. out_be16(&csm->cscr3, CONFIG_SYS_CS3_CTRL);
  65. MCF5307_SP_ERR_FIX(CONFIG_SYS_CS3_BASE, csm->csmr3);
  66. #endif
  67. #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && \
  68. defined(CONFIG_SYS_CS4_CTRL))
  69. out_be16(&csm->csar4, CONFIG_SYS_CS4_BASE);
  70. out_be32(&csm->csmr4, CONFIG_SYS_CS4_MASK);
  71. out_be16(&csm->cscr4, CONFIG_SYS_CS4_CTRL);
  72. MCF5307_SP_ERR_FIX(CONFIG_SYS_CS4_BASE, csm->csmr4);
  73. #endif
  74. #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && \
  75. defined(CONFIG_SYS_CS5_CTRL))
  76. out_be16(&csm->csar5, CONFIG_SYS_CS5_BASE);
  77. out_be32(&csm->csmr5, CONFIG_SYS_CS5_MASK);
  78. out_be16(&csm->cscr5, CONFIG_SYS_CS5_CTRL);
  79. MCF5307_SP_ERR_FIX(CONFIG_SYS_CS5_BASE, csm->csmr5);
  80. #endif
  81. #if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && \
  82. defined(CONFIG_SYS_CS6_CTRL))
  83. out_be16(&csm->csar6, CONFIG_SYS_CS6_BASE);
  84. out_be32(&csm->csmr6, CONFIG_SYS_CS6_MASK);
  85. out_be16(&csm->cscr6, CONFIG_SYS_CS6_CTRL);
  86. MCF5307_SP_ERR_FIX(CONFIG_SYS_CS6_BASE, csm->csmr6);
  87. #endif
  88. #if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && \
  89. defined(CONFIG_SYS_CS7_CTRL))
  90. out_be16(&csm->csar7, CONFIG_SYS_CS7_BASE);
  91. out_be32(&csm->csmr7, CONFIG_SYS_CS7_MASK);
  92. out_be16(&csm->cscr7, CONFIG_SYS_CS7_CTRL);
  93. MCF5307_SP_ERR_FIX(CONFIG_SYS_CS7_BASE, csm->csmr7);
  94. #endif
  95. }
  96. /*
  97. * Set up the memory map and initialize registers
  98. */
  99. void cpu_init_f(void)
  100. {
  101. sim_t *sim = (sim_t *)(MMAP_SIM);
  102. out_8(&sim->sypcr, 0x00);
  103. out_8(&sim->swivr, 0x0f);
  104. out_8(&sim->swsr, 0x00);
  105. out_8(&sim->mpark, 0x00);
  106. intctrl_t *icr = (intctrl_t *)(MMAP_INTC);
  107. /* timer 2 not masked */
  108. out_be32(&icr->imr, 0xfffffbff);
  109. out_8(&icr->icr0, 0x00); /* sw watchdog */
  110. out_8(&icr->icr1, 0x00); /* timer 1 */
  111. out_8(&icr->icr2, 0x88); /* timer 2 */
  112. out_8(&icr->icr3, 0x00); /* i2c */
  113. out_8(&icr->icr4, 0x00); /* uart 0 */
  114. out_8(&icr->icr5, 0x00); /* uart 1 */
  115. out_8(&icr->icr6, 0x00); /* dma 0 */
  116. out_8(&icr->icr7, 0x00); /* dma 1 */
  117. out_8(&icr->icr8, 0x00); /* dma 2 */
  118. out_8(&icr->icr9, 0x00); /* dma 3 */
  119. /* Chipselect Init */
  120. init_csm();
  121. /* enable data/instruction cache now */
  122. icache_enable();
  123. }
  124. /*
  125. * initialize higher level parts of CPU like timers
  126. */
  127. int cpu_init_r(void)
  128. {
  129. return 0;
  130. }
  131. void uart_port_conf(int port)
  132. {
  133. }
  134. void arch_preboot_os(void)
  135. {
  136. /*
  137. * OS can change interrupt offsets and are about to boot the OS so
  138. * we need to make sure we disable all async interrupts.
  139. */
  140. intctrl_t *icr = (intctrl_t *)(MMAP_INTC);
  141. out_8(&icr->icr1, 0x00); /* timer 1 */
  142. out_8(&icr->icr2, 0x00); /* timer 2 */
  143. }
  144. #endif