cpu_init.c 3.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. *
  4. * (C) Copyright 2000-2003
  5. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  6. *
  7. * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc.
  8. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  9. */
  10. #include <common.h>
  11. #include <cpu_func.h>
  12. #include <watchdog.h>
  13. #include <asm/immap.h>
  14. #include <asm/io.h>
  15. #include <asm/rtc.h>
  16. #include <linux/compiler.h>
  17. void cfspi_port_conf(void)
  18. {
  19. gpio_t *gpio = (gpio_t *)MMAP_GPIO;
  20. out_8(&gpio->par_dspi,
  21. GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
  22. GPIO_PAR_DSPI_SCK_SCK);
  23. }
  24. /*
  25. * Breath some life into the CPU...
  26. *
  27. * Set up the memory map,
  28. * initialize a bunch of registers,
  29. * initialize the UPM's
  30. */
  31. void cpu_init_f(void)
  32. {
  33. gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  34. fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS;
  35. #if !defined(CONFIG_CF_SBF)
  36. scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
  37. pll_t *pll = (pll_t *)MMAP_PLL;
  38. /* Workaround, must place before fbcs */
  39. out_be32(&pll->psr, 0x12);
  40. out_be32(&scm1->mpr, 0x77777777);
  41. out_be32(&scm1->pacra, 0);
  42. out_be32(&scm1->pacrb, 0);
  43. out_be32(&scm1->pacrc, 0);
  44. out_be32(&scm1->pacrd, 0);
  45. out_be32(&scm1->pacre, 0);
  46. out_be32(&scm1->pacrf, 0);
  47. out_be32(&scm1->pacrg, 0);
  48. out_be32(&scm1->pacri, 0);
  49. #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
  50. && defined(CONFIG_SYS_CS0_CTRL))
  51. out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
  52. out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
  53. out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
  54. #endif
  55. #endif /* CONFIG_CF_SBF */
  56. #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
  57. && defined(CONFIG_SYS_CS1_CTRL))
  58. out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
  59. out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
  60. out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
  61. #endif
  62. #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
  63. && defined(CONFIG_SYS_CS2_CTRL))
  64. out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
  65. out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
  66. out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
  67. #endif
  68. #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
  69. && defined(CONFIG_SYS_CS3_CTRL))
  70. out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
  71. out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
  72. out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
  73. #endif
  74. #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
  75. && defined(CONFIG_SYS_CS4_CTRL))
  76. out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
  77. out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
  78. out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
  79. #endif
  80. #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
  81. && defined(CONFIG_SYS_CS5_CTRL))
  82. out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
  83. out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
  84. out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
  85. #endif
  86. #ifdef CONFIG_SYS_I2C_FSL
  87. out_8(&gpio->par_i2c, GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA);
  88. #endif
  89. icache_enable();
  90. cfspi_port_conf();
  91. }
  92. /*
  93. * initialize higher level parts of CPU like timers
  94. */
  95. int cpu_init_r(void)
  96. {
  97. #ifdef CONFIG_MCFRTC
  98. rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
  99. rtcex_t *rtcex = (rtcex_t *)&rtc->extended;
  100. out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff);
  101. out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff);
  102. #endif
  103. return (0);
  104. }
  105. void uart_port_conf(int port)
  106. {
  107. gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  108. /* Setup Ports: */
  109. switch (port) {
  110. case 0:
  111. clrbits_be16(&gpio->par_uart,
  112. ~(GPIO_PAR_UART_U0TXD_UNMASK & GPIO_PAR_UART_U0RXD_UNMASK));
  113. setbits_be16(&gpio->par_uart,
  114. GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
  115. break;
  116. case 1:
  117. clrbits_be16(&gpio->par_uart,
  118. ~(GPIO_PAR_UART_U1TXD_UNMASK & GPIO_PAR_UART_U1RXD_UNMASK));
  119. setbits_be16(&gpio->par_uart,
  120. GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
  121. break;
  122. case 2:
  123. clrbits_8(&gpio->par_dspi,
  124. ~(GPIO_PAR_DSPI_SIN_UNMASK & GPIO_PAR_DSPI_SOUT_UNMASK));
  125. out_8(&gpio->par_dspi,
  126. GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD);
  127. break;
  128. }
  129. }