board.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
  4. *
  5. * (C) Copyright 2007-2011
  6. * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  7. * Tom Cubie <tangliang@allwinnertech.com>
  8. *
  9. * Some init for sunxi platform.
  10. */
  11. #include <common.h>
  12. #include <cpu_func.h>
  13. #include <mmc.h>
  14. #include <i2c.h>
  15. #include <serial.h>
  16. #include <spl.h>
  17. #include <asm/gpio.h>
  18. #include <asm/io.h>
  19. #include <asm/arch/clock.h>
  20. #include <asm/arch/gpio.h>
  21. #include <asm/arch/spl.h>
  22. #include <asm/arch/sys_proto.h>
  23. #include <asm/arch/timer.h>
  24. #include <asm/arch/tzpc.h>
  25. #include <asm/arch/mmc.h>
  26. #include <linux/compiler.h>
  27. struct fel_stash {
  28. uint32_t sp;
  29. uint32_t lr;
  30. uint32_t cpsr;
  31. uint32_t sctlr;
  32. uint32_t vbar;
  33. uint32_t cr;
  34. };
  35. struct fel_stash fel_stash __attribute__((section(".data")));
  36. #ifdef CONFIG_ARM64
  37. #include <asm/armv8/mmu.h>
  38. static struct mm_region sunxi_mem_map[] = {
  39. {
  40. /* SRAM, MMIO regions */
  41. .virt = 0x0UL,
  42. .phys = 0x0UL,
  43. .size = 0x40000000UL,
  44. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  45. PTE_BLOCK_NON_SHARE
  46. }, {
  47. /* RAM */
  48. .virt = 0x40000000UL,
  49. .phys = 0x40000000UL,
  50. .size = 0xC0000000UL,
  51. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  52. PTE_BLOCK_INNER_SHARE
  53. }, {
  54. /* List terminator */
  55. 0,
  56. }
  57. };
  58. struct mm_region *mem_map = sunxi_mem_map;
  59. #endif
  60. static int gpio_init(void)
  61. {
  62. __maybe_unused uint val;
  63. #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
  64. #if defined(CONFIG_MACH_SUN4I) || \
  65. defined(CONFIG_MACH_SUN7I) || \
  66. defined(CONFIG_MACH_SUN8I_R40)
  67. /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
  68. sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
  69. sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
  70. #endif
  71. #if defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)
  72. sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
  73. sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
  74. #else
  75. sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
  76. sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
  77. #endif
  78. sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
  79. #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \
  80. defined(CONFIG_MACH_SUN7I) || \
  81. defined(CONFIG_MACH_SUN8I_R40))
  82. sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
  83. sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
  84. sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
  85. #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
  86. sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
  87. sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
  88. sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
  89. #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
  90. sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
  91. sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
  92. sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
  93. #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
  94. sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
  95. sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
  96. sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
  97. #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNXI_H3_H5)
  98. sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
  99. sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
  100. sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
  101. #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I)
  102. sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0);
  103. sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0);
  104. sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
  105. #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H6)
  106. sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H6_GPH_UART0);
  107. sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H6_GPH_UART0);
  108. sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP);
  109. #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
  110. sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
  111. sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
  112. sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
  113. #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S)
  114. sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0);
  115. sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0);
  116. sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
  117. #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
  118. sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
  119. sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
  120. sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
  121. #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
  122. sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
  123. sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
  124. sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
  125. #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
  126. sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
  127. sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
  128. sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
  129. #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
  130. sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
  131. sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
  132. sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
  133. #else
  134. #error Unsupported console port number. Please fix pin mux settings in board.c
  135. #endif
  136. #ifdef CONFIG_MACH_SUN50I_H6
  137. /* Update PIO power bias configuration by copy hardware detected value */
  138. val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
  139. writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
  140. val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
  141. writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
  142. #endif
  143. return 0;
  144. }
  145. #if defined(CONFIG_SPL_BOARD_LOAD_IMAGE) && defined(CONFIG_SPL_BUILD)
  146. static int spl_board_load_image(struct spl_image_info *spl_image,
  147. struct spl_boot_device *bootdev)
  148. {
  149. debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
  150. return_to_fel(fel_stash.sp, fel_stash.lr);
  151. return 0;
  152. }
  153. SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
  154. #endif
  155. void s_init(void)
  156. {
  157. /*
  158. * Undocumented magic taken from boot0, without this DRAM
  159. * access gets messed up (seems cache related).
  160. * The boot0 sources describe this as: "config ema for cache sram"
  161. */
  162. #if defined CONFIG_MACH_SUN6I
  163. setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
  164. #elif defined CONFIG_MACH_SUN8I
  165. __maybe_unused uint version;
  166. /* Unlock sram version info reg, read it, relock */
  167. setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
  168. version = readl(SUNXI_SRAMC_BASE + 0x24) >> 16;
  169. clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
  170. /*
  171. * Ideally this would be a switch case, but we do not know exactly
  172. * which versions there are and which version needs which settings,
  173. * so reproduce the per SoC code from the BSP.
  174. */
  175. #if defined CONFIG_MACH_SUN8I_A23
  176. if (version == 0x1650)
  177. setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
  178. else /* 0x1661 ? */
  179. setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
  180. #elif defined CONFIG_MACH_SUN8I_A33
  181. if (version != 0x1667)
  182. setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
  183. #endif
  184. /* A83T BSP never modifies SUNXI_SRAMC_BASE + 0x44 */
  185. /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
  186. #endif
  187. #if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64)
  188. /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
  189. asm volatile(
  190. "mrc p15, 0, r0, c1, c0, 1\n"
  191. "orr r0, r0, #1 << 6\n"
  192. "mcr p15, 0, r0, c1, c0, 1\n"
  193. ::: "r0");
  194. #endif
  195. #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
  196. /* Enable non-secure access to some peripherals */
  197. tzpc_init();
  198. #endif
  199. clock_init();
  200. timer_init();
  201. gpio_init();
  202. #ifndef CONFIG_DM_I2C
  203. i2c_init_board();
  204. #endif
  205. eth_init_board();
  206. }
  207. /* The sunxi internal brom will try to loader external bootloader
  208. * from mmc0, nand flash, mmc2.
  209. */
  210. uint32_t sunxi_get_boot_device(void)
  211. {
  212. int boot_source;
  213. /*
  214. * When booting from the SD card or NAND memory, the "eGON.BT0"
  215. * signature is expected to be found in memory at the address 0x0004
  216. * (see the "mksunxiboot" tool, which generates this header).
  217. *
  218. * When booting in the FEL mode over USB, this signature is patched in
  219. * memory and replaced with something else by the 'fel' tool. This other
  220. * signature is selected in such a way, that it can't be present in a
  221. * valid bootable SD card image (because the BROM would refuse to
  222. * execute the SPL in this case).
  223. *
  224. * This checks for the signature and if it is not found returns to
  225. * the FEL code in the BROM to wait and receive the main u-boot
  226. * binary over USB. If it is found, it determines where SPL was
  227. * read from.
  228. */
  229. if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
  230. return BOOT_DEVICE_BOARD;
  231. boot_source = readb(SPL_ADDR + 0x28);
  232. switch (boot_source) {
  233. case SUNXI_BOOTED_FROM_MMC0:
  234. case SUNXI_BOOTED_FROM_MMC0_HIGH:
  235. return BOOT_DEVICE_MMC1;
  236. case SUNXI_BOOTED_FROM_NAND:
  237. return BOOT_DEVICE_NAND;
  238. case SUNXI_BOOTED_FROM_MMC2:
  239. case SUNXI_BOOTED_FROM_MMC2_HIGH:
  240. return BOOT_DEVICE_MMC2;
  241. case SUNXI_BOOTED_FROM_SPI:
  242. return BOOT_DEVICE_SPI;
  243. }
  244. panic("Unknown boot source %d\n", boot_source);
  245. return -1; /* Never reached */
  246. }
  247. #ifdef CONFIG_SPL_BUILD
  248. u32 spl_boot_device(void)
  249. {
  250. return sunxi_get_boot_device();
  251. }
  252. void board_init_f(ulong dummy)
  253. {
  254. spl_init();
  255. preloader_console_init();
  256. #ifdef CONFIG_SPL_I2C_SUPPORT
  257. /* Needed early by sunxi_board_init if PMU is enabled */
  258. i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
  259. #endif
  260. sunxi_board_init();
  261. }
  262. #endif
  263. void reset_cpu(ulong addr)
  264. {
  265. #if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40)
  266. static const struct sunxi_wdog *wdog =
  267. &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
  268. /* Set the watchdog for its shortest interval (.5s) and wait */
  269. writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
  270. writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
  271. while (1) {
  272. /* sun5i sometimes gets stuck without this */
  273. writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
  274. }
  275. #elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6)
  276. #if defined(CONFIG_MACH_SUN50I_H6)
  277. /* WDOG is broken for some H6 rev. use the R_WDOG instead */
  278. static const struct sunxi_wdog *wdog =
  279. (struct sunxi_wdog *)SUNXI_R_WDOG_BASE;
  280. #else
  281. static const struct sunxi_wdog *wdog =
  282. ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
  283. #endif
  284. /* Set the watchdog for its shortest interval (.5s) and wait */
  285. writel(WDT_CFG_RESET, &wdog->cfg);
  286. writel(WDT_MODE_EN, &wdog->mode);
  287. writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
  288. while (1) { }
  289. #endif
  290. }
  291. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
  292. void enable_caches(void)
  293. {
  294. /* Enable D-cache. I-cache is already enabled in start.S */
  295. dcache_enable();
  296. }
  297. #endif