cpu.c 16 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
  4. */
  5. #include <common.h>
  6. #include <ahci.h>
  7. #include <cpu_func.h>
  8. #include <linux/mbus.h>
  9. #include <asm/io.h>
  10. #include <asm/pl310.h>
  11. #include <asm/arch/cpu.h>
  12. #include <asm/arch/soc.h>
  13. #include <sdhci.h>
  14. #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
  15. #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
  16. static struct mbus_win windows[] = {
  17. /* SPI */
  18. { MBUS_SPI_BASE, MBUS_SPI_SIZE,
  19. CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPIFLASH },
  20. /* NOR */
  21. { MBUS_BOOTROM_BASE, MBUS_BOOTROM_SIZE,
  22. CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM },
  23. #ifdef CONFIG_ARMADA_MSYS
  24. /* DFX */
  25. { MBUS_DFX_BASE, MBUS_DFX_SIZE, CPU_TARGET_DFX, 0 },
  26. #endif
  27. };
  28. void lowlevel_init(void)
  29. {
  30. /*
  31. * Dummy implementation, we only need LOWLEVEL_INIT
  32. * on Armada to configure CP15 in start.S / cpu_init_cp15()
  33. */
  34. }
  35. void reset_cpu(unsigned long ignored)
  36. {
  37. struct mvebu_system_registers *reg =
  38. (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE;
  39. writel(readl(&reg->rstoutn_mask) | 1, &reg->rstoutn_mask);
  40. writel(readl(&reg->sys_soft_rst) | 1, &reg->sys_soft_rst);
  41. while (1)
  42. ;
  43. }
  44. int mvebu_soc_family(void)
  45. {
  46. u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
  47. switch (devid) {
  48. case SOC_MV78230_ID:
  49. case SOC_MV78260_ID:
  50. case SOC_MV78460_ID:
  51. return MVEBU_SOC_AXP;
  52. case SOC_88F6720_ID:
  53. return MVEBU_SOC_A375;
  54. case SOC_88F6810_ID:
  55. case SOC_88F6820_ID:
  56. case SOC_88F6828_ID:
  57. return MVEBU_SOC_A38X;
  58. case SOC_98DX3236_ID:
  59. case SOC_98DX3336_ID:
  60. case SOC_98DX4251_ID:
  61. return MVEBU_SOC_MSYS;
  62. }
  63. return MVEBU_SOC_UNKNOWN;
  64. }
  65. #if defined(CONFIG_DISPLAY_CPUINFO)
  66. #if defined(CONFIG_ARMADA_375)
  67. /* SAR frequency values for Armada 375 */
  68. static const struct sar_freq_modes sar_freq_tab[] = {
  69. { 0, 0x0, 266, 133, 266 },
  70. { 1, 0x0, 333, 167, 167 },
  71. { 2, 0x0, 333, 167, 222 },
  72. { 3, 0x0, 333, 167, 333 },
  73. { 4, 0x0, 400, 200, 200 },
  74. { 5, 0x0, 400, 200, 267 },
  75. { 6, 0x0, 400, 200, 400 },
  76. { 7, 0x0, 500, 250, 250 },
  77. { 8, 0x0, 500, 250, 334 },
  78. { 9, 0x0, 500, 250, 500 },
  79. { 10, 0x0, 533, 267, 267 },
  80. { 11, 0x0, 533, 267, 356 },
  81. { 12, 0x0, 533, 267, 533 },
  82. { 13, 0x0, 600, 300, 300 },
  83. { 14, 0x0, 600, 300, 400 },
  84. { 15, 0x0, 600, 300, 600 },
  85. { 16, 0x0, 666, 333, 333 },
  86. { 17, 0x0, 666, 333, 444 },
  87. { 18, 0x0, 666, 333, 666 },
  88. { 19, 0x0, 800, 400, 267 },
  89. { 20, 0x0, 800, 400, 400 },
  90. { 21, 0x0, 800, 400, 534 },
  91. { 22, 0x0, 900, 450, 300 },
  92. { 23, 0x0, 900, 450, 450 },
  93. { 24, 0x0, 900, 450, 600 },
  94. { 25, 0x0, 1000, 500, 500 },
  95. { 26, 0x0, 1000, 500, 667 },
  96. { 27, 0x0, 1000, 333, 500 },
  97. { 28, 0x0, 400, 400, 400 },
  98. { 29, 0x0, 1100, 550, 550 },
  99. { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
  100. };
  101. #elif defined(CONFIG_ARMADA_38X)
  102. /* SAR frequency values for Armada 38x */
  103. static const struct sar_freq_modes sar_freq_tab[] = {
  104. { 0x0, 0x0, 666, 333, 333 },
  105. { 0x2, 0x0, 800, 400, 400 },
  106. { 0x4, 0x0, 1066, 533, 533 },
  107. { 0x6, 0x0, 1200, 600, 600 },
  108. { 0x8, 0x0, 1332, 666, 666 },
  109. { 0xc, 0x0, 1600, 800, 800 },
  110. { 0x10, 0x0, 1866, 933, 933 },
  111. { 0x13, 0x0, 2000, 1000, 933 },
  112. { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
  113. };
  114. #elif defined(CONFIG_ARMADA_MSYS)
  115. static const struct sar_freq_modes sar_freq_tab[] = {
  116. { 0x0, 0x0, 400, 400, 400 },
  117. { 0x2, 0x0, 667, 333, 667 },
  118. { 0x3, 0x0, 800, 400, 800 },
  119. { 0x5, 0x0, 800, 400, 800 },
  120. { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
  121. };
  122. #else
  123. /* SAR frequency values for Armada XP */
  124. static const struct sar_freq_modes sar_freq_tab[] = {
  125. { 0xa, 0x5, 800, 400, 400 },
  126. { 0x1, 0x5, 1066, 533, 533 },
  127. { 0x2, 0x5, 1200, 600, 600 },
  128. { 0x2, 0x9, 1200, 600, 400 },
  129. { 0x3, 0x5, 1333, 667, 667 },
  130. { 0x4, 0x5, 1500, 750, 750 },
  131. { 0x4, 0x9, 1500, 750, 500 },
  132. { 0xb, 0x9, 1600, 800, 533 },
  133. { 0xb, 0xa, 1600, 800, 640 },
  134. { 0xb, 0x5, 1600, 800, 800 },
  135. { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
  136. };
  137. #endif
  138. void get_sar_freq(struct sar_freq_modes *sar_freq)
  139. {
  140. u32 val;
  141. u32 freq;
  142. int i;
  143. #if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_MSYS)
  144. val = readl(CONFIG_SAR2_REG); /* SAR - Sample At Reset */
  145. #else
  146. val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
  147. #endif
  148. freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS;
  149. #if defined(SAR2_CPU_FREQ_MASK)
  150. /*
  151. * Shift CPU0 clock frequency select bit from SAR2 register
  152. * into correct position
  153. */
  154. freq |= ((readl(CONFIG_SAR2_REG) & SAR2_CPU_FREQ_MASK)
  155. >> SAR2_CPU_FREQ_OFFS) << 3;
  156. #endif
  157. for (i = 0; sar_freq_tab[i].val != 0xff; i++) {
  158. if (sar_freq_tab[i].val == freq) {
  159. #if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_MSYS)
  160. *sar_freq = sar_freq_tab[i];
  161. return;
  162. #else
  163. int k;
  164. u8 ffc;
  165. ffc = (val & SAR_FFC_FREQ_MASK) >>
  166. SAR_FFC_FREQ_OFFS;
  167. for (k = i; sar_freq_tab[k].ffc != 0xff; k++) {
  168. if (sar_freq_tab[k].ffc == ffc) {
  169. *sar_freq = sar_freq_tab[k];
  170. return;
  171. }
  172. }
  173. i = k;
  174. #endif
  175. }
  176. }
  177. /* SAR value not found, return 0 for frequencies */
  178. *sar_freq = sar_freq_tab[i - 1];
  179. }
  180. int print_cpuinfo(void)
  181. {
  182. u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
  183. u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff;
  184. struct sar_freq_modes sar_freq;
  185. puts("SoC: ");
  186. switch (devid) {
  187. case SOC_MV78230_ID:
  188. puts("MV78230-");
  189. break;
  190. case SOC_MV78260_ID:
  191. puts("MV78260-");
  192. break;
  193. case SOC_MV78460_ID:
  194. puts("MV78460-");
  195. break;
  196. case SOC_88F6720_ID:
  197. puts("MV88F6720-");
  198. break;
  199. case SOC_88F6810_ID:
  200. puts("MV88F6810-");
  201. break;
  202. case SOC_88F6820_ID:
  203. puts("MV88F6820-");
  204. break;
  205. case SOC_88F6828_ID:
  206. puts("MV88F6828-");
  207. break;
  208. case SOC_98DX3236_ID:
  209. puts("98DX3236-");
  210. break;
  211. case SOC_98DX3336_ID:
  212. puts("98DX3336-");
  213. break;
  214. case SOC_98DX4251_ID:
  215. puts("98DX4251-");
  216. break;
  217. default:
  218. puts("Unknown-");
  219. break;
  220. }
  221. if (mvebu_soc_family() == MVEBU_SOC_AXP) {
  222. switch (revid) {
  223. case 1:
  224. puts("A0");
  225. break;
  226. case 2:
  227. puts("B0");
  228. break;
  229. default:
  230. printf("?? (%x)", revid);
  231. break;
  232. }
  233. }
  234. if (mvebu_soc_family() == MVEBU_SOC_A375) {
  235. switch (revid) {
  236. case MV_88F67XX_A0_ID:
  237. puts("A0");
  238. break;
  239. default:
  240. printf("?? (%x)", revid);
  241. break;
  242. }
  243. }
  244. if (mvebu_soc_family() == MVEBU_SOC_A38X) {
  245. switch (revid) {
  246. case MV_88F68XX_Z1_ID:
  247. puts("Z1");
  248. break;
  249. case MV_88F68XX_A0_ID:
  250. puts("A0");
  251. break;
  252. case MV_88F68XX_B0_ID:
  253. puts("B0");
  254. break;
  255. default:
  256. printf("?? (%x)", revid);
  257. break;
  258. }
  259. }
  260. if (mvebu_soc_family() == MVEBU_SOC_MSYS) {
  261. switch (revid) {
  262. case 3:
  263. puts("A0");
  264. break;
  265. case 4:
  266. puts("A1");
  267. break;
  268. default:
  269. printf("?? (%x)", revid);
  270. break;
  271. }
  272. }
  273. get_sar_freq(&sar_freq);
  274. printf(" at %d MHz\n", sar_freq.p_clk);
  275. return 0;
  276. }
  277. #endif /* CONFIG_DISPLAY_CPUINFO */
  278. /*
  279. * This function initialize Controller DRAM Fastpath windows.
  280. * It takes the CS size information from the 0x1500 scratch registers
  281. * and sets the correct windows sizes and base addresses accordingly.
  282. *
  283. * These values are set in the scratch registers by the Marvell
  284. * DDR3 training code, which is executed by the SPL before the
  285. * main payload (U-Boot) is executed.
  286. */
  287. static void update_sdram_window_sizes(void)
  288. {
  289. u64 base = 0;
  290. u32 size, temp;
  291. int i;
  292. for (i = 0; i < SDRAM_MAX_CS; i++) {
  293. size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK;
  294. if (size != 0) {
  295. size |= ~(SDRAM_ADDR_MASK);
  296. /* Set Base Address */
  297. temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF);
  298. writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i));
  299. /*
  300. * Check if out of max window size and resize
  301. * the window
  302. */
  303. temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) &
  304. ~(SDRAM_ADDR_MASK)) | 1;
  305. temp |= (size & SDRAM_ADDR_MASK);
  306. writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i));
  307. base += ((u64)size + 1);
  308. } else {
  309. /*
  310. * Disable window if not used, otherwise this
  311. * leads to overlapping enabled windows with
  312. * pretty strange results
  313. */
  314. clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1);
  315. }
  316. }
  317. }
  318. void mmu_disable(void)
  319. {
  320. asm volatile(
  321. "mrc p15, 0, r0, c1, c0, 0\n"
  322. "bic r0, #1\n"
  323. "mcr p15, 0, r0, c1, c0, 0\n");
  324. }
  325. #ifdef CONFIG_ARCH_CPU_INIT
  326. static void set_cbar(u32 addr)
  327. {
  328. asm("mcr p15, 4, %0, c15, c0" : : "r" (addr));
  329. }
  330. #define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800)
  331. #define MV_USB_PHY_PLL_REG(reg) (MV_USB_PHY_BASE | (((reg) & 0xF) << 2))
  332. #define MV_USB_X3_BASE(addr) (MVEBU_AXP_USB_BASE | BIT(11) | \
  333. (((addr) & 0xF) << 6))
  334. #define MV_USB_X3_PHY_CHANNEL(dev, reg) (MV_USB_X3_BASE((dev) + 1) | \
  335. (((reg) & 0xF) << 2))
  336. static void setup_usb_phys(void)
  337. {
  338. int dev;
  339. /*
  340. * USB PLL init
  341. */
  342. /* Setup PLL frequency */
  343. /* USB REF frequency = 25 MHz */
  344. clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0x3ff, 0x605);
  345. /* Power up PLL and PHY channel */
  346. setbits_le32(MV_USB_PHY_PLL_REG(2), BIT(9));
  347. /* Assert VCOCAL_START */
  348. setbits_le32(MV_USB_PHY_PLL_REG(1), BIT(21));
  349. mdelay(1);
  350. /*
  351. * USB PHY init (change from defaults) specific for 40nm (78X30 78X60)
  352. */
  353. for (dev = 0; dev < 3; dev++) {
  354. setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), BIT(15));
  355. /* Assert REG_RCAL_START in channel REG 1 */
  356. setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
  357. udelay(40);
  358. clrbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
  359. }
  360. }
  361. /*
  362. * This function is not called from the SPL U-Boot version
  363. */
  364. int arch_cpu_init(void)
  365. {
  366. struct pl310_regs *const pl310 =
  367. (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  368. /*
  369. * Only with disabled MMU its possible to switch the base
  370. * register address on Armada 38x. Without this the SDRAM
  371. * located at >= 0x4000.0000 is also not accessible, as its
  372. * still locked to cache.
  373. */
  374. mmu_disable();
  375. /* Linux expects the internal registers to be at 0xf1000000 */
  376. writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
  377. set_cbar(SOC_REGS_PHY_BASE + 0xC000);
  378. /*
  379. * From this stage on, the SoC detection is working. As we have
  380. * configured the internal register base to the value used
  381. * in the macros / defines in the U-Boot header (soc.h).
  382. */
  383. if (mvebu_soc_family() == MVEBU_SOC_A38X) {
  384. /*
  385. * To fully release / unlock this area from cache, we need
  386. * to flush all caches and disable the L2 cache.
  387. */
  388. icache_disable();
  389. dcache_disable();
  390. clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  391. }
  392. /*
  393. * We need to call mvebu_mbus_probe() before calling
  394. * update_sdram_window_sizes() as it disables all previously
  395. * configured mbus windows and then configures them as
  396. * required for U-Boot. Calling update_sdram_window_sizes()
  397. * without this configuration will not work, as the internal
  398. * registers can't be accessed reliably because of potenial
  399. * double mapping.
  400. * After updating the SDRAM access windows we need to call
  401. * mvebu_mbus_probe() again, as this now correctly configures
  402. * the SDRAM areas that are later used by the MVEBU drivers
  403. * (e.g. USB, NETA).
  404. */
  405. /*
  406. * First disable all windows
  407. */
  408. mvebu_mbus_probe(NULL, 0);
  409. if (mvebu_soc_family() == MVEBU_SOC_AXP) {
  410. /*
  411. * Now the SDRAM access windows can be reconfigured using
  412. * the information in the SDRAM scratch pad registers
  413. */
  414. update_sdram_window_sizes();
  415. }
  416. /*
  417. * Finally the mbus windows can be configured with the
  418. * updated SDRAM sizes
  419. */
  420. mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
  421. if (mvebu_soc_family() == MVEBU_SOC_AXP) {
  422. /* Enable GBE0, GBE1, LCD and NFC PUP */
  423. clrsetbits_le32(ARMADA_XP_PUP_ENABLE, 0,
  424. GE0_PUP_EN | GE1_PUP_EN | LCD_PUP_EN |
  425. NAND_PUP_EN | SPI_PUP_EN);
  426. /* Configure USB PLL and PHYs on AXP */
  427. setup_usb_phys();
  428. }
  429. /* Enable NAND and NAND arbiter */
  430. clrsetbits_le32(MVEBU_SOC_DEV_MUX_REG, 0, NAND_EN | NAND_ARBITER_EN);
  431. /* Disable MBUS error propagation */
  432. clrsetbits_le32(SOC_COHERENCY_FABRIC_CTRL_REG, MBUS_ERR_PROP_EN, 0);
  433. return 0;
  434. }
  435. #endif /* CONFIG_ARCH_CPU_INIT */
  436. u32 mvebu_get_nand_clock(void)
  437. {
  438. u32 reg;
  439. if (mvebu_soc_family() == MVEBU_SOC_A38X)
  440. reg = MVEBU_DFX_DIV_CLK_CTRL(1);
  441. else if (mvebu_soc_family() == MVEBU_SOC_MSYS)
  442. reg = MVEBU_DFX_DIV_CLK_CTRL(8);
  443. else
  444. reg = MVEBU_CORE_DIV_CLK_CTRL(1);
  445. return CONFIG_SYS_MVEBU_PLL_CLOCK /
  446. ((readl(reg) &
  447. NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS);
  448. }
  449. /*
  450. * SOC specific misc init
  451. */
  452. #if defined(CONFIG_ARCH_MISC_INIT)
  453. int arch_misc_init(void)
  454. {
  455. /* Nothing yet, perhaps we need something here later */
  456. return 0;
  457. }
  458. #endif /* CONFIG_ARCH_MISC_INIT */
  459. #if defined(CONFIG_MMC_SDHCI_MV) && !defined(CONFIG_DM_MMC)
  460. int board_mmc_init(bd_t *bis)
  461. {
  462. mv_sdh_init(MVEBU_SDIO_BASE, 0, 0,
  463. SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD);
  464. return 0;
  465. }
  466. #endif
  467. #define AHCI_VENDOR_SPECIFIC_0_ADDR 0xa0
  468. #define AHCI_VENDOR_SPECIFIC_0_DATA 0xa4
  469. #define AHCI_WINDOW_CTRL(win) (0x60 + ((win) << 4))
  470. #define AHCI_WINDOW_BASE(win) (0x64 + ((win) << 4))
  471. #define AHCI_WINDOW_SIZE(win) (0x68 + ((win) << 4))
  472. static void ahci_mvebu_mbus_config(void __iomem *base)
  473. {
  474. const struct mbus_dram_target_info *dram;
  475. int i;
  476. /* mbus is not initialized in SPL; keep the ROM settings */
  477. if (IS_ENABLED(CONFIG_SPL_BUILD))
  478. return;
  479. dram = mvebu_mbus_dram_info();
  480. for (i = 0; i < 4; i++) {
  481. writel(0, base + AHCI_WINDOW_CTRL(i));
  482. writel(0, base + AHCI_WINDOW_BASE(i));
  483. writel(0, base + AHCI_WINDOW_SIZE(i));
  484. }
  485. for (i = 0; i < dram->num_cs; i++) {
  486. const struct mbus_dram_window *cs = dram->cs + i;
  487. writel((cs->mbus_attr << 8) |
  488. (dram->mbus_dram_target_id << 4) | 1,
  489. base + AHCI_WINDOW_CTRL(i));
  490. writel(cs->base >> 16, base + AHCI_WINDOW_BASE(i));
  491. writel(((cs->size - 1) & 0xffff0000),
  492. base + AHCI_WINDOW_SIZE(i));
  493. }
  494. }
  495. static void ahci_mvebu_regret_option(void __iomem *base)
  496. {
  497. /*
  498. * Enable the regret bit to allow the SATA unit to regret a
  499. * request that didn't receive an acknowlegde and avoid a
  500. * deadlock
  501. */
  502. writel(0x4, base + AHCI_VENDOR_SPECIFIC_0_ADDR);
  503. writel(0x80, base + AHCI_VENDOR_SPECIFIC_0_DATA);
  504. }
  505. int board_ahci_enable(void)
  506. {
  507. ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE);
  508. ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE);
  509. return 0;
  510. }
  511. #ifdef CONFIG_SCSI_AHCI_PLAT
  512. void scsi_init(void)
  513. {
  514. printf("MVEBU SATA INIT\n");
  515. board_ahci_enable();
  516. ahci_init((void __iomem *)MVEBU_SATA0_BASE);
  517. }
  518. #endif
  519. #ifdef CONFIG_USB_XHCI_MVEBU
  520. #define USB3_MAX_WINDOWS 4
  521. #define USB3_WIN_CTRL(w) (0x0 + ((w) * 8))
  522. #define USB3_WIN_BASE(w) (0x4 + ((w) * 8))
  523. static void xhci_mvebu_mbus_config(void __iomem *base,
  524. const struct mbus_dram_target_info *dram)
  525. {
  526. int i;
  527. for (i = 0; i < USB3_MAX_WINDOWS; i++) {
  528. writel(0, base + USB3_WIN_CTRL(i));
  529. writel(0, base + USB3_WIN_BASE(i));
  530. }
  531. for (i = 0; i < dram->num_cs; i++) {
  532. const struct mbus_dram_window *cs = dram->cs + i;
  533. /* Write size, attributes and target id to control register */
  534. writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
  535. (dram->mbus_dram_target_id << 4) | 1,
  536. base + USB3_WIN_CTRL(i));
  537. /* Write base address to base register */
  538. writel((cs->base & 0xffff0000), base + USB3_WIN_BASE(i));
  539. }
  540. }
  541. int board_xhci_enable(fdt_addr_t base)
  542. {
  543. const struct mbus_dram_target_info *dram;
  544. printf("MVEBU XHCI INIT controller @ 0x%lx\n", base);
  545. dram = mvebu_mbus_dram_info();
  546. xhci_mvebu_mbus_config((void __iomem *)base, dram);
  547. return 0;
  548. }
  549. #endif
  550. void enable_caches(void)
  551. {
  552. /* Avoid problem with e.g. neta ethernet driver */
  553. invalidate_dcache_all();
  554. /*
  555. * Armada 375 still has some problems with d-cache enabled in the
  556. * ethernet driver (mvpp2). So lets keep the d-cache disabled
  557. * until this is solved.
  558. */
  559. if (mvebu_soc_family() != MVEBU_SOC_A375) {
  560. /* Enable D-cache. I-cache is already enabled in start.S */
  561. dcache_enable();
  562. }
  563. }
  564. void v7_outer_cache_enable(void)
  565. {
  566. if (mvebu_soc_family() == MVEBU_SOC_AXP) {
  567. struct pl310_regs *const pl310 =
  568. (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  569. u32 u;
  570. /* The L2 cache is already disabled at this point */
  571. /*
  572. * For Aurora cache in no outer mode, enable via the CP15
  573. * coprocessor broadcasting of cache commands to L2.
  574. */
  575. asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u));
  576. u |= BIT(8); /* Set the FW bit */
  577. asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u));
  578. isb();
  579. /* Enable the L2 cache */
  580. setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  581. }
  582. }
  583. void v7_outer_cache_disable(void)
  584. {
  585. struct pl310_regs *const pl310 =
  586. (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  587. clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  588. }