init.c 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Keystone2: Architecture initialization
  4. *
  5. * (C) Copyright 2012-2014
  6. * Texas Instruments Incorporated, <www.ti.com>
  7. */
  8. #include <common.h>
  9. #include <cpu_func.h>
  10. #include <ns16550.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/msmc.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/arch/hardware.h>
  15. #include <asm/arch/psc_defs.h>
  16. #define MAX_PCI_PORTS 2
  17. enum pci_mode {
  18. ENDPOINT,
  19. LEGACY_ENDPOINT,
  20. ROOTCOMPLEX,
  21. };
  22. #define DEVCFG_MODE_MASK (BIT(2) | BIT(1))
  23. #define DEVCFG_MODE_SHIFT 1
  24. void chip_configuration_unlock(void)
  25. {
  26. __raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
  27. __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
  28. }
  29. #ifdef CONFIG_SOC_K2L
  30. void osr_init(void)
  31. {
  32. u32 i;
  33. u32 j;
  34. u32 val;
  35. u32 base = KS2_OSR_CFG_BASE;
  36. u32 ecc_ctrl[KS2_OSR_NUM_RAM_BANKS];
  37. /* Enable the OSR clock domain */
  38. psc_enable_module(KS2_LPSC_OSR);
  39. /* Disable OSR ECC check for all the ram banks */
  40. for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++) {
  41. val = i | KS2_OSR_ECC_VEC_TRIG_RD |
  42. (KS2_OSR_ECC_CTRL << KS2_OSR_ECC_VEC_RD_ADDR_SH);
  43. writel(val , base + KS2_OSR_ECC_VEC);
  44. /**
  45. * wait till read is done.
  46. * Print should be added after earlyprintk support is added.
  47. */
  48. for (j = 0; j < 10000; j++) {
  49. val = readl(base + KS2_OSR_ECC_VEC);
  50. if (val & KS2_OSR_ECC_VEC_RD_DONE)
  51. break;
  52. }
  53. ecc_ctrl[i] = readl(base + KS2_OSR_ECC_CTRL) ^
  54. KS2_OSR_ECC_CTRL_CHK;
  55. writel(ecc_ctrl[i], KS2_MSMC_DATA_BASE + i * 4);
  56. writel(ecc_ctrl[i], base + KS2_OSR_ECC_CTRL);
  57. }
  58. /* Reset OSR memory to all zeros */
  59. for (i = 0; i < KS2_OSR_SIZE; i += 4)
  60. writel(0, KS2_OSR_DATA_BASE + i);
  61. /* Enable OSR ECC check for all the ram banks */
  62. for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++)
  63. writel(ecc_ctrl[i] |
  64. KS2_OSR_ECC_CTRL_CHK, base + KS2_OSR_ECC_CTRL);
  65. }
  66. #endif
  67. /* Function to set up PCIe mode */
  68. static void config_pcie_mode(int pcie_port, enum pci_mode mode)
  69. {
  70. u32 val = __raw_readl(KS2_DEVCFG);
  71. if (pcie_port >= MAX_PCI_PORTS)
  72. return;
  73. /**
  74. * each pci port has two bits for mode and it starts at
  75. * bit 1. So use port number to get the right bit position.
  76. */
  77. pcie_port <<= 1;
  78. val &= ~(DEVCFG_MODE_MASK << pcie_port);
  79. val |= ((mode << DEVCFG_MODE_SHIFT) << pcie_port);
  80. __raw_writel(val, KS2_DEVCFG);
  81. }
  82. static void msmc_k2hkle_common_setup(void)
  83. {
  84. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_0);
  85. msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_ARM);
  86. msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_NETCP);
  87. msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_QM_PDSP);
  88. msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_PCIE0);
  89. msmc_share_all_segments(KS2_MSMC_SEGMENT_DEBUG);
  90. }
  91. static void msmc_k2hk_setup(void)
  92. {
  93. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_1);
  94. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_2);
  95. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_3);
  96. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_4);
  97. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_5);
  98. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_6);
  99. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_7);
  100. msmc_share_all_segments(K2HKE_MSMC_SEGMENT_HYPERLINK);
  101. }
  102. static inline void msmc_k2l_setup(void)
  103. {
  104. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_1);
  105. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_2);
  106. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_3);
  107. msmc_share_all_segments(K2L_MSMC_SEGMENT_PCIE1);
  108. }
  109. static inline void msmc_k2e_setup(void)
  110. {
  111. msmc_share_all_segments(K2E_MSMC_SEGMENT_PCIE1);
  112. msmc_share_all_segments(K2HKE_MSMC_SEGMENT_HYPERLINK);
  113. msmc_share_all_segments(K2E_MSMC_SEGMENT_TSIP);
  114. }
  115. static void msmc_k2g_setup(void)
  116. {
  117. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_0);
  118. msmc_share_all_segments(K2G_MSMC_SEGMENT_ARM);
  119. msmc_share_all_segments(K2G_MSMC_SEGMENT_ICSS0);
  120. msmc_share_all_segments(K2G_MSMC_SEGMENT_ICSS1);
  121. msmc_share_all_segments(K2G_MSMC_SEGMENT_NSS);
  122. msmc_share_all_segments(K2G_MSMC_SEGMENT_PCIE);
  123. msmc_share_all_segments(K2G_MSMC_SEGMENT_USB);
  124. msmc_share_all_segments(K2G_MSMC_SEGMENT_MLB);
  125. msmc_share_all_segments(K2G_MSMC_SEGMENT_PMMC);
  126. msmc_share_all_segments(K2G_MSMC_SEGMENT_DSS);
  127. msmc_share_all_segments(K2G_MSMC_SEGMENT_MMC);
  128. msmc_share_all_segments(KS2_MSMC_SEGMENT_DEBUG);
  129. }
  130. int arch_cpu_init(void)
  131. {
  132. chip_configuration_unlock();
  133. icache_enable();
  134. if (cpu_is_k2g()) {
  135. msmc_k2g_setup();
  136. } else {
  137. msmc_k2hkle_common_setup();
  138. if (cpu_is_k2e())
  139. msmc_k2e_setup();
  140. else if (cpu_is_k2l())
  141. msmc_k2l_setup();
  142. else
  143. msmc_k2hk_setup();
  144. }
  145. /* Initialize the PCIe-0 to work as Root Complex */
  146. config_pcie_mode(0, ROOTCOMPLEX);
  147. #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
  148. /* Initialize the PCIe-1 to work as Root Complex */
  149. config_pcie_mode(1, ROOTCOMPLEX);
  150. #endif
  151. #ifdef CONFIG_SOC_K2L
  152. osr_init();
  153. #endif
  154. /*
  155. * just initialise the COM2 port so that TI specific
  156. * UART register PWREMU_MGMT is initialized. Linux UART
  157. * driver doesn't handle this.
  158. */
  159. #ifndef CONFIG_DM_SERIAL
  160. NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM2),
  161. CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
  162. #endif
  163. return 0;
  164. }
  165. void reset_cpu(ulong addr)
  166. {
  167. volatile u32 *rstctrl = (volatile u32 *)(KS2_RSTCTRL);
  168. u32 tmp;
  169. tmp = *rstctrl & KS2_RSTCTRL_MASK;
  170. *rstctrl = tmp | KS2_RSTCTRL_KEY;
  171. *rstctrl &= KS2_RSTCTRL_SWRST;
  172. for (;;)
  173. ;
  174. }
  175. void enable_caches(void)
  176. {
  177. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  178. /* Enable D-cache. I-cache is already enabled in start.S */
  179. dcache_enable();
  180. #endif
  181. }
  182. #if defined(CONFIG_DISPLAY_CPUINFO)
  183. int print_cpuinfo(void)
  184. {
  185. u16 cpu = get_part_number();
  186. u8 rev = cpu_revision();
  187. puts("CPU: ");
  188. switch (cpu) {
  189. case CPU_66AK2Hx:
  190. puts("66AK2Hx SR");
  191. break;
  192. case CPU_66AK2Lx:
  193. puts("66AK2Lx SR");
  194. break;
  195. case CPU_66AK2Ex:
  196. puts("66AK2Ex SR");
  197. break;
  198. case CPU_66AK2Gx:
  199. puts("66AK2Gx");
  200. #ifdef CONFIG_SOC_K2G
  201. {
  202. int speed = get_max_arm_speed(speeds);
  203. if (speed == SPD1000)
  204. puts("-100 ");
  205. else if (speed == SPD600)
  206. puts("-60 ");
  207. else
  208. puts("-xx ");
  209. }
  210. #endif
  211. puts("SR");
  212. break;
  213. default:
  214. puts("Unknown\n");
  215. }
  216. if (rev == 2)
  217. puts("2.0\n");
  218. else if (rev == 1)
  219. puts("1.1\n");
  220. else if (rev == 0)
  221. puts("1.0\n");
  222. else if (rev == 8)
  223. puts("1.0\n");
  224. return 0;
  225. }
  226. #endif