soc.c 8.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2017 NXP
  4. *
  5. * Peng Fan <peng.fan@nxp.com>
  6. */
  7. #include <common.h>
  8. #include <cpu_func.h>
  9. #include <asm/arch/imx-regs.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <asm/mach-imx/hab.h>
  14. #include <asm/mach-imx/boot_mode.h>
  15. #include <asm/mach-imx/syscounter.h>
  16. #include <asm/armv8/mmu.h>
  17. #include <dm/uclass.h>
  18. #include <errno.h>
  19. #include <fdt_support.h>
  20. #include <fsl_wdog.h>
  21. #include <imx_sip.h>
  22. DECLARE_GLOBAL_DATA_PTR;
  23. #if defined(CONFIG_IMX_HAB)
  24. struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
  25. .bank = 1,
  26. .word = 3,
  27. };
  28. #endif
  29. int timer_init(void)
  30. {
  31. #ifdef CONFIG_SPL_BUILD
  32. struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
  33. unsigned long freq = readl(&sctr->cntfid0);
  34. /* Update with accurate clock frequency */
  35. asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
  36. clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
  37. SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
  38. #endif
  39. gd->arch.tbl = 0;
  40. gd->arch.tbu = 0;
  41. return 0;
  42. }
  43. void enable_tzc380(void)
  44. {
  45. struct iomuxc_gpr_base_regs *gpr =
  46. (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  47. /* Enable TZASC and lock setting */
  48. setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
  49. setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
  50. if (is_imx8mm() || is_imx8mn())
  51. setbits_le32(&gpr->gpr[10], BIT(1));
  52. /*
  53. * set Region 0 attribute to allow secure and non-secure
  54. * read/write permission. Found some masters like usb dwc3
  55. * controllers can't work with secure memory.
  56. */
  57. writel(0xf0000000, TZASC_BASE_ADDR + 0x108);
  58. }
  59. void set_wdog_reset(struct wdog_regs *wdog)
  60. {
  61. /*
  62. * Output WDOG_B signal to reset external pmic or POR_B decided by
  63. * the board design. Without external reset, the peripherals/DDR/
  64. * PMIC are not reset, that may cause system working abnormal.
  65. * WDZST bit is write-once only bit. Align this bit in kernel,
  66. * otherwise kernel code will have no chance to set this bit.
  67. */
  68. setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
  69. }
  70. static struct mm_region imx8m_mem_map[] = {
  71. {
  72. /* ROM */
  73. .virt = 0x0UL,
  74. .phys = 0x0UL,
  75. .size = 0x100000UL,
  76. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  77. PTE_BLOCK_OUTER_SHARE
  78. }, {
  79. /* CAAM */
  80. .virt = 0x100000UL,
  81. .phys = 0x100000UL,
  82. .size = 0x8000UL,
  83. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  84. PTE_BLOCK_NON_SHARE |
  85. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  86. }, {
  87. /* TCM */
  88. .virt = 0x7C0000UL,
  89. .phys = 0x7C0000UL,
  90. .size = 0x80000UL,
  91. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  92. PTE_BLOCK_NON_SHARE |
  93. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  94. }, {
  95. /* OCRAM */
  96. .virt = 0x900000UL,
  97. .phys = 0x900000UL,
  98. .size = 0x200000UL,
  99. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  100. PTE_BLOCK_OUTER_SHARE
  101. }, {
  102. /* AIPS */
  103. .virt = 0xB00000UL,
  104. .phys = 0xB00000UL,
  105. .size = 0x3f500000UL,
  106. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  107. PTE_BLOCK_NON_SHARE |
  108. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  109. }, {
  110. /* DRAM1 */
  111. .virt = 0x40000000UL,
  112. .phys = 0x40000000UL,
  113. .size = PHYS_SDRAM_SIZE,
  114. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  115. PTE_BLOCK_OUTER_SHARE
  116. #ifdef PHYS_SDRAM_2_SIZE
  117. }, {
  118. /* DRAM2 */
  119. .virt = 0x100000000UL,
  120. .phys = 0x100000000UL,
  121. .size = PHYS_SDRAM_2_SIZE,
  122. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  123. PTE_BLOCK_OUTER_SHARE
  124. #endif
  125. }, {
  126. /* List terminator */
  127. 0,
  128. }
  129. };
  130. struct mm_region *mem_map = imx8m_mem_map;
  131. void enable_caches(void)
  132. {
  133. /*
  134. * If OPTEE runs, remove OPTEE memory from MMU table to
  135. * avoid speculative prefetch. OPTEE runs at the top of
  136. * the first memory bank
  137. */
  138. if (rom_pointer[1])
  139. imx8m_mem_map[5].size -= rom_pointer[1];
  140. icache_enable();
  141. dcache_enable();
  142. }
  143. static u32 get_cpu_variant_type(u32 type)
  144. {
  145. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  146. struct fuse_bank *bank = &ocotp->bank[1];
  147. struct fuse_bank1_regs *fuse =
  148. (struct fuse_bank1_regs *)bank->fuse_regs;
  149. u32 value = readl(&fuse->tester4);
  150. if (type == MXC_CPU_IMX8MM) {
  151. switch (value & 0x3) {
  152. case 2:
  153. if (value & 0x1c0000)
  154. return MXC_CPU_IMX8MMDL;
  155. else
  156. return MXC_CPU_IMX8MMD;
  157. case 3:
  158. if (value & 0x1c0000)
  159. return MXC_CPU_IMX8MMSL;
  160. else
  161. return MXC_CPU_IMX8MMS;
  162. default:
  163. if (value & 0x1c0000)
  164. return MXC_CPU_IMX8MML;
  165. break;
  166. }
  167. }
  168. return type;
  169. }
  170. u32 get_cpu_rev(void)
  171. {
  172. struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
  173. u32 reg = readl(&ana_pll->digprog);
  174. u32 type = (reg >> 16) & 0xff;
  175. u32 major_low = (reg >> 8) & 0xff;
  176. u32 rom_version;
  177. reg &= 0xff;
  178. /* i.MX8MM */
  179. if (major_low == 0x42) {
  180. return (MXC_CPU_IMX8MN << 12) | reg;
  181. } else if (major_low == 0x41) {
  182. type = get_cpu_variant_type(MXC_CPU_IMX8MM);
  183. } else {
  184. if (reg == CHIP_REV_1_0) {
  185. /*
  186. * For B0 chip, the DIGPROG is not updated,
  187. * it is still TO1.0. we have to check ROM
  188. * version or OCOTP_READ_FUSE_DATA.
  189. * 0xff0055aa is magic number for B1.
  190. */
  191. if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) {
  192. reg = CHIP_REV_2_1;
  193. } else {
  194. rom_version =
  195. readl((void __iomem *)ROM_VERSION_A0);
  196. if (rom_version != CHIP_REV_1_0) {
  197. rom_version = readl((void __iomem *)ROM_VERSION_B0);
  198. if (rom_version == CHIP_REV_2_0)
  199. reg = CHIP_REV_2_0;
  200. }
  201. }
  202. }
  203. }
  204. return (type << 12) | reg;
  205. }
  206. static void imx_set_wdog_powerdown(bool enable)
  207. {
  208. struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
  209. struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
  210. struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
  211. /* Write to the PDE (Power Down Enable) bit */
  212. writew(enable, &wdog1->wmcr);
  213. writew(enable, &wdog2->wmcr);
  214. writew(enable, &wdog3->wmcr);
  215. }
  216. int arch_cpu_init_dm(void)
  217. {
  218. struct udevice *dev;
  219. int ret;
  220. if (CONFIG_IS_ENABLED(CLK)) {
  221. ret = uclass_get_device_by_name(UCLASS_CLK,
  222. "clock-controller@30380000",
  223. &dev);
  224. if (ret < 0) {
  225. printf("Failed to find clock node. Check device tree\n");
  226. return ret;
  227. }
  228. }
  229. return 0;
  230. }
  231. int arch_cpu_init(void)
  232. {
  233. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  234. /*
  235. * ROM might disable clock for SCTR,
  236. * enable the clock before timer_init.
  237. */
  238. if (IS_ENABLED(CONFIG_SPL_BUILD))
  239. clock_enable(CCGR_SCTR, 1);
  240. /*
  241. * Init timer at very early state, because sscg pll setting
  242. * will use it
  243. */
  244. timer_init();
  245. if (IS_ENABLED(CONFIG_SPL_BUILD)) {
  246. clock_init();
  247. imx_set_wdog_powerdown(false);
  248. }
  249. if (is_imx8mq()) {
  250. clock_enable(CCGR_OCOTP, 1);
  251. if (readl(&ocotp->ctrl) & 0x200)
  252. writel(0x200, &ocotp->ctrl_clr);
  253. }
  254. return 0;
  255. }
  256. #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
  257. struct rom_api *g_rom_api = (struct rom_api *)0x980;
  258. enum boot_device get_boot_device(void)
  259. {
  260. volatile gd_t *pgd = gd;
  261. int ret;
  262. u32 boot;
  263. u16 boot_type;
  264. u8 boot_instance;
  265. enum boot_device boot_dev = SD1_BOOT;
  266. ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
  267. ((uintptr_t)&boot) ^ QUERY_BT_DEV);
  268. gd = pgd;
  269. if (ret != ROM_API_OKAY) {
  270. puts("ROMAPI: failure at query_boot_info\n");
  271. return -1;
  272. }
  273. boot_type = boot >> 16;
  274. boot_instance = (boot >> 8) & 0xff;
  275. switch (boot_type) {
  276. case BT_DEV_TYPE_SD:
  277. boot_dev = boot_instance + SD1_BOOT;
  278. break;
  279. case BT_DEV_TYPE_MMC:
  280. boot_dev = boot_instance + MMC1_BOOT;
  281. break;
  282. case BT_DEV_TYPE_NAND:
  283. boot_dev = NAND_BOOT;
  284. break;
  285. case BT_DEV_TYPE_FLEXSPINOR:
  286. boot_dev = QSPI_BOOT;
  287. break;
  288. case BT_DEV_TYPE_USB:
  289. boot_dev = USB_BOOT;
  290. break;
  291. default:
  292. break;
  293. }
  294. return boot_dev;
  295. }
  296. #endif
  297. bool is_usb_boot(void)
  298. {
  299. return get_boot_device() == USB_BOOT;
  300. }
  301. #ifdef CONFIG_OF_SYSTEM_SETUP
  302. int ft_system_setup(void *blob, bd_t *bd)
  303. {
  304. int i = 0;
  305. int rc;
  306. int nodeoff;
  307. /* Disable the CPU idle for A0 chip since the HW does not support it */
  308. if (is_soc_rev(CHIP_REV_1_0)) {
  309. static const char * const nodes_path[] = {
  310. "/cpus/cpu@0",
  311. "/cpus/cpu@1",
  312. "/cpus/cpu@2",
  313. "/cpus/cpu@3",
  314. };
  315. for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
  316. nodeoff = fdt_path_offset(blob, nodes_path[i]);
  317. if (nodeoff < 0)
  318. continue; /* Not found, skip it */
  319. printf("Found %s node\n", nodes_path[i]);
  320. rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
  321. if (rc) {
  322. printf("Unable to update property %s:%s, err=%s\n",
  323. nodes_path[i], "status", fdt_strerror(rc));
  324. return rc;
  325. }
  326. printf("Remove %s:%s\n", nodes_path[i],
  327. "cpu-idle-states");
  328. }
  329. }
  330. return 0;
  331. }
  332. #endif
  333. #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SYSRESET)
  334. void reset_cpu(ulong addr)
  335. {
  336. struct watchdog_regs *wdog = (struct watchdog_regs *)addr;
  337. if (!addr)
  338. wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
  339. /* Clear WDA to trigger WDOG_B immediately */
  340. writew((WCR_WDE | WCR_SRS), &wdog->wcr);
  341. while (1) {
  342. /*
  343. * spin for .5 seconds before reset
  344. */
  345. }
  346. }
  347. #endif