cache.c 8.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
  4. * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <errno.h>
  9. #include <asm/armv7m.h>
  10. #include <asm/io.h>
  11. /* Cache maintenance operation registers */
  12. #define V7M_CACHE_REG_ICIALLU ((u32 *)(V7M_CACHE_MAINT_BASE + 0x00))
  13. #define INVAL_ICACHE_POU 0
  14. #define V7M_CACHE_REG_ICIMVALU ((u32 *)(V7M_CACHE_MAINT_BASE + 0x08))
  15. #define V7M_CACHE_REG_DCIMVAC ((u32 *)(V7M_CACHE_MAINT_BASE + 0x0C))
  16. #define V7M_CACHE_REG_DCISW ((u32 *)(V7M_CACHE_MAINT_BASE + 0x10))
  17. #define V7M_CACHE_REG_DCCMVAU ((u32 *)(V7M_CACHE_MAINT_BASE + 0x14))
  18. #define V7M_CACHE_REG_DCCMVAC ((u32 *)(V7M_CACHE_MAINT_BASE + 0x18))
  19. #define V7M_CACHE_REG_DCCSW ((u32 *)(V7M_CACHE_MAINT_BASE + 0x1C))
  20. #define V7M_CACHE_REG_DCCIMVAC ((u32 *)(V7M_CACHE_MAINT_BASE + 0x20))
  21. #define V7M_CACHE_REG_DCCISW ((u32 *)(V7M_CACHE_MAINT_BASE + 0x24))
  22. #define WAYS_SHIFT 30
  23. #define SETS_SHIFT 5
  24. /* armv7m processor feature registers */
  25. #define V7M_PROC_REG_CLIDR ((u32 *)(V7M_PROC_FTR_BASE + 0x00))
  26. #define V7M_PROC_REG_CTR ((u32 *)(V7M_PROC_FTR_BASE + 0x04))
  27. #define V7M_PROC_REG_CCSIDR ((u32 *)(V7M_PROC_FTR_BASE + 0x08))
  28. #define MASK_NUM_WAYS GENMASK(12, 3)
  29. #define MASK_NUM_SETS GENMASK(27, 13)
  30. #define CLINE_SIZE_MASK GENMASK(2, 0)
  31. #define NUM_WAYS_SHIFT 3
  32. #define NUM_SETS_SHIFT 13
  33. #define V7M_PROC_REG_CSSELR ((u32 *)(V7M_PROC_FTR_BASE + 0x0C))
  34. #define SEL_I_OR_D BIT(0)
  35. enum cache_type {
  36. DCACHE,
  37. ICACHE,
  38. };
  39. /* PoU : Point of Unification, Poc: Point of Coherency */
  40. enum cache_action {
  41. INVALIDATE_POU, /* i-cache invalidate by address */
  42. INVALIDATE_POC, /* d-cache invalidate by address */
  43. INVALIDATE_SET_WAY, /* d-cache invalidate by sets/ways */
  44. FLUSH_POU, /* d-cache clean by address to the PoU */
  45. FLUSH_POC, /* d-cache clean by address to the PoC */
  46. FLUSH_SET_WAY, /* d-cache clean by sets/ways */
  47. FLUSH_INVAL_POC, /* d-cache clean & invalidate by addr to PoC */
  48. FLUSH_INVAL_SET_WAY, /* d-cache clean & invalidate by set/ways */
  49. };
  50. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  51. struct dcache_config {
  52. u32 ways;
  53. u32 sets;
  54. };
  55. static void get_cache_ways_sets(struct dcache_config *cache)
  56. {
  57. u32 cache_size_id = readl(V7M_PROC_REG_CCSIDR);
  58. cache->ways = (cache_size_id & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
  59. cache->sets = (cache_size_id & MASK_NUM_SETS) >> NUM_SETS_SHIFT;
  60. }
  61. /*
  62. * Return the io register to perform required cache action like clean or clean
  63. * & invalidate by sets/ways.
  64. */
  65. static u32 *get_action_reg_set_ways(enum cache_action action)
  66. {
  67. switch (action) {
  68. case INVALIDATE_SET_WAY:
  69. return V7M_CACHE_REG_DCISW;
  70. case FLUSH_SET_WAY:
  71. return V7M_CACHE_REG_DCCSW;
  72. case FLUSH_INVAL_SET_WAY:
  73. return V7M_CACHE_REG_DCCISW;
  74. default:
  75. break;
  76. };
  77. return NULL;
  78. }
  79. /*
  80. * Return the io register to perform required cache action like clean or clean
  81. * & invalidate by adddress or range.
  82. */
  83. static u32 *get_action_reg_range(enum cache_action action)
  84. {
  85. switch (action) {
  86. case INVALIDATE_POU:
  87. return V7M_CACHE_REG_ICIMVALU;
  88. case INVALIDATE_POC:
  89. return V7M_CACHE_REG_DCIMVAC;
  90. case FLUSH_POU:
  91. return V7M_CACHE_REG_DCCMVAU;
  92. case FLUSH_POC:
  93. return V7M_CACHE_REG_DCCMVAC;
  94. case FLUSH_INVAL_POC:
  95. return V7M_CACHE_REG_DCCIMVAC;
  96. default:
  97. break;
  98. }
  99. return NULL;
  100. }
  101. static u32 get_cline_size(enum cache_type type)
  102. {
  103. u32 size;
  104. if (type == DCACHE)
  105. clrbits_le32(V7M_PROC_REG_CSSELR, BIT(SEL_I_OR_D));
  106. else if (type == ICACHE)
  107. setbits_le32(V7M_PROC_REG_CSSELR, BIT(SEL_I_OR_D));
  108. /* Make sure cache selection is effective for next memory access */
  109. dsb();
  110. size = readl(V7M_PROC_REG_CCSIDR) & CLINE_SIZE_MASK;
  111. /* Size enocoded as 2 less than log(no_of_words_in_cache_line) base 2 */
  112. size = 1 << (size + 2);
  113. debug("cache line size is %d\n", size);
  114. return size;
  115. }
  116. /* Perform the action like invalidate/clean on a range of cache addresses */
  117. static int action_cache_range(enum cache_action action, u32 start_addr,
  118. int64_t size)
  119. {
  120. u32 cline_size;
  121. u32 *action_reg;
  122. enum cache_type type;
  123. action_reg = get_action_reg_range(action);
  124. if (!action_reg)
  125. return -EINVAL;
  126. if (action == INVALIDATE_POU)
  127. type = ICACHE;
  128. else
  129. type = DCACHE;
  130. /* Cache line size is minium size for the cache action */
  131. cline_size = get_cline_size(type);
  132. /* Align start address to cache line boundary */
  133. start_addr &= ~(cline_size - 1);
  134. debug("total size for cache action = %llx\n", size);
  135. do {
  136. writel(start_addr, action_reg);
  137. size -= cline_size;
  138. start_addr += cline_size;
  139. } while (size > cline_size);
  140. /* Make sure cache action is effective for next memory access */
  141. dsb();
  142. isb(); /* Make sure instruction stream sees it */
  143. debug("cache action on range done\n");
  144. return 0;
  145. }
  146. /* Perform the action like invalidate/clean on all cached addresses */
  147. static int action_dcache_all(enum cache_action action)
  148. {
  149. struct dcache_config cache;
  150. u32 *action_reg;
  151. int i, j;
  152. action_reg = get_action_reg_set_ways(action);
  153. if (!action_reg)
  154. return -EINVAL;
  155. clrbits_le32(V7M_PROC_REG_CSSELR, BIT(SEL_I_OR_D));
  156. /* Make sure cache selection is effective for next memory access */
  157. dsb();
  158. get_cache_ways_sets(&cache); /* Get number of ways & sets */
  159. debug("cache: ways= %d, sets= %d\n", cache.ways + 1, cache.sets + 1);
  160. for (i = cache.sets; i >= 0; i--) {
  161. for (j = cache.ways; j >= 0; j--) {
  162. writel((j << WAYS_SHIFT) | (i << SETS_SHIFT),
  163. action_reg);
  164. }
  165. }
  166. /* Make sure cache action is effective for next memory access */
  167. dsb();
  168. isb(); /* Make sure instruction stream sees it */
  169. return 0;
  170. }
  171. void dcache_enable(void)
  172. {
  173. if (dcache_status()) /* return if cache already enabled */
  174. return;
  175. if (action_dcache_all(INVALIDATE_SET_WAY)) {
  176. printf("ERR: D-cache not enabled\n");
  177. return;
  178. }
  179. setbits_le32(&V7M_SCB->ccr, BIT(V7M_CCR_DCACHE));
  180. /* Make sure cache action is effective for next memory access */
  181. dsb();
  182. isb(); /* Make sure instruction stream sees it */
  183. }
  184. void dcache_disable(void)
  185. {
  186. if (!dcache_status())
  187. return;
  188. /* if dcache is enabled-> dcache disable & then flush */
  189. if (action_dcache_all(FLUSH_SET_WAY)) {
  190. printf("ERR: D-cache not flushed\n");
  191. return;
  192. }
  193. clrbits_le32(&V7M_SCB->ccr, BIT(V7M_CCR_DCACHE));
  194. /* Make sure cache action is effective for next memory access */
  195. dsb();
  196. isb(); /* Make sure instruction stream sees it */
  197. }
  198. int dcache_status(void)
  199. {
  200. return (readl(&V7M_SCB->ccr) & BIT(V7M_CCR_DCACHE)) != 0;
  201. }
  202. void invalidate_dcache_range(unsigned long start, unsigned long stop)
  203. {
  204. if (action_cache_range(INVALIDATE_POC, start, stop - start)) {
  205. printf("ERR: D-cache not invalidated\n");
  206. return;
  207. }
  208. }
  209. void flush_dcache_range(unsigned long start, unsigned long stop)
  210. {
  211. if (action_cache_range(FLUSH_POC, start, stop - start)) {
  212. printf("ERR: D-cache not flushed\n");
  213. return;
  214. }
  215. }
  216. void flush_dcache_all(void)
  217. {
  218. if (action_dcache_all(FLUSH_SET_WAY)) {
  219. printf("ERR: D-cache not flushed\n");
  220. return;
  221. }
  222. }
  223. void invalidate_dcache_all(void)
  224. {
  225. if (action_dcache_all(INVALIDATE_SET_WAY)) {
  226. printf("ERR: D-cache not invalidated\n");
  227. return;
  228. }
  229. }
  230. #else
  231. void dcache_enable(void)
  232. {
  233. return;
  234. }
  235. void dcache_disable(void)
  236. {
  237. return;
  238. }
  239. int dcache_status(void)
  240. {
  241. return 0;
  242. }
  243. void flush_dcache_all(void)
  244. {
  245. }
  246. void invalidate_dcache_all(void)
  247. {
  248. }
  249. #endif
  250. #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
  251. void invalidate_icache_all(void)
  252. {
  253. writel(INVAL_ICACHE_POU, V7M_CACHE_REG_ICIALLU);
  254. /* Make sure cache action is effective for next memory access */
  255. dsb();
  256. isb(); /* Make sure instruction stream sees it */
  257. }
  258. void icache_enable(void)
  259. {
  260. if (icache_status())
  261. return;
  262. invalidate_icache_all();
  263. setbits_le32(&V7M_SCB->ccr, BIT(V7M_CCR_ICACHE));
  264. /* Make sure cache action is effective for next memory access */
  265. dsb();
  266. isb(); /* Make sure instruction stream sees it */
  267. }
  268. int icache_status(void)
  269. {
  270. return (readl(&V7M_SCB->ccr) & BIT(V7M_CCR_ICACHE)) != 0;
  271. }
  272. void icache_disable(void)
  273. {
  274. if (!icache_status())
  275. return;
  276. isb(); /* flush pipeline */
  277. clrbits_le32(&V7M_SCB->ccr, BIT(V7M_CCR_ICACHE));
  278. isb(); /* subsequent instructions fetch see cache disable effect */
  279. }
  280. #else
  281. void icache_enable(void)
  282. {
  283. return;
  284. }
  285. void icache_disable(void)
  286. {
  287. return;
  288. }
  289. int icache_status(void)
  290. {
  291. return 0;
  292. }
  293. #endif
  294. void enable_caches(void)
  295. {
  296. #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
  297. icache_enable();
  298. #endif
  299. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  300. dcache_enable();
  301. #endif
  302. }