board.c 7.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board.c
  4. *
  5. * Board functions for Bosch Guardian
  6. *
  7. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  8. * Copyright (C) 2018 Robert Bosch Power Tools GmbH
  9. */
  10. #include <common.h>
  11. #include <dm.h>
  12. #include <env_internal.h>
  13. #include <errno.h>
  14. #include <i2c.h>
  15. #include <led.h>
  16. #include <panel.h>
  17. #include <linux/delay.h>
  18. #include <asm/global_data.h>
  19. #include <power/tps65217.h>
  20. #include <spl.h>
  21. #include <watchdog.h>
  22. #include <asm/arch/clock.h>
  23. #include <asm/arch/cpu.h>
  24. #include <asm/arch/ddr_defs.h>
  25. #include <asm/arch/gpio.h>
  26. #include <asm/arch/hardware.h>
  27. #include <asm/arch/mem-guardian.h>
  28. #include <asm/arch/omap.h>
  29. #include <asm/arch/sys_proto.h>
  30. #include <asm/emif.h>
  31. #include <asm/gpio.h>
  32. #include <asm/io.h>
  33. #include <jffs2/load_kernel.h>
  34. #include <mtd.h>
  35. #include <nand.h>
  36. #include <video.h>
  37. #include <video_console.h>
  38. #include "board.h"
  39. DECLARE_GLOBAL_DATA_PTR;
  40. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  41. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  42. static const struct ddr_data ddr3_data = {
  43. .datardsratio0 = MT41K128M16JT125K_RD_DQS,
  44. .datawdsratio0 = MT41K128M16JT125K_WR_DQS,
  45. .datafwsratio0 = MT41K128M16JT125K_PHY_FIFO_WE,
  46. .datawrsratio0 = MT41K128M16JT125K_PHY_WR_DATA,
  47. };
  48. static const struct cmd_control ddr3_cmd_ctrl_data = {
  49. .cmd0csratio = MT41K128M16JT125K_RATIO,
  50. .cmd0iclkout = MT41K128M16JT125K_INVERT_CLKOUT,
  51. .cmd1csratio = MT41K128M16JT125K_RATIO,
  52. .cmd1iclkout = MT41K128M16JT125K_INVERT_CLKOUT,
  53. .cmd2csratio = MT41K128M16JT125K_RATIO,
  54. .cmd2iclkout = MT41K128M16JT125K_INVERT_CLKOUT,
  55. };
  56. static struct emif_regs ddr3_emif_reg_data = {
  57. .sdram_config = MT41K128M16JT125K_EMIF_SDCFG,
  58. .ref_ctrl = MT41K128M16JT125K_EMIF_SDREF,
  59. .sdram_tim1 = MT41K128M16JT125K_EMIF_TIM1,
  60. .sdram_tim2 = MT41K128M16JT125K_EMIF_TIM2,
  61. .sdram_tim3 = MT41K128M16JT125K_EMIF_TIM3,
  62. .zq_config = MT41K128M16JT125K_ZQ_CFG,
  63. .emif_ddr_phy_ctlr_1 = MT41K128M16JT125K_EMIF_READ_LATENCY,
  64. };
  65. #define OSC (V_OSCK / 1000000)
  66. const struct dpll_params dpll_ddr = {
  67. 400, OSC - 1, 1, -1, -1, -1, -1};
  68. void am33xx_spl_board_init(void)
  69. {
  70. int mpu_vdd;
  71. int usb_cur_lim;
  72. /* Get the frequency */
  73. dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
  74. if (i2c_probe(TPS65217_CHIP_PM))
  75. return;
  76. /*
  77. * Increase USB current limit to 1300mA or 1800mA and set
  78. * the MPU voltage controller as needed.
  79. */
  80. if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
  81. usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
  82. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
  83. } else {
  84. usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
  85. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
  86. }
  87. if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
  88. TPS65217_POWER_PATH,
  89. usb_cur_lim,
  90. TPS65217_USB_INPUT_CUR_LIMIT_MASK))
  91. puts("tps65217_reg_write failure\n");
  92. /* Set DCDC3 (CORE) voltage to 1.125V */
  93. if (tps65217_voltage_update(TPS65217_DEFDCDC3,
  94. TPS65217_DCDC_VOLT_SEL_1125MV)) {
  95. puts("tps65217_voltage_update failure\n");
  96. return;
  97. }
  98. /* Set CORE Frequencies to OPP100 */
  99. do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
  100. /* Set DCDC2 (MPU) voltage */
  101. if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
  102. puts("tps65217_voltage_update failure\n");
  103. return;
  104. }
  105. /*
  106. * Set LDO3 to 1.8V and LDO4 to 3.3V
  107. */
  108. if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
  109. TPS65217_DEFLS1,
  110. TPS65217_LDO_VOLTAGE_OUT_1_8,
  111. TPS65217_LDO_MASK))
  112. puts("tps65217_reg_write failure\n");
  113. if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
  114. TPS65217_DEFLS2,
  115. TPS65217_LDO_VOLTAGE_OUT_3_3,
  116. TPS65217_LDO_MASK))
  117. puts("tps65217_reg_write failure\n");
  118. /* Set MPU Frequency to what we detected now that voltages are set */
  119. do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
  120. }
  121. const struct dpll_params *get_dpll_ddr_params(void)
  122. {
  123. enable_i2c0_pin_mux();
  124. i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
  125. return &dpll_ddr;
  126. }
  127. void set_uart_mux_conf(void)
  128. {
  129. enable_uart0_pin_mux();
  130. }
  131. void set_mux_conf_regs(void)
  132. {
  133. enable_board_pin_mux();
  134. }
  135. const struct ctrl_ioregs ioregs = {
  136. .cm0ioctl = MT41K128M16JT125K_IOCTRL_VALUE,
  137. .cm1ioctl = MT41K128M16JT125K_IOCTRL_VALUE,
  138. .cm2ioctl = MT41K128M16JT125K_IOCTRL_VALUE,
  139. .dt0ioctl = MT41K128M16JT125K_IOCTRL_VALUE,
  140. .dt1ioctl = MT41K128M16JT125K_IOCTRL_VALUE,
  141. };
  142. void sdram_init(void)
  143. {
  144. config_ddr(400, &ioregs,
  145. &ddr3_data,
  146. &ddr3_cmd_ctrl_data,
  147. &ddr3_emif_reg_data, 0);
  148. }
  149. #endif
  150. int board_init(void)
  151. {
  152. save_omap_boot_params();
  153. #if defined(CONFIG_HW_WATCHDOG)
  154. hw_watchdog_init();
  155. #endif
  156. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  157. #ifdef CONFIG_MTD_RAW_NAND
  158. gpmc_init();
  159. #endif
  160. return 0;
  161. }
  162. #ifdef CONFIG_BOARD_LATE_INIT
  163. static void set_bootmode_env(void)
  164. {
  165. char *boot_mode_gpio = "gpio@44e07000_14";
  166. int ret;
  167. struct gpio_desc boot_mode_desc;
  168. ret = dm_gpio_lookup_name(boot_mode_gpio, &boot_mode_desc);
  169. if (ret) {
  170. printf("%s is not found\n", boot_mode_gpio);
  171. goto err;
  172. }
  173. ret = dm_gpio_request(&boot_mode_desc, "setup_bootmode_env");
  174. if (ret && ret != -EBUSY) {
  175. printf("requesting gpio: %s failed\n", boot_mode_gpio);
  176. goto err;
  177. }
  178. dm_gpio_set_dir_flags(&boot_mode_desc, GPIOD_IS_IN);
  179. udelay(10);
  180. ret = dm_gpio_get_value(&boot_mode_desc);
  181. if (ret == 0) {
  182. env_set("swi_status", "1");
  183. } else if (ret == 1) {
  184. env_set("swi_status", "0");
  185. } else {
  186. printf("swi status gpio error\n");
  187. goto err;
  188. }
  189. return;
  190. err:
  191. env_set("swi_status", "err");
  192. }
  193. void lcdbacklight_en(void)
  194. {
  195. unsigned long brightness = env_get_ulong("backlight_brightness", 10, 50);
  196. if (brightness > 99 || brightness == 0)
  197. brightness = 99;
  198. /*
  199. * Brightness range:
  200. * WLEDCTRL2 DUTY[6:0]
  201. *
  202. * 000 0000b = 1%
  203. * 000 0001b = 2%
  204. * ...
  205. * 110 0010b = 99%
  206. * 110 0011b = 100%
  207. *
  208. */
  209. tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_WLEDCTRL2,
  210. brightness, 0xFF);
  211. tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_WLEDCTRL1,
  212. brightness != 0 ? 0x0A : 0x02, 0xFF);
  213. }
  214. #if IS_ENABLED(CONFIG_AM335X_LCD)
  215. static void splash_screen(void)
  216. {
  217. struct udevice *video_dev;
  218. struct udevice *console_dev;
  219. struct video_priv *vid_priv;
  220. struct mtd_info *mtd;
  221. size_t len;
  222. int ret;
  223. struct mtd_device *mtd_dev;
  224. struct part_info *part;
  225. u8 pnum;
  226. ret = uclass_get_device(UCLASS_VIDEO, 0, &video_dev);
  227. if (ret != 0) {
  228. debug("video device not found\n");
  229. goto exit;
  230. }
  231. vid_priv = dev_get_uclass_priv(video_dev);
  232. mtdparts_init();
  233. if (find_dev_and_part(SPLASH_SCREEN_NAND_PART, &mtd_dev, &pnum, &part)) {
  234. debug("Could not find nand partition\n");
  235. goto splash_screen_text;
  236. }
  237. mtd = get_nand_dev_by_index(mtd_dev->id->num);
  238. if (!mtd) {
  239. debug("MTD partition is not valid\n");
  240. goto splash_screen_text;
  241. }
  242. len = SPLASH_SCREEN_BMP_FILE_SIZE;
  243. ret = nand_read_skip_bad(mtd, part->offset, &len, NULL,
  244. SPLASH_SCREEN_BMP_FILE_SIZE,
  245. (u_char *)SPLASH_SCREEN_BMP_LOAD_ADDR);
  246. if (ret != 0) {
  247. debug("Reading NAND partition failed\n");
  248. goto splash_screen_text;
  249. }
  250. ret = video_bmp_display(video_dev, SPLASH_SCREEN_BMP_LOAD_ADDR, 0, 0, false);
  251. if (ret != 0) {
  252. debug("No valid bmp image found!!\n");
  253. goto splash_screen_text;
  254. } else {
  255. goto exit;
  256. }
  257. splash_screen_text:
  258. vid_priv->colour_fg = CONSOLE_COLOR_RED;
  259. vid_priv->colour_bg = CONSOLE_COLOR_BLACK;
  260. if (!uclass_first_device_err(UCLASS_VIDEO_CONSOLE, &console_dev)) {
  261. debug("Found console\n");
  262. vidconsole_position_cursor(console_dev, 17, 7);
  263. vidconsole_put_string(console_dev, SPLASH_SCREEN_TEXT);
  264. } else {
  265. debug("No console device found\n");
  266. }
  267. exit:
  268. return;
  269. }
  270. #endif /* CONFIG_AM335X_LCD */
  271. int board_late_init(void)
  272. {
  273. int ret;
  274. struct udevice *cdev;
  275. #ifdef CONFIG_LED_GPIO
  276. led_default_state();
  277. #endif
  278. set_bootmode_env();
  279. ret = uclass_get_device(UCLASS_PANEL, 0, &cdev);
  280. if (ret) {
  281. debug("video panel not found: %d\n", ret);
  282. return ret;
  283. }
  284. lcdbacklight_en();
  285. if (IS_ENABLED(CONFIG_AM335X_LCD))
  286. splash_screen();
  287. return 0;
  288. }
  289. #endif /* CONFIG_BOARD_LATE_INIT */