fec.h 9.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * fec.h -- Fast Ethernet Controller definitions
  4. *
  5. * Some definitions copied from commproc.h for MPC8xx:
  6. * MPC8xx Communication Processor Module.
  7. * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
  8. *
  9. * Add FEC Structure and definitions
  10. * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  11. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  12. */
  13. #ifndef fec_h
  14. #define fec_h
  15. #include <phy.h>
  16. /* Buffer descriptors used FEC.
  17. */
  18. typedef struct cpm_buf_desc {
  19. ushort cbd_sc; /* Status and Control */
  20. ushort cbd_datlen; /* Data length in buffer */
  21. uint cbd_bufaddr; /* Buffer address in host memory */
  22. } cbd_t;
  23. #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
  24. #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
  25. #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
  26. #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
  27. #define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
  28. #define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
  29. #define BD_SC_CM ((ushort)0x0200) /* Continous mode */
  30. #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
  31. #define BD_SC_P ((ushort)0x0100) /* xmt preamble */
  32. #define BD_SC_BR ((ushort)0x0020) /* Break received */
  33. #define BD_SC_FR ((ushort)0x0010) /* Framing error */
  34. #define BD_SC_PR ((ushort)0x0008) /* Parity error */
  35. #define BD_SC_OV ((ushort)0x0002) /* Overrun */
  36. #define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */
  37. /* Buffer descriptor control/status used by Ethernet receive.
  38. */
  39. #define BD_ENET_RX_EMPTY ((ushort)0x8000)
  40. #define BD_ENET_RX_RO1 ((ushort)0x4000)
  41. #define BD_ENET_RX_WRAP ((ushort)0x2000)
  42. #define BD_ENET_RX_INTR ((ushort)0x1000)
  43. #define BD_ENET_RX_RO2 BD_ENET_RX_INTR
  44. #define BD_ENET_RX_LAST ((ushort)0x0800)
  45. #define BD_ENET_RX_FIRST ((ushort)0x0400)
  46. #define BD_ENET_RX_MISS ((ushort)0x0100)
  47. #define BD_ENET_RX_BC ((ushort)0x0080)
  48. #define BD_ENET_RX_MC ((ushort)0x0040)
  49. #define BD_ENET_RX_LG ((ushort)0x0020)
  50. #define BD_ENET_RX_NO ((ushort)0x0010)
  51. #define BD_ENET_RX_SH ((ushort)0x0008)
  52. #define BD_ENET_RX_CR ((ushort)0x0004)
  53. #define BD_ENET_RX_OV ((ushort)0x0002)
  54. #define BD_ENET_RX_CL ((ushort)0x0001)
  55. #define BD_ENET_RX_TR BD_ENET_RX_CL
  56. #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
  57. /* Buffer descriptor control/status used by Ethernet transmit.
  58. */
  59. #define BD_ENET_TX_READY ((ushort)0x8000)
  60. #define BD_ENET_TX_PAD ((ushort)0x4000)
  61. #define BD_ENET_TX_TO1 BD_ENET_TX_PAD
  62. #define BD_ENET_TX_WRAP ((ushort)0x2000)
  63. #define BD_ENET_TX_INTR ((ushort)0x1000)
  64. #define BD_ENET_TX_TO2 BD_ENET_TX_INTR_
  65. #define BD_ENET_TX_LAST ((ushort)0x0800)
  66. #define BD_ENET_TX_TC ((ushort)0x0400)
  67. #define BD_ENET_TX_DEF ((ushort)0x0200)
  68. #define BD_ENET_TX_ABC BD_ENET_TX_DEF
  69. #define BD_ENET_TX_HB ((ushort)0x0100)
  70. #define BD_ENET_TX_LC ((ushort)0x0080)
  71. #define BD_ENET_TX_RL ((ushort)0x0040)
  72. #define BD_ENET_TX_RCMASK ((ushort)0x003c)
  73. #define BD_ENET_TX_UN ((ushort)0x0002)
  74. #define BD_ENET_TX_CSL ((ushort)0x0001)
  75. #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
  76. /*********************************************************************
  77. * Fast Ethernet Controller (FEC)
  78. *********************************************************************/
  79. /* FEC private information */
  80. struct fec_info_s {
  81. int index;
  82. u32 iobase;
  83. u32 pinmux;
  84. u32 miibase;
  85. int phy_addr;
  86. int dup_spd;
  87. char *phy_name;
  88. int phyname_init;
  89. cbd_t *rxbd; /* Rx BD */
  90. cbd_t *txbd; /* Tx BD */
  91. uint rx_idx;
  92. uint tx_idx;
  93. char *txbuf;
  94. int initialized;
  95. int to_loop;
  96. struct mii_dev *bus;
  97. };
  98. #ifdef CONFIG_MCFFEC
  99. /* Register read/write struct */
  100. typedef struct fec {
  101. #ifdef CONFIG_M5272
  102. u32 ecr; /* 0x00 */
  103. u32 eir; /* 0x04 */
  104. u32 eimr; /* 0x08 */
  105. u32 ivsr; /* 0x0C */
  106. u32 rdar; /* 0x10 */
  107. u32 tdar; /* 0x14 */
  108. u8 resv1[0x28]; /* 0x18 */
  109. u32 mmfr; /* 0x40 */
  110. u32 mscr; /* 0x44 */
  111. u8 resv2[0x44]; /* 0x48 */
  112. u32 frbr; /* 0x8C */
  113. u32 frsr; /* 0x90 */
  114. u8 resv3[0x10]; /* 0x94 */
  115. u32 tfwr; /* 0xA4 */
  116. u32 res4; /* 0xA8 */
  117. u32 tfsr; /* 0xAC */
  118. u8 resv4[0x50]; /* 0xB0 */
  119. u32 opd; /* 0x100 - dummy */
  120. u32 rcr; /* 0x104 */
  121. u32 mibc; /* 0x108 */
  122. u8 resv5[0x38]; /* 0x10C */
  123. u32 tcr; /* 0x144 */
  124. u8 resv6[0x270]; /* 0x148 */
  125. u32 iaur; /* 0x3B8 - dummy */
  126. u32 ialr; /* 0x3BC - dummy */
  127. u32 palr; /* 0x3C0 */
  128. u32 paur; /* 0x3C4 */
  129. u32 gaur; /* 0x3C8 */
  130. u32 galr; /* 0x3CC */
  131. u32 erdsr; /* 0x3D0 */
  132. u32 etdsr; /* 0x3D4 */
  133. u32 emrbr; /* 0x3D8 */
  134. u8 resv12[0x74]; /* 0x18C */
  135. #else
  136. u8 resv0[0x4];
  137. u32 eir;
  138. u32 eimr;
  139. u8 resv1[0x4];
  140. u32 rdar;
  141. u32 tdar;
  142. u8 resv2[0xC];
  143. u32 ecr;
  144. u8 resv3[0x18];
  145. u32 mmfr;
  146. u32 mscr;
  147. u8 resv4[0x1C];
  148. u32 mibc;
  149. u8 resv5[0x1C];
  150. u32 rcr;
  151. u8 resv6[0x3C];
  152. u32 tcr;
  153. u8 resv7[0x1C];
  154. u32 palr;
  155. u32 paur;
  156. u32 opd;
  157. u8 resv8[0x28];
  158. u32 iaur;
  159. u32 ialr;
  160. u32 gaur;
  161. u32 galr;
  162. u8 resv9[0x1C];
  163. u32 tfwr;
  164. u8 resv10[0x4];
  165. u32 frbr;
  166. u32 frsr;
  167. u8 resv11[0x2C];
  168. u32 erdsr;
  169. u32 etdsr;
  170. u32 emrbr;
  171. u8 resv12[0x74];
  172. #endif
  173. u32 rmon_t_drop;
  174. u32 rmon_t_packets;
  175. u32 rmon_t_bc_pkt;
  176. u32 rmon_t_mc_pkt;
  177. u32 rmon_t_crc_align;
  178. u32 rmon_t_undersize;
  179. u32 rmon_t_oversize;
  180. u32 rmon_t_frag;
  181. u32 rmon_t_jab;
  182. u32 rmon_t_col;
  183. u32 rmon_t_p64;
  184. u32 rmon_t_p65to127;
  185. u32 rmon_t_p128to255;
  186. u32 rmon_t_p256to511;
  187. u32 rmon_t_p512to1023;
  188. u32 rmon_t_p1024to2047;
  189. u32 rmon_t_p_gte2048;
  190. u32 rmon_t_octets;
  191. u32 ieee_t_drop;
  192. u32 ieee_t_frame_ok;
  193. u32 ieee_t_1col;
  194. u32 ieee_t_mcol;
  195. u32 ieee_t_def;
  196. u32 ieee_t_lcol;
  197. u32 ieee_t_excol;
  198. u32 ieee_t_macerr;
  199. u32 ieee_t_cserr;
  200. u32 ieee_t_sqe;
  201. u32 ieee_t_fdxfc;
  202. u32 ieee_t_octets_ok;
  203. u8 resv13[0x8];
  204. u32 rmon_r_drop;
  205. u32 rmon_r_packets;
  206. u32 rmon_r_bc_pkt;
  207. u32 rmon_r_mc_pkt;
  208. u32 rmon_r_crc_align;
  209. u32 rmon_r_undersize;
  210. u32 rmon_r_oversize;
  211. u32 rmon_r_frag;
  212. u32 rmon_r_jab;
  213. u32 rmon_r_resvd_0;
  214. u32 rmon_r_p64;
  215. u32 rmon_r_p65to127;
  216. u32 rmon_r_p128to255;
  217. u32 rmon_r_p256to511;
  218. u32 rmon_r_p512to1023;
  219. u32 rmon_r_p1024to2047;
  220. u32 rmon_r_p_gte2048;
  221. u32 rmon_r_octets;
  222. u32 ieee_r_drop;
  223. u32 ieee_r_frame_ok;
  224. u32 ieee_r_crc;
  225. u32 ieee_r_align;
  226. u32 ieee_r_macerr;
  227. u32 ieee_r_fdxfc;
  228. u32 ieee_r_octets_ok;
  229. } fec_t;
  230. #endif /* CONFIG_MCFFEC */
  231. /*********************************************************************
  232. * Fast Ethernet Controller (FEC)
  233. *********************************************************************/
  234. /* Bit definitions and macros for FEC_EIR */
  235. #define FEC_EIR_CLEAR_ALL (0xFFF80000)
  236. #define FEC_EIR_HBERR (0x80000000)
  237. #define FEC_EIR_BABR (0x40000000)
  238. #define FEC_EIR_BABT (0x20000000)
  239. #define FEC_EIR_GRA (0x10000000)
  240. #define FEC_EIR_TXF (0x08000000)
  241. #define FEC_EIR_TXB (0x04000000)
  242. #define FEC_EIR_RXF (0x02000000)
  243. #define FEC_EIR_RXB (0x01000000)
  244. #define FEC_EIR_MII (0x00800000)
  245. #define FEC_EIR_EBERR (0x00400000)
  246. #define FEC_EIR_LC (0x00200000)
  247. #define FEC_EIR_RL (0x00100000)
  248. #define FEC_EIR_UN (0x00080000)
  249. /* Bit definitions and macros for FEC_RDAR */
  250. #define FEC_RDAR_R_DES_ACTIVE (0x01000000)
  251. /* Bit definitions and macros for FEC_TDAR */
  252. #define FEC_TDAR_X_DES_ACTIVE (0x01000000)
  253. /* Bit definitions and macros for FEC_ECR */
  254. #define FEC_ECR_ETHER_EN (0x00000002)
  255. #define FEC_ECR_RESET (0x00000001)
  256. /* Bit definitions and macros for FEC_MMFR */
  257. #define FEC_MMFR_DATA(x) (((x)&0xFFFF))
  258. #define FEC_MMFR_ST(x) (((x)&0x03)<<30)
  259. #define FEC_MMFR_ST_01 (0x40000000)
  260. #define FEC_MMFR_OP_RD (0x20000000)
  261. #define FEC_MMFR_OP_WR (0x10000000)
  262. #define FEC_MMFR_PA(x) (((x)&0x1F)<<23)
  263. #define FEC_MMFR_RA(x) (((x)&0x1F)<<18)
  264. #define FEC_MMFR_TA(x) (((x)&0x03)<<16)
  265. #define FEC_MMFR_TA_10 (0x00020000)
  266. /* Bit definitions and macros for FEC_MSCR */
  267. #define FEC_MSCR_DIS_PREAMBLE (0x00000080)
  268. #define FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<1)
  269. /* Bit definitions and macros for FEC_MIBC */
  270. #define FEC_MIBC_MIB_DISABLE (0x80000000)
  271. #define FEC_MIBC_MIB_IDLE (0x40000000)
  272. /* Bit definitions and macros for FEC_RCR */
  273. #define FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<16)
  274. #define FEC_RCR_FCE (0x00000020)
  275. #define FEC_RCR_BC_REJ (0x00000010)
  276. #define FEC_RCR_PROM (0x00000008)
  277. #define FEC_RCR_MII_MODE (0x00000004)
  278. #define FEC_RCR_DRT (0x00000002)
  279. #define FEC_RCR_LOOP (0x00000001)
  280. /* Bit definitions and macros for FEC_TCR */
  281. #define FEC_TCR_RFC_PAUSE (0x00000010)
  282. #define FEC_TCR_TFC_PAUSE (0x00000008)
  283. #define FEC_TCR_FDEN (0x00000004)
  284. #define FEC_TCR_HBC (0x00000002)
  285. #define FEC_TCR_GTS (0x00000001)
  286. /* Bit definitions and macros for FEC_PAUR */
  287. #define FEC_PAUR_PADDR2(x) (((x)&0xFFFF)<<16)
  288. #define FEC_PAUR_TYPE(x) ((x)&0xFFFF)
  289. /* Bit definitions and macros for FEC_OPD */
  290. #define FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0)
  291. #define FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16)
  292. /* Bit definitions and macros for FEC_TFWR */
  293. #define FEC_TFWR_X_WMRK(x) ((x)&0x03)
  294. #define FEC_TFWR_X_WMRK_64 (0x01)
  295. #define FEC_TFWR_X_WMRK_128 (0x02)
  296. #define FEC_TFWR_X_WMRK_192 (0x03)
  297. /* Bit definitions and macros for FEC_FRBR */
  298. #define FEC_FRBR_R_BOUND(x) (((x)&0xFF)<<2)
  299. /* Bit definitions and macros for FEC_FRSR */
  300. #define FEC_FRSR_R_FSTART(x) (((x)&0xFF)<<2)
  301. /* Bit definitions and macros for FEC_ERDSR */
  302. #define FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2)
  303. /* Bit definitions and macros for FEC_ETDSR */
  304. #define FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2)
  305. /* Bit definitions and macros for FEC_EMRBR */
  306. #define FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x7F)<<4)
  307. #define FEC_RESET_DELAY 100
  308. #define FEC_RX_TOUT 100
  309. typedef struct fec_info_s fec_info_t;
  310. #define FEC_T fec_t
  311. int fecpin_setclear(fec_info_t *info, int setclear);
  312. int mii_discover_phy(fec_info_t *info);
  313. int fec_get_base_addr(int fec_idx, u32 *fec_iobase);
  314. int fec_get_mii_base(int fec_idx, u32 *mii_base);
  315. #ifdef CONFIG_SYS_DISCOVER_PHY
  316. void __mii_init(void);
  317. uint mii_send(uint mii_cmd);
  318. int mcffec_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg);
  319. int mcffec_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
  320. u16 value);
  321. #endif
  322. #endif /* fec_h */