eport.h 3.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Edge Port Memory Map
  4. *
  5. * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
  6. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  7. */
  8. #ifndef __EPORT_H__
  9. #define __EPORT_H__
  10. /* Edge Port Module (EPORT) */
  11. typedef struct eport {
  12. u16 par; /* 0x00 Pin Assignment */
  13. u8 ddr; /* 0x02 Data Direction */
  14. u8 ier; /* 0x03 Interrupt Enable */
  15. u8 dr; /* 0x04 Data */
  16. u8 pdr; /* 0x05 Pin Data */
  17. u8 fr; /* 0x06 Flag */
  18. u8 res0;
  19. } eport_t;
  20. /* EPPAR */
  21. #define EPORT_PAR_EPPA1(x) (((x)&0x0003)<<2)
  22. #define EPORT_PAR_EPPA2(x) (((x)&0x0003)<<4)
  23. #define EPORT_PAR_EPPA3(x) (((x)&0x0003)<<6)
  24. #define EPORT_PAR_EPPA4(x) (((x)&0x0003)<<8)
  25. #define EPORT_PAR_EPPA5(x) (((x)&0x0003)<<10)
  26. #define EPORT_PAR_EPPA6(x) (((x)&0x0003)<<12)
  27. #define EPORT_PAR_EPPA7(x) (((x)&0x0003)<<14)
  28. #define EPORT_PAR_LEVEL (0)
  29. #define EPORT_PAR_RISING (1)
  30. #define EPORT_PAR_FALLING (2)
  31. #define EPORT_PAR_BOTH (3)
  32. #define EPORT_PAR_EPPA7_LEVEL (0x0000)
  33. #define EPORT_PAR_EPPA7_RISING (0x4000)
  34. #define EPORT_PAR_EPPA7_FALLING (0x8000)
  35. #define EPORT_PAR_EPPA7_BOTH (0xC000)
  36. #define EPORT_PAR_EPPA6_LEVEL (0x0000)
  37. #define EPORT_PAR_EPPA6_RISING (0x1000)
  38. #define EPORT_PAR_EPPA6_FALLING (0x2000)
  39. #define EPORT_PAR_EPPA6_BOTH (0x3000)
  40. #define EPORT_PAR_EPPA5_LEVEL (0x0000)
  41. #define EPORT_PAR_EPPA5_RISING (0x0400)
  42. #define EPORT_PAR_EPPA5_FALLING (0x0800)
  43. #define EPORT_PAR_EPPA5_BOTH (0x0C00)
  44. #define EPORT_PAR_EPPA4_LEVEL (0x0000)
  45. #define EPORT_PAR_EPPA4_RISING (0x0100)
  46. #define EPORT_PAR_EPPA4_FALLING (0x0200)
  47. #define EPORT_PAR_EPPA4_BOTH (0x0300)
  48. #define EPORT_PAR_EPPA3_LEVEL (0x0000)
  49. #define EPORT_PAR_EPPA3_RISING (0x0040)
  50. #define EPORT_PAR_EPPA3_FALLING (0x0080)
  51. #define EPORT_PAR_EPPA3_BOTH (0x00C0)
  52. #define EPORT_PAR_EPPA2_LEVEL (0x0000)
  53. #define EPORT_PAR_EPPA2_RISING (0x0010)
  54. #define EPORT_PAR_EPPA2_FALLING (0x0020)
  55. #define EPORT_PAR_EPPA2_BOTH (0x0030)
  56. #define EPORT_PAR_EPPA1_LEVEL (0x0000)
  57. #define EPORT_PAR_EPPA1_RISING (0x0004)
  58. #define EPORT_PAR_EPPA1_FALLING (0x0008)
  59. #define EPORT_PAR_EPPA1_BOTH (0x000C)
  60. /* EPDDR */
  61. #define EPORT_DDR_EPDD1 (0x02)
  62. #define EPORT_DDR_EPDD2 (0x04)
  63. #define EPORT_DDR_EPDD3 (0x08)
  64. #define EPORT_DDR_EPDD4 (0x10)
  65. #define EPORT_DDR_EPDD5 (0x20)
  66. #define EPORT_DDR_EPDD6 (0x40)
  67. #define EPORT_DDR_EPDD7 (0x80)
  68. /* EPIER */
  69. #define EPORT_IER_EPIE1 (0x02)
  70. #define EPORT_IER_EPIE2 (0x04)
  71. #define EPORT_IER_EPIE3 (0x08)
  72. #define EPORT_IER_EPIE4 (0x10)
  73. #define EPORT_IER_EPIE5 (0x20)
  74. #define EPORT_IER_EPIE6 (0x40)
  75. #define EPORT_IER_EPIE7 (0x80)
  76. /* EPDR */
  77. #define EPORT_DR_EPD1 (0x02)
  78. #define EPORT_DR_EPD2 (0x04)
  79. #define EPORT_DR_EPD3 (0x08)
  80. #define EPORT_DR_EPD4 (0x10)
  81. #define EPORT_DR_EPD5 (0x20)
  82. #define EPORT_DR_EPD6 (0x40)
  83. #define EPORT_DR_EPD7 (0x80)
  84. /* EPPDR */
  85. #define EPORT_PDR_EPPD1 (0x02)
  86. #define EPORT_PDR_EPPD2 (0x04)
  87. #define EPORT_PDR_EPPD3 (0x08)
  88. #define EPORT_PDR_EPPD4 (0x10)
  89. #define EPORT_PDR_EPPD5 (0x20)
  90. #define EPORT_PDR_EPPD6 (0x40)
  91. #define EPORT_PDR_EPPD7 (0x80)
  92. /* EPFR */
  93. #define EPORT_FR_EPF1 (0x02)
  94. #define EPORT_FR_EPF2 (0x04)
  95. #define EPORT_FR_EPF3 (0x08)
  96. #define EPORT_FR_EPF4 (0x10)
  97. #define EPORT_FR_EPF5 (0x20)
  98. #define EPORT_FR_EPF6 (0x40)
  99. #define EPORT_FR_EPF7 (0x80)
  100. #endif /* __EPORT_H__ */