dspi.h 4.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * MCF5227x Internal Memory Map
  4. *
  5. * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  6. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  7. */
  8. #ifndef __DSPI_H__
  9. #define __DSPI_H__
  10. /* DMA Serial Peripheral Interface (DSPI) */
  11. typedef struct dspi {
  12. u32 mcr; /* 0x00 */
  13. u32 resv0; /* 0x04 */
  14. u32 tcr; /* 0x08 */
  15. u32 ctar[8]; /* 0x0C - 0x28 */
  16. u32 sr; /* 0x2C */
  17. u32 irsr; /* 0x30 */
  18. u32 tfr; /* 0x34 - PUSHR */
  19. u16 resv1; /* 0x38 */
  20. u16 rfr; /* 0x3A - POPR */
  21. u32 tfdr[16]; /* 0x3C */
  22. u32 rfdr[16]; /* 0x7C */
  23. } dspi_t;
  24. /* Module configuration */
  25. #define DSPI_MCR_MSTR (0x80000000)
  26. #define DSPI_MCR_CSCK (0x40000000)
  27. #define DSPI_MCR_DCONF(x) (((x)&0x03)<<28)
  28. #define DSPI_MCR_FRZ (0x08000000)
  29. #define DSPI_MCR_MTFE (0x04000000)
  30. #define DSPI_MCR_PCSSE (0x02000000)
  31. #define DSPI_MCR_ROOE (0x01000000)
  32. #define DSPI_MCR_CSIS7 (0x00800000)
  33. #define DSPI_MCR_CSIS6 (0x00400000)
  34. #define DSPI_MCR_CSIS5 (0x00200000)
  35. #define DSPI_MCR_CSIS4 (0x00100000)
  36. #define DSPI_MCR_CSIS3 (0x00080000)
  37. #define DSPI_MCR_CSIS2 (0x00040000)
  38. #define DSPI_MCR_CSIS1 (0x00020000)
  39. #define DSPI_MCR_CSIS0 (0x00010000)
  40. #define DSPI_MCR_MDIS (0x00004000)
  41. #define DSPI_MCR_DTXF (0x00002000)
  42. #define DSPI_MCR_DRXF (0x00001000)
  43. #define DSPI_MCR_CTXF (0x00000800)
  44. #define DSPI_MCR_CRXF (0x00000400)
  45. #define DSPI_MCR_SMPL_PT(x) (((x)&0x03)<<8)
  46. #define DSPI_MCR_HALT (0x00000001)
  47. /* Transfer count */
  48. #define DSPI_TCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16)
  49. /* Clock and transfer attributes */
  50. #define DSPI_CTAR_DBR (0x80000000)
  51. #define DSPI_CTAR_TRSZ(x) (((x)&0x0F)<<27)
  52. #define DSPI_CTAR_CPOL (0x04000000)
  53. #define DSPI_CTAR_CPHA (0x02000000)
  54. #define DSPI_CTAR_LSBFE (0x01000000)
  55. #define DSPI_CTAR_PCSSCK(x) (((x)&0x03)<<22)
  56. #define DSPI_CTAR_PCSSCK_7CLK (0x00A00000)
  57. #define DSPI_CTAR_PCSSCK_5CLK (0x00800000)
  58. #define DSPI_CTAR_PCSSCK_3CLK (0x00400000)
  59. #define DSPI_CTAR_PCSSCK_1CLK (0x00000000)
  60. #define DSPI_CTAR_PASC(x) (((x)&0x03)<<20)
  61. #define DSPI_CTAR_PASC_7CLK (0x00300000)
  62. #define DSPI_CTAR_PASC_5CLK (0x00200000)
  63. #define DSPI_CTAR_PASC_3CLK (0x00100000)
  64. #define DSPI_CTAR_PASC_1CLK (0x00000000)
  65. #define DSPI_CTAR_PDT(x) (((x)&0x03)<<18)
  66. #define DSPI_CTAR_PDT_7CLK (0x000A0000)
  67. #define DSPI_CTAR_PDT_5CLK (0x00080000)
  68. #define DSPI_CTAR_PDT_3CLK (0x00040000)
  69. #define DSPI_CTAR_PDT_1CLK (0x00000000)
  70. #define DSPI_CTAR_PBR(x) (((x)&0x03)<<16)
  71. #define DSPI_CTAR_PBR_7CLK (0x00030000)
  72. #define DSPI_CTAR_PBR_5CLK (0x00020000)
  73. #define DSPI_CTAR_PBR_3CLK (0x00010000)
  74. #define DSPI_CTAR_PBR_1CLK (0x00000000)
  75. #define DSPI_CTAR_CSSCK(x) (((x)&0x0F)<<12)
  76. #define DSPI_CTAR_ASC(x) (((x)&0x0F)<<8)
  77. #define DSPI_CTAR_DT(x) (((x)&0x0F)<<4)
  78. #define DSPI_CTAR_BR(x) (((x)&0x0F))
  79. /* Status */
  80. #define DSPI_SR_TCF (0x80000000)
  81. #define DSPI_SR_TXRXS (0x40000000)
  82. #define DSPI_SR_EOQF (0x10000000)
  83. #define DSPI_SR_TFUF (0x08000000)
  84. #define DSPI_SR_TFFF (0x02000000)
  85. #define DSPI_SR_RFOF (0x00080000)
  86. #define DSPI_SR_RFDF (0x00020000)
  87. #define DSPI_SR_TXCTR(x) (((x)&0x0F)<<12)
  88. #define DSPI_SR_TXPTR(x) (((x)&0x0F)<<8)
  89. #define DSPI_SR_RXCTR(x) (((x)&0x0F)<<4)
  90. #define DSPI_SR_RXPTR(x) (((x)&0x0F))
  91. /* DMA/interrupt request selct and enable */
  92. #define DSPI_IRSR_TCFE (0x80000000)
  93. #define DSPI_IRSR_EOQFE (0x10000000)
  94. #define DSPI_IRSR_TFUFE (0x08000000)
  95. #define DSPI_IRSR_TFFFE (0x02000000)
  96. #define DSPI_IRSR_TFFFS (0x01000000)
  97. #define DSPI_IRSR_RFOFE (0x00080000)
  98. #define DSPI_IRSR_RFDFE (0x00020000)
  99. #define DSPI_IRSR_RFDFS (0x00010000)
  100. /* Transfer control - 32-bit access */
  101. #define DSPI_TFR_CONT (0x80000000)
  102. #define DSPI_TFR_CTAS(x) (((x)&0x07)<<12)
  103. #define DSPI_TFR_EOQ (0x08000000)
  104. #define DSPI_TFR_CTCNT (0x04000000)
  105. #define DSPI_TFR_CS7 (0x00800000)
  106. #define DSPI_TFR_CS6 (0x00400000)
  107. #define DSPI_TFR_CS5 (0x00200000)
  108. #define DSPI_TFR_CS4 (0x00100000)
  109. #define DSPI_TFR_CS3 (0x00080000)
  110. #define DSPI_TFR_CS2 (0x00040000)
  111. #define DSPI_TFR_CS1 (0x00020000)
  112. #define DSPI_TFR_CS0 (0x00010000)
  113. /* Transfer Fifo */
  114. #define DSPI_TFR_TXDATA(x) (((x)&0xFFFF))
  115. /* Bit definitions and macros for DRFR */
  116. #define DSPI_RFR_RXDATA(x) (((x)&0xFFFF))
  117. /* Bit definitions and macros for DTFDR group */
  118. #define DSPI_TFDR_TXDATA(x) (((x)&0x0000FFFF))
  119. #define DSPI_TFDR_TXCMD(x) (((x)&0x0000FFFF)<<16)
  120. /* Bit definitions and macros for DRFDR group */
  121. #define DSPI_RFDR_RXDATA(x) (((x)&0x0000FFFF))
  122. /* Architecture-related operations */
  123. void dspi_chip_select(int cs);
  124. void dspi_chip_unselect(int cs);
  125. #endif /* __DSPI_H__ */