clk-uclass.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Google, Inc
  4. * Written by Simon Glass <sjg@chromium.org>
  5. * Copyright (c) 2016, NVIDIA CORPORATION.
  6. * Copyright (c) 2018, Theobroma Systems Design und Consulting GmbH
  7. */
  8. #include <common.h>
  9. #include <clk.h>
  10. #include <clk-uclass.h>
  11. #include <dm.h>
  12. #include <dt-structs.h>
  13. #include <errno.h>
  14. #include <log.h>
  15. #include <malloc.h>
  16. #include <dm/device-internal.h>
  17. #include <dm/devres.h>
  18. #include <dm/read.h>
  19. #include <linux/bug.h>
  20. #include <linux/clk-provider.h>
  21. #include <linux/err.h>
  22. static inline const struct clk_ops *clk_dev_ops(struct udevice *dev)
  23. {
  24. return (const struct clk_ops *)dev->driver->ops;
  25. }
  26. struct clk *dev_get_clk_ptr(struct udevice *dev)
  27. {
  28. return (struct clk *)dev_get_uclass_priv(dev);
  29. }
  30. #if CONFIG_IS_ENABLED(OF_CONTROL)
  31. # if CONFIG_IS_ENABLED(OF_PLATDATA)
  32. int clk_get_by_driver_info(struct udevice *dev, struct phandle_1_arg *cells,
  33. struct clk *clk)
  34. {
  35. int ret;
  36. ret = device_get_by_driver_info((struct driver_info *)cells->node,
  37. &clk->dev);
  38. if (ret)
  39. return ret;
  40. clk->id = cells->arg[0];
  41. return 0;
  42. }
  43. # else
  44. static int clk_of_xlate_default(struct clk *clk,
  45. struct ofnode_phandle_args *args)
  46. {
  47. debug("%s(clk=%p)\n", __func__, clk);
  48. if (args->args_count > 1) {
  49. debug("Invaild args_count: %d\n", args->args_count);
  50. return -EINVAL;
  51. }
  52. if (args->args_count)
  53. clk->id = args->args[0];
  54. else
  55. clk->id = 0;
  56. clk->data = 0;
  57. return 0;
  58. }
  59. static int clk_get_by_index_tail(int ret, ofnode node,
  60. struct ofnode_phandle_args *args,
  61. const char *list_name, int index,
  62. struct clk *clk)
  63. {
  64. struct udevice *dev_clk;
  65. const struct clk_ops *ops;
  66. assert(clk);
  67. clk->dev = NULL;
  68. if (ret)
  69. goto err;
  70. ret = uclass_get_device_by_ofnode(UCLASS_CLK, args->node, &dev_clk);
  71. if (ret) {
  72. debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
  73. __func__, ret);
  74. return ret;
  75. }
  76. clk->dev = dev_clk;
  77. ops = clk_dev_ops(dev_clk);
  78. if (ops->of_xlate)
  79. ret = ops->of_xlate(clk, args);
  80. else
  81. ret = clk_of_xlate_default(clk, args);
  82. if (ret) {
  83. debug("of_xlate() failed: %d\n", ret);
  84. return ret;
  85. }
  86. return clk_request(dev_clk, clk);
  87. err:
  88. debug("%s: Node '%s', property '%s', failed to request CLK index %d: %d\n",
  89. __func__, ofnode_get_name(node), list_name, index, ret);
  90. return ret;
  91. }
  92. static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name,
  93. int index, struct clk *clk)
  94. {
  95. int ret;
  96. struct ofnode_phandle_args args;
  97. debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
  98. assert(clk);
  99. clk->dev = NULL;
  100. ret = dev_read_phandle_with_args(dev, prop_name, "#clock-cells", 0,
  101. index, &args);
  102. if (ret) {
  103. debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
  104. __func__, ret);
  105. return ret;
  106. }
  107. return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks",
  108. index, clk);
  109. }
  110. int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
  111. {
  112. struct ofnode_phandle_args args;
  113. int ret;
  114. ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
  115. index, &args);
  116. return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks",
  117. index, clk);
  118. }
  119. int clk_get_by_index_nodev(ofnode node, int index, struct clk *clk)
  120. {
  121. struct ofnode_phandle_args args;
  122. int ret;
  123. ret = ofnode_parse_phandle_with_args(node, "clocks", "#clock-cells", 0,
  124. index, &args);
  125. return clk_get_by_index_tail(ret, node, &args, "clocks",
  126. index, clk);
  127. }
  128. int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
  129. {
  130. int i, ret, err, count;
  131. bulk->count = 0;
  132. count = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
  133. if (count < 1)
  134. return count;
  135. bulk->clks = devm_kcalloc(dev, count, sizeof(struct clk), GFP_KERNEL);
  136. if (!bulk->clks)
  137. return -ENOMEM;
  138. for (i = 0; i < count; i++) {
  139. ret = clk_get_by_index(dev, i, &bulk->clks[i]);
  140. if (ret < 0)
  141. goto bulk_get_err;
  142. ++bulk->count;
  143. }
  144. return 0;
  145. bulk_get_err:
  146. err = clk_release_all(bulk->clks, bulk->count);
  147. if (err)
  148. debug("%s: could release all clocks for %p\n",
  149. __func__, dev);
  150. return ret;
  151. }
  152. static int clk_set_default_parents(struct udevice *dev, int stage)
  153. {
  154. struct clk clk, parent_clk;
  155. int index;
  156. int num_parents;
  157. int ret;
  158. num_parents = dev_count_phandle_with_args(dev, "assigned-clock-parents",
  159. "#clock-cells");
  160. if (num_parents < 0) {
  161. debug("%s: could not read assigned-clock-parents for %p\n",
  162. __func__, dev);
  163. return 0;
  164. }
  165. for (index = 0; index < num_parents; index++) {
  166. ret = clk_get_by_indexed_prop(dev, "assigned-clock-parents",
  167. index, &parent_clk);
  168. /* If -ENOENT, this is a no-op entry */
  169. if (ret == -ENOENT)
  170. continue;
  171. if (ret) {
  172. debug("%s: could not get parent clock %d for %s\n",
  173. __func__, index, dev_read_name(dev));
  174. return ret;
  175. }
  176. ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
  177. index, &clk);
  178. if (ret) {
  179. debug("%s: could not get assigned clock %d for %s\n",
  180. __func__, index, dev_read_name(dev));
  181. return ret;
  182. }
  183. /* This is clk provider device trying to reparent itself
  184. * It cannot be done right now but need to wait after the
  185. * device is probed
  186. */
  187. if (stage == 0 && clk.dev == dev)
  188. continue;
  189. if (stage > 0 && clk.dev != dev)
  190. /* do not setup twice the parent clocks */
  191. continue;
  192. ret = clk_set_parent(&clk, &parent_clk);
  193. /*
  194. * Not all drivers may support clock-reparenting (as of now).
  195. * Ignore errors due to this.
  196. */
  197. if (ret == -ENOSYS)
  198. continue;
  199. if (ret < 0) {
  200. debug("%s: failed to reparent clock %d for %s\n",
  201. __func__, index, dev_read_name(dev));
  202. return ret;
  203. }
  204. }
  205. return 0;
  206. }
  207. static int clk_set_default_rates(struct udevice *dev, int stage)
  208. {
  209. struct clk clk;
  210. int index;
  211. int num_rates;
  212. int size;
  213. int ret = 0;
  214. u32 *rates = NULL;
  215. size = dev_read_size(dev, "assigned-clock-rates");
  216. if (size < 0)
  217. return 0;
  218. num_rates = size / sizeof(u32);
  219. rates = calloc(num_rates, sizeof(u32));
  220. if (!rates)
  221. return -ENOMEM;
  222. ret = dev_read_u32_array(dev, "assigned-clock-rates", rates, num_rates);
  223. if (ret)
  224. goto fail;
  225. for (index = 0; index < num_rates; index++) {
  226. /* If 0 is passed, this is a no-op */
  227. if (!rates[index])
  228. continue;
  229. ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
  230. index, &clk);
  231. if (ret) {
  232. debug("%s: could not get assigned clock %d for %s\n",
  233. __func__, index, dev_read_name(dev));
  234. continue;
  235. }
  236. /* This is clk provider device trying to program itself
  237. * It cannot be done right now but need to wait after the
  238. * device is probed
  239. */
  240. if (stage == 0 && clk.dev == dev)
  241. continue;
  242. if (stage > 0 && clk.dev != dev)
  243. /* do not setup twice the parent clocks */
  244. continue;
  245. ret = clk_set_rate(&clk, rates[index]);
  246. if (ret < 0) {
  247. debug("%s: failed to set rate on clock index %d (%ld) for %s\n",
  248. __func__, index, clk.id, dev_read_name(dev));
  249. break;
  250. }
  251. }
  252. fail:
  253. free(rates);
  254. return ret;
  255. }
  256. int clk_set_defaults(struct udevice *dev, int stage)
  257. {
  258. int ret;
  259. if (!dev_of_valid(dev))
  260. return 0;
  261. /* If this not in SPL and pre-reloc state, don't take any action. */
  262. if (!(IS_ENABLED(CONFIG_SPL_BUILD) || (gd->flags & GD_FLG_RELOC)))
  263. return 0;
  264. debug("%s(%s)\n", __func__, dev_read_name(dev));
  265. ret = clk_set_default_parents(dev, stage);
  266. if (ret)
  267. return ret;
  268. ret = clk_set_default_rates(dev, stage);
  269. if (ret < 0)
  270. return ret;
  271. return 0;
  272. }
  273. int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
  274. {
  275. int index;
  276. debug("%s(dev=%p, name=%s, clk=%p)\n", __func__, dev, name, clk);
  277. clk->dev = NULL;
  278. index = dev_read_stringlist_search(dev, "clock-names", name);
  279. if (index < 0) {
  280. debug("fdt_stringlist_search() failed: %d\n", index);
  281. return index;
  282. }
  283. return clk_get_by_index(dev, index, clk);
  284. }
  285. # endif /* OF_PLATDATA */
  286. int clk_get_by_name_nodev(ofnode node, const char *name, struct clk *clk)
  287. {
  288. int index;
  289. debug("%s(node=%p, name=%s, clk=%p)\n", __func__,
  290. ofnode_get_name(node), name, clk);
  291. clk->dev = NULL;
  292. index = ofnode_stringlist_search(node, "clock-names", name);
  293. if (index < 0) {
  294. debug("fdt_stringlist_search() failed: %d\n", index);
  295. return index;
  296. }
  297. return clk_get_by_index_nodev(node, index, clk);
  298. }
  299. int clk_get_optional_nodev(ofnode node, const char *name, struct clk *clk)
  300. {
  301. int ret;
  302. ret = clk_get_by_name_nodev(node, name, clk);
  303. if (ret == -ENODATA)
  304. return 0;
  305. return ret;
  306. }
  307. int clk_release_all(struct clk *clk, int count)
  308. {
  309. int i, ret;
  310. for (i = 0; i < count; i++) {
  311. debug("%s(clk[%d]=%p)\n", __func__, i, &clk[i]);
  312. /* check if clock has been previously requested */
  313. if (!clk[i].dev)
  314. continue;
  315. ret = clk_disable(&clk[i]);
  316. if (ret && ret != -ENOSYS)
  317. return ret;
  318. ret = clk_free(&clk[i]);
  319. if (ret && ret != -ENOSYS)
  320. return ret;
  321. }
  322. return 0;
  323. }
  324. #endif /* OF_CONTROL */
  325. int clk_request(struct udevice *dev, struct clk *clk)
  326. {
  327. const struct clk_ops *ops;
  328. debug("%s(dev=%p, clk=%p)\n", __func__, dev, clk);
  329. if (!clk)
  330. return 0;
  331. ops = clk_dev_ops(dev);
  332. clk->dev = dev;
  333. if (!ops->request)
  334. return 0;
  335. return ops->request(clk);
  336. }
  337. int clk_free(struct clk *clk)
  338. {
  339. const struct clk_ops *ops;
  340. debug("%s(clk=%p)\n", __func__, clk);
  341. if (!clk_valid(clk))
  342. return 0;
  343. ops = clk_dev_ops(clk->dev);
  344. if (!ops->rfree)
  345. return 0;
  346. return ops->rfree(clk);
  347. }
  348. ulong clk_get_rate(struct clk *clk)
  349. {
  350. const struct clk_ops *ops;
  351. debug("%s(clk=%p)\n", __func__, clk);
  352. if (!clk_valid(clk))
  353. return 0;
  354. ops = clk_dev_ops(clk->dev);
  355. if (!ops->get_rate)
  356. return -ENOSYS;
  357. return ops->get_rate(clk);
  358. }
  359. struct clk *clk_get_parent(struct clk *clk)
  360. {
  361. struct udevice *pdev;
  362. struct clk *pclk;
  363. debug("%s(clk=%p)\n", __func__, clk);
  364. if (!clk_valid(clk))
  365. return NULL;
  366. pdev = dev_get_parent(clk->dev);
  367. pclk = dev_get_clk_ptr(pdev);
  368. if (!pclk)
  369. return ERR_PTR(-ENODEV);
  370. return pclk;
  371. }
  372. long long clk_get_parent_rate(struct clk *clk)
  373. {
  374. const struct clk_ops *ops;
  375. struct clk *pclk;
  376. debug("%s(clk=%p)\n", __func__, clk);
  377. if (!clk_valid(clk))
  378. return 0;
  379. pclk = clk_get_parent(clk);
  380. if (IS_ERR(pclk))
  381. return -ENODEV;
  382. ops = clk_dev_ops(pclk->dev);
  383. if (!ops->get_rate)
  384. return -ENOSYS;
  385. /* Read the 'rate' if not already set or if proper flag set*/
  386. if (!pclk->rate || pclk->flags & CLK_GET_RATE_NOCACHE)
  387. pclk->rate = clk_get_rate(pclk);
  388. return pclk->rate;
  389. }
  390. ulong clk_set_rate(struct clk *clk, ulong rate)
  391. {
  392. const struct clk_ops *ops;
  393. debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
  394. if (!clk_valid(clk))
  395. return 0;
  396. ops = clk_dev_ops(clk->dev);
  397. if (!ops->set_rate)
  398. return -ENOSYS;
  399. return ops->set_rate(clk, rate);
  400. }
  401. int clk_set_parent(struct clk *clk, struct clk *parent)
  402. {
  403. const struct clk_ops *ops;
  404. int ret;
  405. debug("%s(clk=%p, parent=%p)\n", __func__, clk, parent);
  406. if (!clk_valid(clk))
  407. return 0;
  408. ops = clk_dev_ops(clk->dev);
  409. if (!ops->set_parent)
  410. return -ENOSYS;
  411. ret = ops->set_parent(clk, parent);
  412. if (ret)
  413. return ret;
  414. if (CONFIG_IS_ENABLED(CLK_CCF))
  415. ret = device_reparent(clk->dev, parent->dev);
  416. return ret;
  417. }
  418. int clk_enable(struct clk *clk)
  419. {
  420. const struct clk_ops *ops;
  421. struct clk *clkp = NULL;
  422. int ret;
  423. debug("%s(clk=%p)\n", __func__, clk);
  424. if (!clk_valid(clk))
  425. return 0;
  426. ops = clk_dev_ops(clk->dev);
  427. if (CONFIG_IS_ENABLED(CLK_CCF)) {
  428. /* Take id 0 as a non-valid clk, such as dummy */
  429. if (clk->id && !clk_get_by_id(clk->id, &clkp)) {
  430. if (clkp->enable_count) {
  431. clkp->enable_count++;
  432. return 0;
  433. }
  434. if (clkp->dev->parent &&
  435. device_get_uclass_id(clkp->dev) == UCLASS_CLK) {
  436. ret = clk_enable(dev_get_clk_ptr(clkp->dev->parent));
  437. if (ret) {
  438. printf("Enable %s failed\n",
  439. clkp->dev->parent->name);
  440. return ret;
  441. }
  442. }
  443. }
  444. if (ops->enable) {
  445. ret = ops->enable(clk);
  446. if (ret) {
  447. printf("Enable %s failed\n", clk->dev->name);
  448. return ret;
  449. }
  450. }
  451. if (clkp)
  452. clkp->enable_count++;
  453. } else {
  454. if (!ops->enable)
  455. return -ENOSYS;
  456. return ops->enable(clk);
  457. }
  458. return 0;
  459. }
  460. int clk_enable_bulk(struct clk_bulk *bulk)
  461. {
  462. int i, ret;
  463. for (i = 0; i < bulk->count; i++) {
  464. ret = clk_enable(&bulk->clks[i]);
  465. if (ret < 0 && ret != -ENOSYS)
  466. return ret;
  467. }
  468. return 0;
  469. }
  470. int clk_disable(struct clk *clk)
  471. {
  472. const struct clk_ops *ops;
  473. struct clk *clkp = NULL;
  474. int ret;
  475. debug("%s(clk=%p)\n", __func__, clk);
  476. if (!clk_valid(clk))
  477. return 0;
  478. ops = clk_dev_ops(clk->dev);
  479. if (CONFIG_IS_ENABLED(CLK_CCF)) {
  480. if (clk->id && !clk_get_by_id(clk->id, &clkp)) {
  481. if (clkp->flags & CLK_IS_CRITICAL)
  482. return 0;
  483. if (clkp->enable_count == 0) {
  484. printf("clk %s already disabled\n",
  485. clkp->dev->name);
  486. return 0;
  487. }
  488. if (--clkp->enable_count > 0)
  489. return 0;
  490. }
  491. if (ops->disable) {
  492. ret = ops->disable(clk);
  493. if (ret)
  494. return ret;
  495. }
  496. if (clkp && clkp->dev->parent &&
  497. device_get_uclass_id(clkp->dev) == UCLASS_CLK) {
  498. ret = clk_disable(dev_get_clk_ptr(clkp->dev->parent));
  499. if (ret) {
  500. printf("Disable %s failed\n",
  501. clkp->dev->parent->name);
  502. return ret;
  503. }
  504. }
  505. } else {
  506. if (!ops->disable)
  507. return -ENOSYS;
  508. return ops->disable(clk);
  509. }
  510. return 0;
  511. }
  512. int clk_disable_bulk(struct clk_bulk *bulk)
  513. {
  514. int i, ret;
  515. for (i = 0; i < bulk->count; i++) {
  516. ret = clk_disable(&bulk->clks[i]);
  517. if (ret < 0 && ret != -ENOSYS)
  518. return ret;
  519. }
  520. return 0;
  521. }
  522. int clk_get_by_id(ulong id, struct clk **clkp)
  523. {
  524. struct udevice *dev;
  525. struct uclass *uc;
  526. int ret;
  527. ret = uclass_get(UCLASS_CLK, &uc);
  528. if (ret)
  529. return ret;
  530. uclass_foreach_dev(dev, uc) {
  531. struct clk *clk = dev_get_clk_ptr(dev);
  532. if (clk && clk->id == id) {
  533. *clkp = clk;
  534. return 0;
  535. }
  536. }
  537. return -ENOENT;
  538. }
  539. bool clk_is_match(const struct clk *p, const struct clk *q)
  540. {
  541. /* trivial case: identical struct clk's or both NULL */
  542. if (p == q)
  543. return true;
  544. /* trivial case #2: on the clk pointer is NULL */
  545. if (!p || !q)
  546. return false;
  547. /* same device, id and data */
  548. if (p->dev == q->dev && p->id == q->id && p->data == q->data)
  549. return true;
  550. return false;
  551. }
  552. static void devm_clk_release(struct udevice *dev, void *res)
  553. {
  554. clk_free(res);
  555. }
  556. static int devm_clk_match(struct udevice *dev, void *res, void *data)
  557. {
  558. return res == data;
  559. }
  560. struct clk *devm_clk_get(struct udevice *dev, const char *id)
  561. {
  562. int rc;
  563. struct clk *clk;
  564. clk = devres_alloc(devm_clk_release, sizeof(struct clk), __GFP_ZERO);
  565. if (unlikely(!clk))
  566. return ERR_PTR(-ENOMEM);
  567. rc = clk_get_by_name(dev, id, clk);
  568. if (rc)
  569. return ERR_PTR(rc);
  570. devres_add(dev, clk);
  571. return clk;
  572. }
  573. struct clk *devm_clk_get_optional(struct udevice *dev, const char *id)
  574. {
  575. struct clk *clk = devm_clk_get(dev, id);
  576. if (PTR_ERR(clk) == -ENODATA)
  577. return NULL;
  578. return clk;
  579. }
  580. void devm_clk_put(struct udevice *dev, struct clk *clk)
  581. {
  582. int rc;
  583. if (!clk)
  584. return;
  585. rc = devres_release(dev, devm_clk_release, devm_clk_match, clk);
  586. WARN_ON(rc);
  587. }
  588. int clk_uclass_post_probe(struct udevice *dev)
  589. {
  590. /*
  591. * when a clock provider is probed. Call clk_set_defaults()
  592. * also after the device is probed. This takes care of cases
  593. * where the DT is used to setup default parents and rates
  594. * using assigned-clocks
  595. */
  596. clk_set_defaults(dev, 1);
  597. return 0;
  598. }
  599. UCLASS_DRIVER(clk) = {
  600. .id = UCLASS_CLK,
  601. .name = "clk",
  602. .post_probe = clk_uclass_post_probe,
  603. };