Kconfig 6.2 KB

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  1. if ARCH_SOCFPGA
  2. config ERR_PTR_OFFSET
  3. default 0xfffec000 if TARGET_SOCFPGA_GEN5 # Boot ROM range
  4. config NR_DRAM_BANKS
  5. default 1
  6. config SPL_SIZE_LIMIT
  7. default 0x10000 if TARGET_SOCFPGA_GEN5
  8. config SPL_SIZE_LIMIT_PROVIDE_STACK
  9. default 0x200 if TARGET_SOCFPGA_GEN5
  10. config SPL_STACK_R_ADDR
  11. default 0x00800000 if TARGET_SOCFPGA_GEN5
  12. config SPL_SYS_MALLOC_F_LEN
  13. default 0x800 if TARGET_SOCFPGA_GEN5
  14. config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
  15. default 0xa2
  16. config SYS_MALLOC_F_LEN
  17. default 0x2000 if TARGET_SOCFPGA_ARRIA10
  18. default 0x2000 if TARGET_SOCFPGA_GEN5
  19. config SYS_TEXT_BASE
  20. default 0x01000040 if TARGET_SOCFPGA_ARRIA10
  21. default 0x01000040 if TARGET_SOCFPGA_GEN5
  22. config TARGET_SOCFPGA_AGILEX
  23. bool
  24. select ARMV8_MULTIENTRY
  25. select ARMV8_SET_SMPEN
  26. select BINMAN if SPL_ATF
  27. select CLK
  28. select FPGA_INTEL_SDM_MAILBOX
  29. select NCORE_CACHE
  30. select SPL_CLK if SPL
  31. select TARGET_SOCFPGA_SOC64
  32. config TARGET_SOCFPGA_ARRIA5
  33. bool
  34. select TARGET_SOCFPGA_GEN5
  35. config TARGET_SOCFPGA_ARRIA10
  36. bool
  37. select SPL_ALTERA_SDRAM
  38. select SPL_BOARD_INIT if SPL
  39. select SPL_CACHE if SPL
  40. select CLK
  41. select SPL_CLK if SPL
  42. select DM_I2C
  43. select DM_RESET
  44. select SPL_DM_RESET if SPL
  45. select REGMAP
  46. select SPL_REGMAP if SPL
  47. select SYSCON
  48. select SPL_SYSCON if SPL
  49. select ETH_DESIGNWARE_SOCFPGA
  50. imply FPGA_SOCFPGA
  51. imply SPL_USE_TINY_PRINTF
  52. config TARGET_SOCFPGA_CYCLONE5
  53. bool
  54. select TARGET_SOCFPGA_GEN5
  55. config TARGET_SOCFPGA_GEN5
  56. bool
  57. select SPL_ALTERA_SDRAM
  58. imply FPGA_SOCFPGA
  59. imply SPL_SIZE_LIMIT_SUBTRACT_GD
  60. imply SPL_SIZE_LIMIT_SUBTRACT_MALLOC
  61. imply SPL_STACK_R
  62. imply SPL_SYS_MALLOC_SIMPLE
  63. imply SPL_USE_TINY_PRINTF
  64. config TARGET_SOCFPGA_SOC64
  65. bool
  66. config TARGET_SOCFPGA_STRATIX10
  67. bool
  68. select ARMV8_MULTIENTRY
  69. select ARMV8_SET_SMPEN
  70. select BINMAN if SPL_ATF
  71. select FPGA_INTEL_SDM_MAILBOX
  72. select TARGET_SOCFPGA_SOC64
  73. choice
  74. prompt "Altera SOCFPGA board select"
  75. optional
  76. config TARGET_SOCFPGA_AGILEX_SOCDK
  77. bool "Intel SOCFPGA SoCDK (Agilex)"
  78. select TARGET_SOCFPGA_AGILEX
  79. config TARGET_SOCFPGA_ARIES_MCVEVK
  80. bool "Aries MCVEVK (Cyclone V)"
  81. select TARGET_SOCFPGA_CYCLONE5
  82. config TARGET_SOCFPGA_ARRIA10_SOCDK
  83. bool "Altera SOCFPGA SoCDK (Arria 10)"
  84. select TARGET_SOCFPGA_ARRIA10
  85. config TARGET_SOCFPGA_ARRIA5_SECU1
  86. bool "ABB SECU1 (Arria V)"
  87. select TARGET_SOCFPGA_ARRIA5
  88. select VENDOR_KM
  89. config TARGET_SOCFPGA_ARRIA5_SOCDK
  90. bool "Altera SOCFPGA SoCDK (Arria V)"
  91. select TARGET_SOCFPGA_ARRIA5
  92. config TARGET_SOCFPGA_CYCLONE5_SOCDK
  93. bool "Altera SOCFPGA SoCDK (Cyclone V)"
  94. select TARGET_SOCFPGA_CYCLONE5
  95. config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
  96. bool "Devboards DBM-SoC1 (Cyclone V)"
  97. select TARGET_SOCFPGA_CYCLONE5
  98. config TARGET_SOCFPGA_EBV_SOCRATES
  99. bool "EBV SoCrates (Cyclone V)"
  100. select TARGET_SOCFPGA_CYCLONE5
  101. config TARGET_SOCFPGA_IS1
  102. bool "IS1 (Cyclone V)"
  103. select TARGET_SOCFPGA_CYCLONE5
  104. config TARGET_SOCFPGA_SOFTING_VINING_FPGA
  105. bool "Softing VIN|ING FPGA (Cyclone V)"
  106. select BOARD_LATE_INIT
  107. select TARGET_SOCFPGA_CYCLONE5
  108. config TARGET_SOCFPGA_SR1500
  109. bool "SR1500 (Cyclone V)"
  110. select TARGET_SOCFPGA_CYCLONE5
  111. config TARGET_SOCFPGA_STRATIX10_SOCDK
  112. bool "Intel SOCFPGA SoCDK (Stratix 10)"
  113. select TARGET_SOCFPGA_STRATIX10
  114. config TARGET_SOCFPGA_TERASIC_DE0_NANO
  115. bool "Terasic DE0-Nano-Atlas (Cyclone V)"
  116. select TARGET_SOCFPGA_CYCLONE5
  117. config TARGET_SOCFPGA_TERASIC_DE10_NANO
  118. bool "Terasic DE10-Nano (Cyclone V)"
  119. select TARGET_SOCFPGA_CYCLONE5
  120. config TARGET_SOCFPGA_TERASIC_DE1_SOC
  121. bool "Terasic DE1-SoC (Cyclone V)"
  122. select TARGET_SOCFPGA_CYCLONE5
  123. config TARGET_SOCFPGA_TERASIC_SOCKIT
  124. bool "Terasic SoCkit (Cyclone V)"
  125. select TARGET_SOCFPGA_CYCLONE5
  126. endchoice
  127. config SYS_BOARD
  128. default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
  129. default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
  130. default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
  131. default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
  132. default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
  133. default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
  134. default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
  135. default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
  136. default "is1" if TARGET_SOCFPGA_IS1
  137. default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
  138. default "secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
  139. default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
  140. default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
  141. default "sr1500" if TARGET_SOCFPGA_SR1500
  142. default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
  143. default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
  144. config SYS_VENDOR
  145. default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK
  146. default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
  147. default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
  148. default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
  149. default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
  150. default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
  151. default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
  152. default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
  153. default "keymile" if TARGET_SOCFPGA_ARRIA5_SECU1
  154. default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
  155. default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
  156. default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
  157. default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
  158. default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
  159. config SYS_SOC
  160. default "socfpga"
  161. config SYS_CONFIG_NAME
  162. default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
  163. default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
  164. default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
  165. default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
  166. default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
  167. default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
  168. default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
  169. default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
  170. default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
  171. default "socfpga_is1" if TARGET_SOCFPGA_IS1
  172. default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
  173. default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
  174. default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
  175. default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
  176. default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
  177. default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
  178. source "board/keymile/Kconfig"
  179. endif