sdram_config.h 9.0 KB

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  1. /* SPDX-License-Identifier: BSD-3-Clause */
  2. /*
  3. * Altera SoCFPGA SDRAM configuration
  4. */
  5. #ifndef __SOCFPGA_SDRAM_CONFIG_H__
  6. #define __SOCFPGA_SDRAM_CONFIG_H__
  7. /* SDRAM configuration */
  8. #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
  9. #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
  10. #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
  11. #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
  12. #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
  13. #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
  14. #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
  15. #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
  16. #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
  17. #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
  18. #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
  19. #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
  20. #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
  21. #define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
  22. #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
  23. #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
  24. #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
  25. #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
  26. #define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
  27. #define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
  28. #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
  29. #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
  30. #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
  31. #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
  32. #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
  33. #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
  34. #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
  35. #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140
  36. #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5
  37. #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
  38. #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560
  39. #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
  40. #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
  41. #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
  42. #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
  43. #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
  44. #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
  45. #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
  46. #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5
  47. #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
  48. #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
  49. #define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
  50. #define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
  51. #define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
  52. #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
  53. #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
  54. #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
  55. #define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
  56. #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
  57. #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
  58. #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
  59. #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
  60. #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
  61. #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
  62. #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
  63. #define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
  64. #define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
  65. #define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
  66. #define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
  67. #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
  68. #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
  69. #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
  70. #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
  71. #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
  72. #define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
  73. #define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
  74. #define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
  75. #define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
  76. #define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
  77. #define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
  78. /* Sequencer auto configuration */
  79. #define RW_MGR_ACTIVATE_0_AND_1 0x0D
  80. #define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
  81. #define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
  82. #define RW_MGR_ACTIVATE_1 0x0F
  83. #define RW_MGR_CLEAR_DQS_ENABLE 0x49
  84. #define RW_MGR_GUARANTEED_READ 0x4C
  85. #define RW_MGR_GUARANTEED_READ_CONT 0x54
  86. #define RW_MGR_GUARANTEED_WRITE 0x18
  87. #define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B
  88. #define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F
  89. #define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19
  90. #define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D
  91. #define RW_MGR_IDLE 0x00
  92. #define RW_MGR_IDLE_LOOP1 0x7B
  93. #define RW_MGR_IDLE_LOOP2 0x7A
  94. #define RW_MGR_INIT_RESET_0_CKE_0 0x6F
  95. #define RW_MGR_INIT_RESET_1_CKE_0 0x74
  96. #define RW_MGR_LFSR_WR_RD_BANK_0 0x22
  97. #define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25
  98. #define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24
  99. #define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23
  100. #define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32
  101. #define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21
  102. #define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36
  103. #define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39
  104. #define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38
  105. #define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37
  106. #define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46
  107. #define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35
  108. #define RW_MGR_MRS0_DLL_RESET 0x02
  109. #define RW_MGR_MRS0_DLL_RESET_MIRR 0x08
  110. #define RW_MGR_MRS0_USER 0x07
  111. #define RW_MGR_MRS0_USER_MIRR 0x0C
  112. #define RW_MGR_MRS1 0x03
  113. #define RW_MGR_MRS1_MIRR 0x09
  114. #define RW_MGR_MRS2 0x04
  115. #define RW_MGR_MRS2_MIRR 0x0A
  116. #define RW_MGR_MRS3 0x05
  117. #define RW_MGR_MRS3_MIRR 0x0B
  118. #define RW_MGR_PRECHARGE_ALL 0x12
  119. #define RW_MGR_READ_B2B 0x59
  120. #define RW_MGR_READ_B2B_WAIT1 0x61
  121. #define RW_MGR_READ_B2B_WAIT2 0x6B
  122. #define RW_MGR_REFRESH_ALL 0x14
  123. #define RW_MGR_RETURN 0x01
  124. #define RW_MGR_SGLE_READ 0x7D
  125. #define RW_MGR_ZQCL 0x06
  126. /* Sequencer defines configuration */
  127. #define AFI_RATE_RATIO 1
  128. #define CALIB_LFIFO_OFFSET 7
  129. #define CALIB_VFIFO_OFFSET 5
  130. #define ENABLE_SUPER_QUICK_CALIBRATION 0
  131. #define IO_DELAY_PER_DCHAIN_TAP 25
  132. #define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
  133. #define IO_DELAY_PER_OPA_TAP 312
  134. #define IO_DLL_CHAIN_LENGTH 8
  135. #define IO_DQDQS_OUT_PHASE_MAX 0
  136. #define IO_DQS_EN_DELAY_MAX 31
  137. #define IO_DQS_EN_DELAY_OFFSET 0
  138. #define IO_DQS_EN_PHASE_MAX 7
  139. #define IO_DQS_IN_DELAY_MAX 31
  140. #define IO_DQS_IN_RESERVE 4
  141. #define IO_DQS_OUT_RESERVE 4
  142. #define IO_IO_IN_DELAY_MAX 31
  143. #define IO_IO_OUT1_DELAY_MAX 31
  144. #define IO_IO_OUT2_DELAY_MAX 0
  145. #define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
  146. #define MAX_LATENCY_COUNT_WIDTH 5
  147. #define READ_VALID_FIFO_SIZE 16
  148. #define REG_FILE_INIT_SEQ_SIGNATURE 0x55550496
  149. #define RW_MGR_MEM_ADDRESS_MIRRORING 0
  150. #define RW_MGR_MEM_DATA_MASK_WIDTH 4
  151. #define RW_MGR_MEM_DATA_WIDTH 32
  152. #define RW_MGR_MEM_DQ_PER_READ_DQS 8
  153. #define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
  154. #define RW_MGR_MEM_IF_READ_DQS_WIDTH 4
  155. #define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4
  156. #define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
  157. #define RW_MGR_MEM_NUMBER_OF_RANKS 1
  158. #define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
  159. #define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
  160. #define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4
  161. #define TINIT_CNTR0_VAL 99
  162. #define TINIT_CNTR1_VAL 32
  163. #define TINIT_CNTR2_VAL 32
  164. #define TRESET_CNTR0_VAL 99
  165. #define TRESET_CNTR1_VAL 99
  166. #define TRESET_CNTR2_VAL 10
  167. /* Sequencer ac_rom_init configuration */
  168. const u32 ac_rom_init[] = {
  169. 0x20700000,
  170. 0x20780000,
  171. 0x10080421,
  172. 0x10080520,
  173. 0x10090044,
  174. 0x100a0008,
  175. 0x100b0000,
  176. 0x10380400,
  177. 0x10080441,
  178. 0x100804c0,
  179. 0x100a0024,
  180. 0x10090010,
  181. 0x100b0000,
  182. 0x30780000,
  183. 0x38780000,
  184. 0x30780000,
  185. 0x10680000,
  186. 0x106b0000,
  187. 0x10280400,
  188. 0x10480000,
  189. 0x1c980000,
  190. 0x1c9b0000,
  191. 0x1c980008,
  192. 0x1c9b0008,
  193. 0x38f80000,
  194. 0x3cf80000,
  195. 0x38780000,
  196. 0x18180000,
  197. 0x18980000,
  198. 0x13580000,
  199. 0x135b0000,
  200. 0x13580008,
  201. 0x135b0008,
  202. 0x33780000,
  203. 0x10580008,
  204. 0x10780000
  205. };
  206. /* Sequencer inst_rom_init configuration */
  207. const u32 inst_rom_init[] = {
  208. 0x80000,
  209. 0x80680,
  210. 0x8180,
  211. 0x8200,
  212. 0x8280,
  213. 0x8300,
  214. 0x8380,
  215. 0x8100,
  216. 0x8480,
  217. 0x8500,
  218. 0x8580,
  219. 0x8600,
  220. 0x8400,
  221. 0x800,
  222. 0x8680,
  223. 0x880,
  224. 0xa680,
  225. 0x80680,
  226. 0x900,
  227. 0x80680,
  228. 0x980,
  229. 0xa680,
  230. 0x8680,
  231. 0x80680,
  232. 0xb68,
  233. 0xcce8,
  234. 0xae8,
  235. 0x8ce8,
  236. 0xb88,
  237. 0xec88,
  238. 0xa08,
  239. 0xac88,
  240. 0x80680,
  241. 0xce00,
  242. 0xcd80,
  243. 0xe700,
  244. 0xc00,
  245. 0x20ce0,
  246. 0x20ce0,
  247. 0x20ce0,
  248. 0x20ce0,
  249. 0xd00,
  250. 0x680,
  251. 0x680,
  252. 0x680,
  253. 0x680,
  254. 0x60e80,
  255. 0x61080,
  256. 0x61080,
  257. 0x61080,
  258. 0xa680,
  259. 0x8680,
  260. 0x80680,
  261. 0xce00,
  262. 0xcd80,
  263. 0xe700,
  264. 0xc00,
  265. 0x30ce0,
  266. 0x30ce0,
  267. 0x30ce0,
  268. 0x30ce0,
  269. 0xd00,
  270. 0x680,
  271. 0x680,
  272. 0x680,
  273. 0x680,
  274. 0x70e80,
  275. 0x71080,
  276. 0x71080,
  277. 0x71080,
  278. 0xa680,
  279. 0x8680,
  280. 0x80680,
  281. 0x1158,
  282. 0x6d8,
  283. 0x80680,
  284. 0x1168,
  285. 0x7e8,
  286. 0x7e8,
  287. 0x87e8,
  288. 0x40fe8,
  289. 0x410e8,
  290. 0x410e8,
  291. 0x410e8,
  292. 0x1168,
  293. 0x7e8,
  294. 0x7e8,
  295. 0xa7e8,
  296. 0x80680,
  297. 0x40e88,
  298. 0x41088,
  299. 0x41088,
  300. 0x41088,
  301. 0x40f68,
  302. 0x410e8,
  303. 0x410e8,
  304. 0x410e8,
  305. 0xa680,
  306. 0x40fe8,
  307. 0x410e8,
  308. 0x410e8,
  309. 0x410e8,
  310. 0x41008,
  311. 0x41088,
  312. 0x41088,
  313. 0x41088,
  314. 0x1100,
  315. 0xc680,
  316. 0x8680,
  317. 0xe680,
  318. 0x80680,
  319. 0x0,
  320. 0x8000,
  321. 0xa000,
  322. 0xc000,
  323. 0x80000,
  324. 0x80,
  325. 0x8080,
  326. 0xa080,
  327. 0xc080,
  328. 0x80080,
  329. 0x9180,
  330. 0x8680,
  331. 0xa680,
  332. 0x80680,
  333. 0x40f08,
  334. 0x80680
  335. };
  336. #endif /* __SOCFPGA_SDRAM_CONFIG_H__ */