ls1021aqds.c 8.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. * Copyright 2019 NXP
  5. */
  6. #include <common.h>
  7. #include <clock_legacy.h>
  8. #include <fdt_support.h>
  9. #include <i2c.h>
  10. #include <init.h>
  11. #include <log.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/immap_ls102xa.h>
  14. #include <asm/arch/clock.h>
  15. #include <asm/arch/fsl_serdes.h>
  16. #include <asm/arch/ls102xa_soc.h>
  17. #include <asm/arch/ls102xa_devdis.h>
  18. #include <hwconfig.h>
  19. #include <mmc.h>
  20. #include <fsl_csu.h>
  21. #include <fsl_ifc.h>
  22. #include <fsl_sec.h>
  23. #include <spl.h>
  24. #include <fsl_devdis.h>
  25. #include <fsl_validate.h>
  26. #include <fsl_ddr.h>
  27. #include "../common/i2c_mux.h"
  28. #include "../common/sleep.h"
  29. #include "../common/qixis.h"
  30. #include "ls1021aqds_qixis.h"
  31. #ifdef CONFIG_U_QE
  32. #include <fsl_qe.h>
  33. #endif
  34. #define PIN_MUX_SEL_CAN 0x03
  35. #define PIN_MUX_SEL_IIC2 0xa0
  36. #define PIN_MUX_SEL_RGMII 0x00
  37. #define PIN_MUX_SEL_SAI 0x0c
  38. #define PIN_MUX_SEL_SDHC 0x00
  39. #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value)
  40. #define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
  41. enum {
  42. MUX_TYPE_CAN,
  43. MUX_TYPE_IIC2,
  44. MUX_TYPE_RGMII,
  45. MUX_TYPE_SAI,
  46. MUX_TYPE_SDHC,
  47. MUX_TYPE_SD_PCI4,
  48. MUX_TYPE_SD_PC_SA_SG_SG,
  49. MUX_TYPE_SD_PC_SA_PC_SG,
  50. MUX_TYPE_SD_PC_SG_SG,
  51. };
  52. enum {
  53. GE0_CLK125,
  54. GE2_CLK125,
  55. GE1_CLK125,
  56. };
  57. int checkboard(void)
  58. {
  59. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  60. char buf[64];
  61. #endif
  62. #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
  63. u8 sw;
  64. #endif
  65. puts("Board: LS1021AQDS\n");
  66. #ifdef CONFIG_SD_BOOT
  67. puts("SD\n");
  68. #elif CONFIG_QSPI_BOOT
  69. puts("QSPI\n");
  70. #else
  71. sw = QIXIS_READ(brdcfg[0]);
  72. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  73. if (sw < 0x8)
  74. printf("vBank: %d\n", sw);
  75. else if (sw == 0x8)
  76. puts("PromJet\n");
  77. else if (sw == 0x9)
  78. puts("NAND\n");
  79. else if (sw == 0x15)
  80. printf("IFCCard\n");
  81. else
  82. printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  83. #endif
  84. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  85. printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
  86. QIXIS_READ(id), QIXIS_READ(arch));
  87. printf("FPGA: v%d (%s), build %d\n",
  88. (int)QIXIS_READ(scver), qixis_read_tag(buf),
  89. (int)qixis_read_minor());
  90. #endif
  91. return 0;
  92. }
  93. unsigned long get_board_sys_clk(void)
  94. {
  95. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  96. switch (sysclk_conf & 0x0f) {
  97. case QIXIS_SYSCLK_64:
  98. return 64000000;
  99. case QIXIS_SYSCLK_83:
  100. return 83333333;
  101. case QIXIS_SYSCLK_100:
  102. return 100000000;
  103. case QIXIS_SYSCLK_125:
  104. return 125000000;
  105. case QIXIS_SYSCLK_133:
  106. return 133333333;
  107. case QIXIS_SYSCLK_150:
  108. return 150000000;
  109. case QIXIS_SYSCLK_160:
  110. return 160000000;
  111. case QIXIS_SYSCLK_166:
  112. return 166666666;
  113. }
  114. return 66666666;
  115. }
  116. unsigned long get_board_ddr_clk(void)
  117. {
  118. u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  119. switch ((ddrclk_conf & 0x30) >> 4) {
  120. case QIXIS_DDRCLK_100:
  121. return 100000000;
  122. case QIXIS_DDRCLK_125:
  123. return 125000000;
  124. case QIXIS_DDRCLK_133:
  125. return 133333333;
  126. }
  127. return 66666666;
  128. }
  129. int dram_init(void)
  130. {
  131. /*
  132. * When resuming from deep sleep, the I2C channel may not be
  133. * in the default channel. So, switch to the default channel
  134. * before accessing DDR SPD.
  135. *
  136. * PCA9547(0x77) mount on I2C1 bus
  137. */
  138. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
  139. return fsl_initdram();
  140. }
  141. int board_early_init_f(void)
  142. {
  143. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  144. #ifdef CONFIG_TSEC_ENET
  145. /* clear BD & FR bits for BE BD's and frame data */
  146. clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
  147. #endif
  148. #ifdef CONFIG_FSL_IFC
  149. init_early_memctl_regs();
  150. #endif
  151. arch_soc_init();
  152. #if defined(CONFIG_DEEP_SLEEP)
  153. if (is_warm_boot())
  154. fsl_dp_disable_console();
  155. #endif
  156. return 0;
  157. }
  158. #ifdef CONFIG_SPL_BUILD
  159. void board_init_f(ulong dummy)
  160. {
  161. #ifdef CONFIG_NAND_BOOT
  162. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  163. u32 porsr1, pinctl;
  164. /*
  165. * There is LS1 SoC issue where NOR, FPGA are inaccessible during
  166. * NAND boot because IFC signals > IFC_AD7 are not enabled.
  167. * This workaround changes RCW source to make all signals enabled.
  168. */
  169. porsr1 = in_be32(&gur->porsr1);
  170. pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
  171. DCFG_CCSR_PORSR1_RCW_SRC_I2C);
  172. out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
  173. pinctl);
  174. #endif
  175. /* Clear the BSS */
  176. memset(__bss_start, 0, __bss_end - __bss_start);
  177. #ifdef CONFIG_FSL_IFC
  178. init_early_memctl_regs();
  179. #endif
  180. get_clocks();
  181. #if defined(CONFIG_DEEP_SLEEP)
  182. if (is_warm_boot())
  183. fsl_dp_disable_console();
  184. #endif
  185. preloader_console_init();
  186. #ifdef CONFIG_SPL_I2C
  187. i2c_init_all();
  188. #endif
  189. timer_init();
  190. dram_init();
  191. /* Allow OCRAM access permission as R/W */
  192. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  193. enable_layerscape_ns_access();
  194. #endif
  195. board_init_r(NULL, 0);
  196. }
  197. #endif
  198. void config_etseccm_source(int etsec_gtx_125_mux)
  199. {
  200. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  201. switch (etsec_gtx_125_mux) {
  202. case GE0_CLK125:
  203. out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125);
  204. debug("etseccm set to GE0_CLK125\n");
  205. break;
  206. case GE2_CLK125:
  207. out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
  208. debug("etseccm set to GE2_CLK125\n");
  209. break;
  210. case GE1_CLK125:
  211. out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125);
  212. debug("etseccm set to GE1_CLK125\n");
  213. break;
  214. default:
  215. printf("Error! trying to set etseccm to invalid value\n");
  216. break;
  217. }
  218. }
  219. int config_board_mux(int ctrl_type)
  220. {
  221. u8 reg12, reg14;
  222. reg12 = QIXIS_READ(brdcfg[12]);
  223. reg14 = QIXIS_READ(brdcfg[14]);
  224. switch (ctrl_type) {
  225. case MUX_TYPE_CAN:
  226. config_etseccm_source(GE2_CLK125);
  227. reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
  228. break;
  229. case MUX_TYPE_IIC2:
  230. reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2);
  231. break;
  232. case MUX_TYPE_RGMII:
  233. reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
  234. break;
  235. case MUX_TYPE_SAI:
  236. config_etseccm_source(GE2_CLK125);
  237. reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
  238. break;
  239. case MUX_TYPE_SDHC:
  240. reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC);
  241. break;
  242. case MUX_TYPE_SD_PCI4:
  243. reg12 = 0x38;
  244. break;
  245. case MUX_TYPE_SD_PC_SA_SG_SG:
  246. reg12 = 0x01;
  247. break;
  248. case MUX_TYPE_SD_PC_SA_PC_SG:
  249. reg12 = 0x01;
  250. break;
  251. case MUX_TYPE_SD_PC_SG_SG:
  252. reg12 = 0x21;
  253. break;
  254. default:
  255. printf("Wrong mux interface type\n");
  256. return -1;
  257. }
  258. QIXIS_WRITE(brdcfg[12], reg12);
  259. QIXIS_WRITE(brdcfg[14], reg14);
  260. return 0;
  261. }
  262. int config_serdes_mux(void)
  263. {
  264. struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
  265. u32 cfg;
  266. cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
  267. cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
  268. switch (cfg) {
  269. case 0x0:
  270. config_board_mux(MUX_TYPE_SD_PCI4);
  271. break;
  272. case 0x30:
  273. config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
  274. break;
  275. case 0x60:
  276. config_board_mux(MUX_TYPE_SD_PC_SG_SG);
  277. break;
  278. case 0x70:
  279. config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
  280. break;
  281. default:
  282. printf("SRDS1 prtcl:0x%x\n", cfg);
  283. break;
  284. }
  285. return 0;
  286. }
  287. #ifdef CONFIG_BOARD_LATE_INIT
  288. int board_late_init(void)
  289. {
  290. #ifdef CONFIG_CHAIN_OF_TRUST
  291. fsl_setenv_chain_of_trust();
  292. #endif
  293. return 0;
  294. }
  295. #endif
  296. int misc_init_r(void)
  297. {
  298. int conflict_flag;
  299. /* some signals can not enable simultaneous*/
  300. conflict_flag = 0;
  301. if (hwconfig("sdhc"))
  302. conflict_flag++;
  303. if (hwconfig("iic2"))
  304. conflict_flag++;
  305. if (conflict_flag > 1) {
  306. printf("WARNING: pin conflict !\n");
  307. return 0;
  308. }
  309. conflict_flag = 0;
  310. if (hwconfig("rgmii"))
  311. conflict_flag++;
  312. if (hwconfig("can"))
  313. conflict_flag++;
  314. if (hwconfig("sai"))
  315. conflict_flag++;
  316. if (conflict_flag > 1) {
  317. printf("WARNING: pin conflict !\n");
  318. return 0;
  319. }
  320. if (hwconfig("can"))
  321. config_board_mux(MUX_TYPE_CAN);
  322. else if (hwconfig("rgmii"))
  323. config_board_mux(MUX_TYPE_RGMII);
  324. else if (hwconfig("sai"))
  325. config_board_mux(MUX_TYPE_SAI);
  326. if (hwconfig("iic2"))
  327. config_board_mux(MUX_TYPE_IIC2);
  328. else if (hwconfig("sdhc"))
  329. config_board_mux(MUX_TYPE_SDHC);
  330. #ifdef CONFIG_FSL_DEVICE_DISABLE
  331. device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
  332. #endif
  333. #ifdef CONFIG_FSL_CAAM
  334. return sec_init();
  335. #endif
  336. return 0;
  337. }
  338. int board_init(void)
  339. {
  340. #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
  341. erratum_a010315();
  342. #endif
  343. #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
  344. erratum_a009942_check_cpo();
  345. #endif
  346. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
  347. #ifndef CONFIG_SYS_FSL_NO_SERDES
  348. fsl_serdes_init();
  349. config_serdes_mux();
  350. #endif
  351. ls102xa_smmu_stream_id_init();
  352. #ifdef CONFIG_U_QE
  353. u_qe_init();
  354. #endif
  355. return 0;
  356. }
  357. #if defined(CONFIG_DEEP_SLEEP)
  358. void board_sleep_prepare(void)
  359. {
  360. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  361. enable_layerscape_ns_access();
  362. #endif
  363. }
  364. #endif
  365. int ft_board_setup(void *blob, struct bd_info *bd)
  366. {
  367. ft_cpu_setup(blob, bd);
  368. #ifdef CONFIG_PCI
  369. ft_pci_setup(blob, bd);
  370. #endif
  371. return 0;
  372. }
  373. u8 flash_read8(void *addr)
  374. {
  375. return __raw_readb(addr + 1);
  376. }
  377. void flash_write16(u16 val, void *addr)
  378. {
  379. u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
  380. __raw_writew(shftval, addr);
  381. }
  382. u16 flash_read16(void *addr)
  383. {
  384. u16 val = __raw_readw(addr);
  385. return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
  386. }