p1010rdb.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2010-2011 Freescale Semiconductor, Inc.
  4. * Copyright 2020 NXP
  5. */
  6. #include <common.h>
  7. #include <command.h>
  8. #include <image.h>
  9. #include <init.h>
  10. #include <net.h>
  11. #include <asm/global_data.h>
  12. #include <asm/processor.h>
  13. #include <asm/mmu.h>
  14. #include <asm/cache.h>
  15. #include <asm/immap_85xx.h>
  16. #include <asm/io.h>
  17. #include <env.h>
  18. #include <miiphy.h>
  19. #include <linux/libfdt.h>
  20. #include <fdt_support.h>
  21. #include <fsl_mdio.h>
  22. #include <tsec.h>
  23. #include <mmc.h>
  24. #include <netdev.h>
  25. #include <pci.h>
  26. #include <asm/fsl_serdes.h>
  27. #include <fsl_ifc.h>
  28. #include <asm/fsl_pci.h>
  29. #include <hwconfig.h>
  30. #include <i2c.h>
  31. DECLARE_GLOBAL_DATA_PTR;
  32. #define GPIO4_PCIE_RESET_SET 0x08000000
  33. #define MUX_CPLD_CAN_UART 0x00
  34. #define MUX_CPLD_TDM 0x01
  35. #define MUX_CPLD_SPICS0_FLASH 0x00
  36. #define MUX_CPLD_SPICS0_SLIC 0x02
  37. #define PMUXCR1_IFC_MASK 0x00ffff00
  38. #define PMUXCR1_SDHC_MASK 0x00fff000
  39. #define PMUXCR1_SDHC_ENABLE 0x00555000
  40. enum {
  41. MUX_TYPE_IFC,
  42. MUX_TYPE_SDHC,
  43. MUX_TYPE_SPIFLASH,
  44. MUX_TYPE_TDM,
  45. MUX_TYPE_CAN,
  46. MUX_TYPE_CS0_NOR,
  47. MUX_TYPE_CS0_NAND,
  48. };
  49. enum {
  50. I2C_READ_BANK,
  51. I2C_READ_PCB_VER,
  52. };
  53. static uint sd_ifc_mux;
  54. struct cpld_data {
  55. u8 cpld_ver; /* cpld revision */
  56. #if defined(CONFIG_TARGET_P1010RDB_PA)
  57. u8 pcba_ver; /* pcb revision number */
  58. u8 twindie_ddr3;
  59. u8 res1[6];
  60. u8 bank_sel; /* NOR Flash bank */
  61. u8 res2[5];
  62. u8 usb2_sel;
  63. u8 res3[1];
  64. u8 porsw_sel;
  65. u8 tdm_can_sel;
  66. u8 spi_cs0_sel; /* SPI CS0 SLIC/SPI Flash */
  67. u8 por0; /* POR Options */
  68. u8 por1; /* POR Options */
  69. u8 por2; /* POR Options */
  70. u8 por3; /* POR Options */
  71. #elif defined(CONFIG_TARGET_P1010RDB_PB)
  72. u8 rom_loc;
  73. #endif
  74. };
  75. int board_early_init_f(void)
  76. {
  77. ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
  78. struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
  79. /* Clock configuration to access CPLD using IFC(GPCM) */
  80. setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
  81. /*
  82. * Reset PCIe slots via GPIO4
  83. */
  84. setbits_be32(&pgpio->gpdir, GPIO4_PCIE_RESET_SET);
  85. setbits_be32(&pgpio->gpdat, GPIO4_PCIE_RESET_SET);
  86. return 0;
  87. }
  88. int board_early_init_r(void)
  89. {
  90. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  91. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  92. /*
  93. * Remap Boot flash region to caching-inhibited
  94. * so that flash can be erased properly.
  95. */
  96. /* Flush d-cache and invalidate i-cache of any FLASH data */
  97. flush_dcache();
  98. invalidate_icache();
  99. if (flash_esel == -1) {
  100. /* very unlikely unless something is messed up */
  101. puts("Error: Could not find TLB for FLASH BASE\n");
  102. flash_esel = 2; /* give our best effort to continue */
  103. } else {
  104. /* invalidate existing TLB entry for flash */
  105. disable_tlb(flash_esel);
  106. }
  107. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
  108. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  109. 0, flash_esel, BOOKE_PAGESZ_16M, 1);
  110. set_tlb(1, flashbase + 0x1000000,
  111. CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
  112. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  113. 0, flash_esel+1, BOOKE_PAGESZ_16M, 1);
  114. return 0;
  115. }
  116. int config_board_mux(int ctrl_type)
  117. {
  118. ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  119. u8 tmp;
  120. #if CONFIG_IS_ENABLED(DM_I2C)
  121. struct udevice *dev;
  122. int ret;
  123. #if defined(CONFIG_TARGET_P1010RDB_PA)
  124. struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  125. ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM,
  126. I2C_PCA9557_ADDR1, 1, &dev);
  127. if (ret) {
  128. printf("%s: Cannot find udev for a bus %d\n",
  129. __func__, I2C_PCA9557_BUS_NUM);
  130. return ret;
  131. }
  132. switch (ctrl_type) {
  133. case MUX_TYPE_IFC:
  134. tmp = 0xf0;
  135. dm_i2c_write(dev, 3, &tmp, 1);
  136. tmp = 0x01;
  137. dm_i2c_write(dev, 1, &tmp, 1);
  138. sd_ifc_mux = MUX_TYPE_IFC;
  139. clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
  140. break;
  141. case MUX_TYPE_SDHC:
  142. tmp = 0xf0;
  143. dm_i2c_write(dev, 3, &tmp, 1);
  144. tmp = 0x05;
  145. dm_i2c_write(dev, 1, &tmp, 1);
  146. sd_ifc_mux = MUX_TYPE_SDHC;
  147. clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
  148. PMUXCR1_SDHC_ENABLE);
  149. break;
  150. case MUX_TYPE_SPIFLASH:
  151. out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
  152. break;
  153. case MUX_TYPE_TDM:
  154. out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
  155. out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
  156. break;
  157. case MUX_TYPE_CAN:
  158. out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
  159. break;
  160. default:
  161. break;
  162. }
  163. #elif defined(CONFIG_TARGET_P1010RDB_PB)
  164. ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM,
  165. I2C_PCA9557_ADDR2, 1, &dev);
  166. if (ret) {
  167. printf("%s: Cannot find udev for a bus %d\n",
  168. __func__, I2C_PCA9557_BUS_NUM);
  169. return ret;
  170. }
  171. switch (ctrl_type) {
  172. case MUX_TYPE_IFC:
  173. dm_i2c_read(dev, 0, &tmp, 1);
  174. clrbits_8(&tmp, 0x04);
  175. dm_i2c_write(dev, 1, &tmp, 1);
  176. dm_i2c_read(dev, 3, &tmp, 1);
  177. clrbits_8(&tmp, 0x04);
  178. dm_i2c_write(dev, 3, &tmp, 1);
  179. sd_ifc_mux = MUX_TYPE_IFC;
  180. clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
  181. break;
  182. case MUX_TYPE_SDHC:
  183. dm_i2c_read(dev, 0, &tmp, 1);
  184. setbits_8(&tmp, 0x04);
  185. dm_i2c_write(dev, 1, &tmp, 1);
  186. dm_i2c_read(dev, 3, &tmp, 1);
  187. clrbits_8(&tmp, 0x04);
  188. dm_i2c_write(dev, 3, &tmp, 1);
  189. sd_ifc_mux = MUX_TYPE_SDHC;
  190. clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
  191. PMUXCR1_SDHC_ENABLE);
  192. break;
  193. case MUX_TYPE_SPIFLASH:
  194. dm_i2c_read(dev, 0, &tmp, 1);
  195. clrbits_8(&tmp, 0x80);
  196. dm_i2c_write(dev, 1, &tmp, 1);
  197. dm_i2c_read(dev, 3, &tmp, 1);
  198. clrbits_8(&tmp, 0x80);
  199. dm_i2c_write(dev, 3, &tmp, 1);
  200. break;
  201. case MUX_TYPE_TDM:
  202. dm_i2c_read(dev, 0, &tmp, 1);
  203. setbits_8(&tmp, 0x82);
  204. dm_i2c_write(dev, 1, &tmp, 1);
  205. dm_i2c_read(dev, 3, &tmp, 1);
  206. clrbits_8(&tmp, 0x82);
  207. dm_i2c_write(dev, 3, &tmp, 1);
  208. break;
  209. case MUX_TYPE_CAN:
  210. dm_i2c_read(dev, 0, &tmp, 1);
  211. clrbits_8(&tmp, 0x02);
  212. dm_i2c_write(dev, 1, &tmp, 1);
  213. dm_i2c_read(dev, 3, &tmp, 1);
  214. clrbits_8(&tmp, 0x02);
  215. dm_i2c_write(dev, 3, &tmp, 1);
  216. break;
  217. case MUX_TYPE_CS0_NOR:
  218. dm_i2c_read(dev, 0, &tmp, 1);
  219. clrbits_8(&tmp, 0x08);
  220. dm_i2c_write(dev, 1, &tmp, 1);
  221. dm_i2c_read(dev, 3, &tmp, 1);
  222. clrbits_8(&tmp, 0x08);
  223. dm_i2c_write(dev, 3, &tmp, 1);
  224. break;
  225. case MUX_TYPE_CS0_NAND:
  226. dm_i2c_read(dev, 0, &tmp, 1);
  227. setbits_8(&tmp, 0x08);
  228. dm_i2c_write(dev, 1, &tmp, 1);
  229. dm_i2c_read(dev, 3, &tmp, 1);
  230. clrbits_8(&tmp, 0x08);
  231. dm_i2c_write(dev, 3, &tmp, 1);
  232. break;
  233. default:
  234. break;
  235. }
  236. #endif
  237. #else
  238. #if defined(CONFIG_TARGET_P1010RDB_PA)
  239. struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  240. switch (ctrl_type) {
  241. case MUX_TYPE_IFC:
  242. i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
  243. tmp = 0xf0;
  244. i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
  245. tmp = 0x01;
  246. i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
  247. sd_ifc_mux = MUX_TYPE_IFC;
  248. clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
  249. break;
  250. case MUX_TYPE_SDHC:
  251. i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
  252. tmp = 0xf0;
  253. i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
  254. tmp = 0x05;
  255. i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
  256. sd_ifc_mux = MUX_TYPE_SDHC;
  257. clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
  258. PMUXCR1_SDHC_ENABLE);
  259. break;
  260. case MUX_TYPE_SPIFLASH:
  261. out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
  262. break;
  263. case MUX_TYPE_TDM:
  264. out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
  265. out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
  266. break;
  267. case MUX_TYPE_CAN:
  268. out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
  269. break;
  270. default:
  271. break;
  272. }
  273. #elif defined(CONFIG_TARGET_P1010RDB_PB)
  274. uint orig_bus = i2c_get_bus_num();
  275. i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
  276. switch (ctrl_type) {
  277. case MUX_TYPE_IFC:
  278. i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
  279. clrbits_8(&tmp, 0x04);
  280. i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
  281. i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  282. clrbits_8(&tmp, 0x04);
  283. i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  284. sd_ifc_mux = MUX_TYPE_IFC;
  285. clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
  286. break;
  287. case MUX_TYPE_SDHC:
  288. i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
  289. setbits_8(&tmp, 0x04);
  290. i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
  291. i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  292. clrbits_8(&tmp, 0x04);
  293. i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  294. sd_ifc_mux = MUX_TYPE_SDHC;
  295. clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
  296. PMUXCR1_SDHC_ENABLE);
  297. break;
  298. case MUX_TYPE_SPIFLASH:
  299. i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
  300. clrbits_8(&tmp, 0x80);
  301. i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
  302. i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  303. clrbits_8(&tmp, 0x80);
  304. i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  305. break;
  306. case MUX_TYPE_TDM:
  307. i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
  308. setbits_8(&tmp, 0x82);
  309. i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
  310. i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  311. clrbits_8(&tmp, 0x82);
  312. i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  313. break;
  314. case MUX_TYPE_CAN:
  315. i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
  316. clrbits_8(&tmp, 0x02);
  317. i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
  318. i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  319. clrbits_8(&tmp, 0x02);
  320. i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  321. break;
  322. case MUX_TYPE_CS0_NOR:
  323. i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
  324. clrbits_8(&tmp, 0x08);
  325. i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
  326. i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  327. clrbits_8(&tmp, 0x08);
  328. i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  329. break;
  330. case MUX_TYPE_CS0_NAND:
  331. i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
  332. setbits_8(&tmp, 0x08);
  333. i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
  334. i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  335. clrbits_8(&tmp, 0x08);
  336. i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  337. break;
  338. default:
  339. break;
  340. }
  341. i2c_set_bus_num(orig_bus);
  342. #endif
  343. #endif
  344. return 0;
  345. }
  346. #ifdef CONFIG_TARGET_P1010RDB_PB
  347. int i2c_pca9557_read(int type)
  348. {
  349. u8 val;
  350. int bus_num = I2C_PCA9557_BUS_NUM;
  351. #if CONFIG_IS_ENABLED(DM_I2C)
  352. struct udevice *dev;
  353. int ret;
  354. ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA9557_ADDR2, 1, &dev);
  355. if (ret) {
  356. printf("%s: Cannot find udev for a bus %d\n",
  357. __func__, bus_num);
  358. return ret;
  359. }
  360. dm_i2c_read(dev, 0, &val, 1);
  361. #else
  362. i2c_set_bus_num(bus_num);
  363. i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1);
  364. #endif
  365. switch (type) {
  366. case I2C_READ_BANK:
  367. val = (val & 0x10) >> 4;
  368. break;
  369. case I2C_READ_PCB_VER:
  370. val = ((val & 0x60) >> 5) + 1;
  371. break;
  372. default:
  373. break;
  374. }
  375. return val;
  376. }
  377. #endif
  378. int checkboard(void)
  379. {
  380. struct cpu_type *cpu;
  381. struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  382. u8 val;
  383. cpu = gd->arch.cpu;
  384. #if defined(CONFIG_TARGET_P1010RDB_PA)
  385. printf("Board: %sRDB-PA, ", cpu->name);
  386. #elif defined(CONFIG_TARGET_P1010RDB_PB)
  387. printf("Board: %sRDB-PB, ", cpu->name);
  388. #if CONFIG_IS_ENABLED(DM_I2C)
  389. struct udevice *dev;
  390. int ret;
  391. ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, I2C_PCA9557_ADDR2,
  392. 1, &dev);
  393. if (ret) {
  394. printf("%s: Cannot find udev for a bus %d\n", __func__,
  395. I2C_PCA9557_BUS_NUM);
  396. return ret;
  397. }
  398. val = 0x0; /* no polarity inversion */
  399. dm_i2c_write(dev, 2, &val, 1);
  400. #else
  401. i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
  402. i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE);
  403. val = 0x0; /* no polarity inversion */
  404. i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1);
  405. #endif
  406. #endif
  407. #ifdef CONFIG_SDCARD
  408. /* switch to IFC to read info from CPLD */
  409. config_board_mux(MUX_TYPE_IFC);
  410. #endif
  411. #if defined(CONFIG_TARGET_P1010RDB_PA)
  412. val = (in_8(&cpld_data->pcba_ver) & 0xf);
  413. printf("PCB: v%x.0\n", val);
  414. #elif defined(CONFIG_TARGET_P1010RDB_PB)
  415. val = in_8(&cpld_data->cpld_ver);
  416. printf("CPLD: v%x.%x, ", val >> 4, val & 0xf);
  417. printf("PCB: v%x.0, ", i2c_pca9557_read(I2C_READ_PCB_VER));
  418. val = in_8(&cpld_data->rom_loc) & 0xf;
  419. puts("Boot from: ");
  420. switch (val) {
  421. case 0xf:
  422. config_board_mux(MUX_TYPE_CS0_NOR);
  423. printf("NOR vBank%d\n", i2c_pca9557_read(I2C_READ_BANK));
  424. break;
  425. case 0xe:
  426. puts("SDHC\n");
  427. val = 0x60; /* set pca9557 pin input/output */
  428. #if CONFIG_IS_ENABLED(DM_I2C)
  429. dm_i2c_write(dev, 3, &val, 1);
  430. #else
  431. i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1);
  432. #endif
  433. break;
  434. case 0x5:
  435. config_board_mux(MUX_TYPE_IFC);
  436. config_board_mux(MUX_TYPE_CS0_NAND);
  437. puts("NAND\n");
  438. break;
  439. case 0x6:
  440. config_board_mux(MUX_TYPE_IFC);
  441. puts("SPI\n");
  442. break;
  443. default:
  444. puts("unknown\n");
  445. break;
  446. }
  447. #endif
  448. return 0;
  449. }
  450. #ifndef CONFIG_DM_ETH
  451. int board_eth_init(struct bd_info *bis)
  452. {
  453. #ifdef CONFIG_TSEC_ENET
  454. struct fsl_pq_mdio_info mdio_info;
  455. struct tsec_info_struct tsec_info[4];
  456. struct cpu_type *cpu;
  457. int num = 0;
  458. cpu = gd->arch.cpu;
  459. #ifdef CONFIG_TSEC1
  460. SET_STD_TSEC_INFO(tsec_info[num], 1);
  461. num++;
  462. #endif
  463. #ifdef CONFIG_TSEC2
  464. SET_STD_TSEC_INFO(tsec_info[num], 2);
  465. num++;
  466. #endif
  467. #ifdef CONFIG_TSEC3
  468. /* P1014 and it's derivatives do not support eTSEC3 */
  469. if (cpu->soc_ver != SVR_P1014) {
  470. SET_STD_TSEC_INFO(tsec_info[num], 3);
  471. num++;
  472. }
  473. #endif
  474. if (!num) {
  475. printf("No TSECs initialized\n");
  476. return 0;
  477. }
  478. mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
  479. mdio_info.name = DEFAULT_MII_NAME;
  480. fsl_pq_mdio_init(bis, &mdio_info);
  481. tsec_eth_init(bis, tsec_info, num);
  482. #endif
  483. return pci_eth_init(bis);
  484. }
  485. #endif
  486. #if defined(CONFIG_OF_BOARD_SETUP)
  487. void fdt_del_flexcan(void *blob)
  488. {
  489. int nodeoff = 0;
  490. while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
  491. "fsl,p1010-flexcan")) >= 0) {
  492. fdt_del_node(blob, nodeoff);
  493. }
  494. }
  495. void fdt_del_spi_flash(void *blob)
  496. {
  497. int nodeoff = 0;
  498. while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
  499. "spansion,s25sl12801")) >= 0) {
  500. fdt_del_node(blob, nodeoff);
  501. }
  502. }
  503. void fdt_del_spi_slic(void *blob)
  504. {
  505. int nodeoff = 0;
  506. while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
  507. "zarlink,le88266")) >= 0) {
  508. fdt_del_node(blob, nodeoff);
  509. }
  510. }
  511. void fdt_del_tdm(void *blob)
  512. {
  513. int nodeoff = 0;
  514. while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
  515. "fsl,starlite-tdm")) >= 0) {
  516. fdt_del_node(blob, nodeoff);
  517. }
  518. }
  519. void fdt_del_sdhc(void *blob)
  520. {
  521. int nodeoff = 0;
  522. while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
  523. "fsl,esdhc")) >= 0) {
  524. fdt_del_node(blob, nodeoff);
  525. }
  526. }
  527. void fdt_del_ifc(void *blob)
  528. {
  529. int nodeoff = 0;
  530. while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
  531. "fsl,ifc")) >= 0) {
  532. fdt_del_node(blob, nodeoff);
  533. }
  534. }
  535. void fdt_disable_uart1(void *blob)
  536. {
  537. int nodeoff;
  538. nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550",
  539. CONFIG_SYS_NS16550_COM2);
  540. if (nodeoff > 0) {
  541. fdt_status_disabled(blob, nodeoff);
  542. } else {
  543. printf("WARNING unable to set status for fsl,ns16550 "
  544. "uart1: %s\n", fdt_strerror(nodeoff));
  545. }
  546. }
  547. int ft_board_setup(void *blob, struct bd_info *bd)
  548. {
  549. phys_addr_t base;
  550. phys_size_t size;
  551. struct cpu_type *cpu;
  552. cpu = gd->arch.cpu;
  553. ft_cpu_setup(blob, bd);
  554. base = env_get_bootm_low();
  555. size = env_get_bootm_size();
  556. fdt_fixup_memory(blob, (u64)base, (u64)size);
  557. #if defined(CONFIG_HAS_FSL_DR_USB)
  558. fsl_fdt_fixup_dr_usb(blob, bd);
  559. #endif
  560. /* P1014 and it's derivatives don't support CAN and eTSEC3 */
  561. if (cpu->soc_ver == SVR_P1014) {
  562. fdt_del_flexcan(blob);
  563. fdt_del_node_and_alias(blob, "ethernet2");
  564. }
  565. /* Delete IFC node as IFC pins are multiplexing with SDHC */
  566. if (sd_ifc_mux != MUX_TYPE_IFC)
  567. fdt_del_ifc(blob);
  568. else
  569. fdt_del_sdhc(blob);
  570. if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
  571. fdt_del_tdm(blob);
  572. fdt_del_spi_slic(blob);
  573. } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
  574. fdt_del_flexcan(blob);
  575. fdt_del_spi_flash(blob);
  576. fdt_disable_uart1(blob);
  577. } else {
  578. /*
  579. * If we don't set fsl_p1010mux:tdm_can to "can" or "tdm"
  580. * explicitly, defaultly spi_cs_sel to spi-flash instead of
  581. * to tdm/slic.
  582. */
  583. fdt_del_tdm(blob);
  584. fdt_del_flexcan(blob);
  585. fdt_disable_uart1(blob);
  586. }
  587. return 0;
  588. }
  589. #endif
  590. #ifdef CONFIG_SDCARD
  591. int board_mmc_init(struct bd_info *bis)
  592. {
  593. config_board_mux(MUX_TYPE_SDHC);
  594. return -1;
  595. }
  596. #else
  597. void board_reset(void)
  598. {
  599. /* mux to IFC to enable CPLD for reset */
  600. if (sd_ifc_mux != MUX_TYPE_IFC)
  601. config_board_mux(MUX_TYPE_IFC);
  602. }
  603. #endif
  604. int misc_init_r(void)
  605. {
  606. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  607. if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
  608. clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM |
  609. MPC85xx_PMUXCR_CAN1_UART |
  610. MPC85xx_PMUXCR_CAN2_TDM |
  611. MPC85xx_PMUXCR_CAN2_UART);
  612. config_board_mux(MUX_TYPE_CAN);
  613. } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
  614. clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART |
  615. MPC85xx_PMUXCR_CAN1_UART);
  616. setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM |
  617. MPC85xx_PMUXCR_CAN1_TDM);
  618. clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO);
  619. setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM);
  620. config_board_mux(MUX_TYPE_TDM);
  621. } else {
  622. /* defaultly spi_cs_sel to flash */
  623. config_board_mux(MUX_TYPE_SPIFLASH);
  624. }
  625. if (hwconfig("esdhc"))
  626. config_board_mux(MUX_TYPE_SDHC);
  627. else if (hwconfig("ifc"))
  628. config_board_mux(MUX_TYPE_IFC);
  629. #ifdef CONFIG_TARGET_P1010RDB_PB
  630. setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
  631. #endif
  632. return 0;
  633. }
  634. #ifndef CONFIG_SPL_BUILD
  635. static int pin_mux_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
  636. char *const argv[])
  637. {
  638. if (argc < 2)
  639. return CMD_RET_USAGE;
  640. if (strcmp(argv[1], "ifc") == 0)
  641. config_board_mux(MUX_TYPE_IFC);
  642. else if (strcmp(argv[1], "sdhc") == 0)
  643. config_board_mux(MUX_TYPE_SDHC);
  644. else
  645. return CMD_RET_USAGE;
  646. return 0;
  647. }
  648. U_BOOT_CMD(
  649. mux, 2, 0, pin_mux_cmd,
  650. "configure multiplexing pin for IFC/SDHC bus in runtime",
  651. "bus_type (e.g. mux sdhc)"
  652. );
  653. #endif