mpc8548cds.c 5.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2004, 2007, 2009-2011 Freescale Semiconductor, Inc.
  4. *
  5. * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  6. */
  7. #include <common.h>
  8. #include <init.h>
  9. #include <net.h>
  10. #include <pci.h>
  11. #include <vsprintf.h>
  12. #include <asm/processor.h>
  13. #include <asm/mmu.h>
  14. #include <asm/immap_85xx.h>
  15. #include <asm/fsl_pci.h>
  16. #include <fsl_ddr_sdram.h>
  17. #include <asm/fsl_serdes.h>
  18. #include <miiphy.h>
  19. #include <linux/delay.h>
  20. #include <linux/libfdt.h>
  21. #include <fdt_support.h>
  22. #include <tsec.h>
  23. #include <fsl_mdio.h>
  24. #include <netdev.h>
  25. #include "../common/cadmus.h"
  26. #include "../common/eeprom.h"
  27. #include "../common/via.h"
  28. void local_bus_init(void);
  29. int checkboard (void)
  30. {
  31. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  32. volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
  33. /* PCI slot in USER bits CSR[6:7] by convention. */
  34. uint pci_slot = get_pci_slot ();
  35. uint cpu_board_rev = get_cpu_board_revision ();
  36. puts("Board: MPC8548CDS");
  37. printf(" Carrier Rev: 0x%02x, PCI Slot %d\n",
  38. get_board_version(), pci_slot);
  39. printf(" Daughtercard Rev: %d.%d (0x%04x)\n",
  40. MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
  41. MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
  42. /*
  43. * Initialize local bus.
  44. */
  45. local_bus_init ();
  46. /*
  47. * Hack TSEC 3 and 4 IO voltages.
  48. */
  49. gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
  50. ecm->eedr = 0xffffffff; /* clear ecm errors */
  51. ecm->eeer = 0xffffffff; /* enable ecm errors */
  52. return 0;
  53. }
  54. /*
  55. * Initialize Local Bus
  56. */
  57. void
  58. local_bus_init(void)
  59. {
  60. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  61. volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
  62. uint clkdiv;
  63. sys_info_t sysinfo;
  64. get_sys_info(&sysinfo);
  65. clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
  66. gur->lbiuiplldcr1 = 0x00078080;
  67. if (clkdiv == 16) {
  68. gur->lbiuiplldcr0 = 0x7c0f1bf0;
  69. } else if (clkdiv == 8) {
  70. gur->lbiuiplldcr0 = 0x6c0f1bf0;
  71. } else if (clkdiv == 4) {
  72. gur->lbiuiplldcr0 = 0x5c0f1bf0;
  73. }
  74. lbc->lcrr |= 0x00030000;
  75. asm("sync;isync;msync");
  76. lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
  77. lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
  78. }
  79. /*
  80. * Initialize SDRAM memory on the Local Bus.
  81. */
  82. void lbc_sdram_init(void)
  83. {
  84. #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
  85. uint idx;
  86. volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
  87. uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
  88. uint lsdmr_common;
  89. puts("LBC SDRAM: ");
  90. print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
  91. "\n");
  92. /*
  93. * Setup SDRAM Base and Option Registers
  94. */
  95. set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
  96. set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
  97. lbc->lbcr = CONFIG_SYS_LBC_LBCR;
  98. asm("msync");
  99. lbc->lsrt = CONFIG_SYS_LBC_LSRT;
  100. lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
  101. asm("msync");
  102. /*
  103. * MPC8548 uses "new" 15-16 style addressing.
  104. */
  105. lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
  106. lsdmr_common |= LSDMR_BSMA1516;
  107. /*
  108. * Issue PRECHARGE ALL command.
  109. */
  110. lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
  111. asm("sync;msync");
  112. *sdram_addr = 0xff;
  113. ppcDcbf((unsigned long) sdram_addr);
  114. udelay(100);
  115. /*
  116. * Issue 8 AUTO REFRESH commands.
  117. */
  118. for (idx = 0; idx < 8; idx++) {
  119. lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
  120. asm("sync;msync");
  121. *sdram_addr = 0xff;
  122. ppcDcbf((unsigned long) sdram_addr);
  123. udelay(100);
  124. }
  125. /*
  126. * Issue 8 MODE-set command.
  127. */
  128. lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
  129. asm("sync;msync");
  130. *sdram_addr = 0xff;
  131. ppcDcbf((unsigned long) sdram_addr);
  132. udelay(100);
  133. /*
  134. * Issue NORMAL OP command.
  135. */
  136. lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
  137. asm("sync;msync");
  138. *sdram_addr = 0xff;
  139. ppcDcbf((unsigned long) sdram_addr);
  140. udelay(200); /* Overkill. Must wait > 200 bus cycles */
  141. #endif /* enable SDRAM init */
  142. }
  143. void configure_rgmii(void)
  144. {
  145. unsigned short temp;
  146. /* Change the resistors for the PHY */
  147. /* This is needed to get the RGMII working for the 1.3+
  148. * CDS cards */
  149. if (get_board_version() == 0x13) {
  150. miiphy_write(DEFAULT_MII_NAME,
  151. TSEC1_PHY_ADDR, 29, 18);
  152. miiphy_read(DEFAULT_MII_NAME,
  153. TSEC1_PHY_ADDR, 30, &temp);
  154. temp = (temp & 0xf03f);
  155. temp |= 2 << 9; /* 36 ohm */
  156. temp |= 2 << 6; /* 39 ohm */
  157. miiphy_write(DEFAULT_MII_NAME,
  158. TSEC1_PHY_ADDR, 30, temp);
  159. miiphy_write(DEFAULT_MII_NAME,
  160. TSEC1_PHY_ADDR, 29, 3);
  161. miiphy_write(DEFAULT_MII_NAME,
  162. TSEC1_PHY_ADDR, 30, 0x8000);
  163. }
  164. return;
  165. }
  166. int board_eth_init(struct bd_info *bis)
  167. {
  168. #ifdef CONFIG_TSEC_ENET
  169. struct fsl_pq_mdio_info mdio_info;
  170. struct tsec_info_struct tsec_info[4];
  171. int num = 0;
  172. #ifdef CONFIG_TSEC1
  173. SET_STD_TSEC_INFO(tsec_info[num], 1);
  174. num++;
  175. #endif
  176. #ifdef CONFIG_TSEC2
  177. SET_STD_TSEC_INFO(tsec_info[num], 2);
  178. num++;
  179. #endif
  180. #ifdef CONFIG_TSEC3
  181. /* initialize TSEC3 only if Carrier is 1.3 or above on CDS */
  182. if (get_board_version() >= 0x13) {
  183. SET_STD_TSEC_INFO(tsec_info[num], 3);
  184. tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
  185. num++;
  186. }
  187. #endif
  188. #ifdef CONFIG_TSEC4
  189. /* initialize TSEC4 only if Carrier is 1.3 or above on CDS */
  190. if (get_board_version() >= 0x13) {
  191. SET_STD_TSEC_INFO(tsec_info[num], 4);
  192. tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
  193. num++;
  194. }
  195. #endif
  196. if (!num) {
  197. printf("No TSECs initialized\n");
  198. return 0;
  199. }
  200. mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
  201. mdio_info.name = DEFAULT_MII_NAME;
  202. fsl_pq_mdio_init(bis, &mdio_info);
  203. tsec_eth_init(bis, tsec_info, num);
  204. configure_rgmii();
  205. #endif
  206. return pci_eth_init(bis);
  207. }