cache.h 4.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * ColdFire cache
  4. *
  5. * Copyright 2004-2012 Freescale Semiconductor, Inc.
  6. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  7. */
  8. #ifndef __CACHE_H
  9. #define __CACHE_H
  10. #if defined(CONFIG_MCF520x) || defined(CONFIG_MCF523x) || \
  11. defined(CONFIG_MCF52x2)
  12. #define CONFIG_CF_V2
  13. #endif
  14. #if defined(CONFIG_MCF530x) || defined(CONFIG_MCF532x) || \
  15. defined(CONFIG_MCF5301x)
  16. #define CONFIG_CF_V3
  17. #endif
  18. #if defined(CONFIG_MCF5441x)
  19. #define CONFIG_CF_V4E /* Four Extra ACRn */
  20. #endif
  21. /* ***** CACR ***** */
  22. /* V2 Core */
  23. #ifdef CONFIG_CF_V2
  24. #define CF_CACR_CENB (1 << 31)
  25. #define CF_CACR_CPD (1 << 28)
  26. #define CF_CACR_CFRZ (1 << 27)
  27. #define CF_CACR_CEIB (1 << 10)
  28. #define CF_CACR_DCM (1 << 9)
  29. #define CF_CACR_DBWE (1 << 8)
  30. #if defined(CONFIG_MCF5249) || defined(CONFIG_MCF5253)
  31. #define CF_CACR_DWP (1 << 6)
  32. #else
  33. #define CF_CACR_CINV (1 << 24)
  34. #define CF_CACR_DISI (1 << 23)
  35. #define CF_CACR_DISD (1 << 22)
  36. #define CF_CACR_INVI (1 << 21)
  37. #define CF_CACR_INVD (1 << 20)
  38. #define CF_CACR_DWP (1 << 5)
  39. #define CF_CACR_EUSP (1 << 4)
  40. #endif /* CONFIG_MCF5249 || CONFIG_MCF5253 */
  41. #endif /* CONFIG_CF_V2 */
  42. /* V3 Core */
  43. #ifdef CONFIG_CF_V3
  44. #define CF_CACR_EC (1 << 31)
  45. #define CF_CACR_ESB (1 << 29)
  46. #define CF_CACR_DPI (1 << 28)
  47. #define CF_CACR_HLCK (1 << 27)
  48. #define CF_CACR_CINVA (1 << 24)
  49. #define CF_CACR_DNFB (1 << 10)
  50. #define CF_CACR_DCM_UNMASK 0xFFFFFCFF
  51. #define CF_CACR_DCM_WT (0 << 8)
  52. #define CF_CACR_DCM_CB (1 << 8)
  53. #define CF_CACR_DCM_P (2 << 8)
  54. #define CF_CACR_DCM_IP (3 << 8)
  55. #define CF_CACR_DW (1 << 5)
  56. #define CF_CACR_EUSP (1 << 4)
  57. #endif /* CONFIG_CF_V3 */
  58. /* V4 Core */
  59. #if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
  60. #define CF_CACR_DEC (1 << 31)
  61. #define CF_CACR_DW (1 << 30)
  62. #define CF_CACR_DESB (1 << 29)
  63. #define CF_CACR_DDPI (1 << 28)
  64. #define CF_CACR_DHLCK (1 << 27)
  65. #define CF_CACR_DDCM_UNMASK (0xF9FFFFFF)
  66. #define CF_CACR_DDCM_WT (0 << 25)
  67. #define CF_CACR_DDCM_CB (1 << 25)
  68. #define CF_CACR_DDCM_P (2 << 25)
  69. #define CF_CACR_DDCM_IP (3 << 25)
  70. #define CF_CACR_DCINVA (1 << 24)
  71. #define CF_CACR_DDSP (1 << 23)
  72. #define CF_CACR_BEC (1 << 19)
  73. #define CF_CACR_BCINVA (1 << 18)
  74. #define CF_CACR_IEC (1 << 15)
  75. #define CF_CACR_DNFB (1 << 13)
  76. #define CF_CACR_IDPI (1 << 12)
  77. #define CF_CACR_IHLCK (1 << 11)
  78. #define CF_CACR_IDCM (1 << 10)
  79. #define CF_CACR_ICINVA (1 << 8)
  80. #define CF_CACR_IDSP (1 << 7)
  81. #define CF_CACR_EUSP (1 << 5)
  82. #if defined(CONFIG_MCF5445x) || defined(CONFIG_MCF5441x)
  83. #define CF_CACR_IVO (1 << 20)
  84. #define CF_CACR_SPA (1 << 14)
  85. #else
  86. #define CF_CACR_DF (1 << 4)
  87. #endif
  88. #endif /* CONFIG_CF_V4 */
  89. /* ***** ACR ***** */
  90. #define CF_ACR_ADR_UNMASK (0x00FFFFFF)
  91. #define CF_ACR_ADR(x) ((x & 0xFF) << 24)
  92. #define CF_ACR_ADRMSK_UNMASK (0xFF00FFFF)
  93. #define CF_ACR_ADRMSK(x) ((x & 0xFF) << 16)
  94. #define CF_ACR_EN (1 << 15)
  95. #define CF_ACR_SM_UNMASK (0xFFFF9FFF)
  96. #define CF_ACR_SM_UM (0 << 13)
  97. #define CF_ACR_SM_SM (1 << 13)
  98. #define CF_ACR_SM_ALL (3 << 13)
  99. #define CF_ACR_WP (1 << 2)
  100. /* V2 Core */
  101. #ifdef CONFIG_CF_V2
  102. #define CF_ACR_CM (1 << 6)
  103. #define CF_ACR_BWE (1 << 5)
  104. #else
  105. /* V3 & V4 */
  106. #define CF_ACR_CM_UNMASK (0xFFFFFF9F)
  107. #define CF_ACR_CM_WT (0 << 5)
  108. #define CF_ACR_CM_CB (1 << 5)
  109. #define CF_ACR_CM_P (2 << 5)
  110. #define CF_ACR_CM_IP (3 << 5)
  111. #endif /* CONFIG_CF_V2 */
  112. /* V4 Core */
  113. #if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
  114. #define CF_ACR_AMM (1 << 10)
  115. #define CF_ACR_SP (1 << 3)
  116. #endif /* CONFIG_CF_V4 */
  117. #ifndef CONFIG_SYS_CACHE_ICACR
  118. #define CONFIG_SYS_CACHE_ICACR 0
  119. #endif
  120. #ifndef CONFIG_SYS_CACHE_DCACR
  121. #ifdef CONFIG_SYS_CACHE_ICACR
  122. #define CONFIG_SYS_CACHE_DCACR CONFIG_SYS_CACHE_ICACR
  123. #else
  124. #define CONFIG_SYS_CACHE_DCACR 0
  125. #endif
  126. #endif
  127. #ifndef CONFIG_SYS_CACHE_ACR0
  128. #define CONFIG_SYS_CACHE_ACR0 0
  129. #endif
  130. #ifndef CONFIG_SYS_CACHE_ACR1
  131. #define CONFIG_SYS_CACHE_ACR1 0
  132. #endif
  133. #ifndef CONFIG_SYS_CACHE_ACR2
  134. #define CONFIG_SYS_CACHE_ACR2 0
  135. #endif
  136. #ifndef CONFIG_SYS_CACHE_ACR3
  137. #define CONFIG_SYS_CACHE_ACR3 0
  138. #endif
  139. #ifndef CONFIG_SYS_CACHE_ACR4
  140. #define CONFIG_SYS_CACHE_ACR4 0
  141. #endif
  142. #ifndef CONFIG_SYS_CACHE_ACR5
  143. #define CONFIG_SYS_CACHE_ACR5 0
  144. #endif
  145. #ifndef CONFIG_SYS_CACHE_ACR6
  146. #define CONFIG_SYS_CACHE_ACR6 0
  147. #endif
  148. #ifndef CONFIG_SYS_CACHE_ACR7
  149. #define CONFIG_SYS_CACHE_ACR7 0
  150. #endif
  151. #define CF_ADDRMASK(x) (((x > 0x10) ? ((x >> 4) - 1) : (x)) << 16)
  152. #ifndef __ASSEMBLY__ /* put C only stuff in this section */
  153. void icache_invalid(void);
  154. void dcache_invalid(void);
  155. #endif
  156. /*
  157. * m68k uses 16 byte L1 data cache line sizes. Use this for DMA buffer
  158. * alignment unless the board configuration has specified a new value.
  159. */
  160. #ifdef CONFIG_SYS_CACHELINE_SIZE
  161. #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
  162. #else
  163. #define ARCH_DMA_MINALIGN 16
  164. #endif
  165. #endif /* __CACHE_H */