Kconfig 11 KB

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  1. menu "MIPS architecture"
  2. depends on MIPS
  3. config SYS_ARCH
  4. default "mips"
  5. config SYS_CPU
  6. default "mips32" if CPU_MIPS32
  7. default "mips64" if CPU_MIPS64
  8. choice
  9. prompt "Target select"
  10. optional
  11. config TARGET_QEMU_MIPS
  12. bool "Support qemu-mips"
  13. select ROM_EXCEPTION_VECTORS
  14. select SUPPORTS_BIG_ENDIAN
  15. select SUPPORTS_CPU_MIPS32_R1
  16. select SUPPORTS_CPU_MIPS32_R2
  17. select SUPPORTS_CPU_MIPS64_R1
  18. select SUPPORTS_CPU_MIPS64_R2
  19. select SUPPORTS_LITTLE_ENDIAN
  20. config TARGET_MALTA
  21. bool "Support malta"
  22. select DM
  23. select DM_SERIAL
  24. select DYNAMIC_IO_PORT_BASE
  25. select MIPS_CM
  26. select MIPS_INSERT_BOOT_CONFIG
  27. select MIPS_L1_CACHE_SHIFT_6
  28. select MIPS_L2_CACHE
  29. select OF_CONTROL
  30. select OF_ISA_BUS
  31. select ROM_EXCEPTION_VECTORS
  32. select SUPPORTS_BIG_ENDIAN
  33. select SUPPORTS_CPU_MIPS32_R1
  34. select SUPPORTS_CPU_MIPS32_R2
  35. select SUPPORTS_CPU_MIPS32_R6
  36. select SUPPORTS_CPU_MIPS64_R1
  37. select SUPPORTS_CPU_MIPS64_R2
  38. select SUPPORTS_CPU_MIPS64_R6
  39. select SUPPORTS_LITTLE_ENDIAN
  40. select SWAP_IO_SPACE
  41. imply CMD_DM
  42. config TARGET_VCT
  43. bool "Support vct"
  44. select ROM_EXCEPTION_VECTORS
  45. select SUPPORTS_BIG_ENDIAN
  46. select SUPPORTS_CPU_MIPS32_R1
  47. select SUPPORTS_CPU_MIPS32_R2
  48. select SYS_MIPS_CACHE_INIT_RAM_LOAD
  49. config ARCH_ATH79
  50. bool "Support QCA/Atheros ath79"
  51. select DM
  52. select OF_CONTROL
  53. imply CMD_DM
  54. config ARCH_BMIPS
  55. bool "Support BMIPS SoCs"
  56. select CLK
  57. select CPU
  58. select DM
  59. select OF_CONTROL
  60. select RAM
  61. select SYSRESET
  62. imply CMD_DM
  63. config ARCH_MT7620
  64. bool "Support MT7620/7688 SoCs"
  65. imply CMD_DM
  66. select DISPLAY_CPUINFO
  67. select DM
  68. select DM_SERIAL
  69. imply DM_SPI
  70. imply DM_SPI_FLASH
  71. select MIPS_TUNE_24KC
  72. select OF_CONTROL
  73. select ROM_EXCEPTION_VECTORS
  74. select SUPPORTS_CPU_MIPS32_R1
  75. select SUPPORTS_CPU_MIPS32_R2
  76. select SUPPORTS_LITTLE_ENDIAN
  77. select SYSRESET
  78. config MACH_PIC32
  79. bool "Support Microchip PIC32"
  80. select DM
  81. select OF_CONTROL
  82. imply CMD_DM
  83. config TARGET_BOSTON
  84. bool "Support Boston"
  85. select DM
  86. select DM_SERIAL
  87. select MIPS_CM
  88. select MIPS_L1_CACHE_SHIFT_6
  89. select MIPS_L2_CACHE
  90. select OF_BOARD_SETUP
  91. select OF_CONTROL
  92. select ROM_EXCEPTION_VECTORS
  93. select SUPPORTS_BIG_ENDIAN
  94. select SUPPORTS_CPU_MIPS32_R1
  95. select SUPPORTS_CPU_MIPS32_R2
  96. select SUPPORTS_CPU_MIPS32_R6
  97. select SUPPORTS_CPU_MIPS64_R1
  98. select SUPPORTS_CPU_MIPS64_R2
  99. select SUPPORTS_CPU_MIPS64_R6
  100. select SUPPORTS_LITTLE_ENDIAN
  101. imply CMD_DM
  102. config TARGET_XILFPGA
  103. bool "Support Imagination Xilfpga"
  104. select DM
  105. select DM_ETH
  106. select DM_GPIO
  107. select DM_SERIAL
  108. select MIPS_L1_CACHE_SHIFT_4
  109. select OF_CONTROL
  110. select ROM_EXCEPTION_VECTORS
  111. select SUPPORTS_CPU_MIPS32_R1
  112. select SUPPORTS_CPU_MIPS32_R2
  113. select SUPPORTS_LITTLE_ENDIAN
  114. imply CMD_DM
  115. help
  116. This supports IMGTEC MIPSfpga platform
  117. endchoice
  118. source "board/imgtec/boston/Kconfig"
  119. source "board/imgtec/malta/Kconfig"
  120. source "board/imgtec/xilfpga/Kconfig"
  121. source "board/micronas/vct/Kconfig"
  122. source "board/qemu-mips/Kconfig"
  123. source "arch/mips/mach-ath79/Kconfig"
  124. source "arch/mips/mach-bmips/Kconfig"
  125. source "arch/mips/mach-pic32/Kconfig"
  126. source "arch/mips/mach-mt7620/Kconfig"
  127. if MIPS
  128. choice
  129. prompt "Endianness selection"
  130. help
  131. Some MIPS boards can be configured for either little or big endian
  132. byte order. These modes require different U-Boot images. In general there
  133. is one preferred byteorder for a particular system but some systems are
  134. just as commonly used in the one or the other endianness.
  135. config SYS_BIG_ENDIAN
  136. bool "Big endian"
  137. depends on SUPPORTS_BIG_ENDIAN
  138. config SYS_LITTLE_ENDIAN
  139. bool "Little endian"
  140. depends on SUPPORTS_LITTLE_ENDIAN
  141. endchoice
  142. choice
  143. prompt "CPU selection"
  144. default CPU_MIPS32_R2
  145. config CPU_MIPS32_R1
  146. bool "MIPS32 Release 1"
  147. depends on SUPPORTS_CPU_MIPS32_R1
  148. select 32BIT
  149. help
  150. Choose this option to build an U-Boot for release 1 through 5 of the
  151. MIPS32 architecture.
  152. config CPU_MIPS32_R2
  153. bool "MIPS32 Release 2"
  154. depends on SUPPORTS_CPU_MIPS32_R2
  155. select 32BIT
  156. help
  157. Choose this option to build an U-Boot for release 2 through 5 of the
  158. MIPS32 architecture.
  159. config CPU_MIPS32_R6
  160. bool "MIPS32 Release 6"
  161. depends on SUPPORTS_CPU_MIPS32_R6
  162. select 32BIT
  163. help
  164. Choose this option to build an U-Boot for release 6 or later of the
  165. MIPS32 architecture.
  166. config CPU_MIPS64_R1
  167. bool "MIPS64 Release 1"
  168. depends on SUPPORTS_CPU_MIPS64_R1
  169. select 64BIT
  170. help
  171. Choose this option to build a kernel for release 1 through 5 of the
  172. MIPS64 architecture.
  173. config CPU_MIPS64_R2
  174. bool "MIPS64 Release 2"
  175. depends on SUPPORTS_CPU_MIPS64_R2
  176. select 64BIT
  177. help
  178. Choose this option to build a kernel for release 2 through 5 of the
  179. MIPS64 architecture.
  180. config CPU_MIPS64_R6
  181. bool "MIPS64 Release 6"
  182. depends on SUPPORTS_CPU_MIPS64_R6
  183. select 64BIT
  184. help
  185. Choose this option to build a kernel for release 6 or later of the
  186. MIPS64 architecture.
  187. endchoice
  188. menu "General setup"
  189. config ROM_EXCEPTION_VECTORS
  190. bool "Build U-Boot image with exception vectors"
  191. help
  192. Enable this to include exception vectors in the U-Boot image. This is
  193. required if the U-Boot entry point is equal to the address of the
  194. CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
  195. U-Boot booted from parallel NOR flash).
  196. Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
  197. In that case the image size will be reduced by 0x500 bytes.
  198. config MIPS_CM_BASE
  199. hex "MIPS CM GCR Base Address"
  200. depends on MIPS_CM
  201. default 0x16100000 if TARGET_BOSTON
  202. default 0x1fbf8000
  203. help
  204. The physical base address at which to map the MIPS Coherence Manager
  205. Global Configuration Registers (GCRs). This should be set such that
  206. the GCRs occupy a region of the physical address space which is
  207. otherwise unused, or at minimum that software doesn't need to access.
  208. config MIPS_CACHE_INDEX_BASE
  209. hex "Index base address for cache initialisation"
  210. default 0x80000000 if CPU_MIPS32
  211. default 0xffffffff80000000 if CPU_MIPS64
  212. help
  213. This is the base address for a memory block, which is used for
  214. initialising the cache lines. This is also the base address of a memory
  215. block which is used for loading and filling cache lines when
  216. SYS_MIPS_CACHE_INIT_RAM_LOAD is selected.
  217. Normally this is CKSEG0. If the MIPS system needs to move this block
  218. to some SRAM or ScratchPad RAM, adapt this option accordingly.
  219. config MIPS_RELOCATION_TABLE_SIZE
  220. hex "Relocation table size"
  221. range 0x100 0x10000
  222. default "0x8000"
  223. ---help---
  224. A table of relocation data will be appended to the U-Boot binary
  225. and parsed in relocate_code() to fix up all offsets in the relocated
  226. U-Boot.
  227. This option allows the amount of space reserved for the table to be
  228. adjusted in a range from 256 up to 64k. The default is 32k and should
  229. be ok in most cases. Reduce this value to shrink the size of U-Boot
  230. binary.
  231. The build will fail and a valid size suggested if this is too small.
  232. If unsure, leave at the default value.
  233. endmenu
  234. menu "OS boot interface"
  235. config MIPS_BOOT_CMDLINE_LEGACY
  236. bool "Hand over legacy command line to Linux kernel"
  237. default y
  238. help
  239. Enable this option if you want U-Boot to hand over the Yamon-style
  240. command line to the kernel. All bootargs will be prepared as argc/argv
  241. compatible list. The argument count (argc) is stored in register $a0.
  242. The address of the argument list (argv) is stored in register $a1.
  243. config MIPS_BOOT_ENV_LEGACY
  244. bool "Hand over legacy environment to Linux kernel"
  245. default y
  246. help
  247. Enable this option if you want U-Boot to hand over the Yamon-style
  248. environment to the kernel. Information like memory size, initrd
  249. address and size will be prepared as zero-terminated key/value list.
  250. The address of the environment is stored in register $a2.
  251. config MIPS_BOOT_FDT
  252. bool "Hand over a flattened device tree to Linux kernel"
  253. default n
  254. help
  255. Enable this option if you want U-Boot to hand over a flattened
  256. device tree to the kernel. According to UHI register $a0 will be set
  257. to -2 and the FDT address is stored in $a1.
  258. endmenu
  259. config SUPPORTS_BIG_ENDIAN
  260. bool
  261. config SUPPORTS_LITTLE_ENDIAN
  262. bool
  263. config SUPPORTS_CPU_MIPS32_R1
  264. bool
  265. config SUPPORTS_CPU_MIPS32_R2
  266. bool
  267. config SUPPORTS_CPU_MIPS32_R6
  268. bool
  269. config SUPPORTS_CPU_MIPS64_R1
  270. bool
  271. config SUPPORTS_CPU_MIPS64_R2
  272. bool
  273. config SUPPORTS_CPU_MIPS64_R6
  274. bool
  275. config CPU_MIPS32
  276. bool
  277. default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
  278. config CPU_MIPS64
  279. bool
  280. default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
  281. config MIPS_TUNE_4KC
  282. bool
  283. config MIPS_TUNE_14KC
  284. bool
  285. config MIPS_TUNE_24KC
  286. bool
  287. config MIPS_TUNE_34KC
  288. bool
  289. config MIPS_TUNE_74KC
  290. bool
  291. config 32BIT
  292. bool
  293. config 64BIT
  294. bool
  295. config SWAP_IO_SPACE
  296. bool
  297. config SYS_MIPS_CACHE_INIT_RAM_LOAD
  298. bool
  299. config MIPS_INIT_STACK_IN_SRAM
  300. bool
  301. default n
  302. help
  303. Select this if the initial stack frame could be setup in SRAM.
  304. Normally the initial stack frame is set up in DRAM which is often
  305. only available after lowlevel_init. With this option the initial
  306. stack frame and the early C environment is set up before
  307. lowlevel_init. Thus lowlevel_init does not need to be implemented
  308. in assembler.
  309. config SYS_DCACHE_SIZE
  310. int
  311. default 0
  312. help
  313. The total size of the L1 Dcache, if known at compile time.
  314. config SYS_DCACHE_LINE_SIZE
  315. int
  316. default 0
  317. help
  318. The size of L1 Dcache lines, if known at compile time.
  319. config SYS_ICACHE_SIZE
  320. int
  321. default 0
  322. help
  323. The total size of the L1 ICache, if known at compile time.
  324. config SYS_ICACHE_LINE_SIZE
  325. int
  326. default 0
  327. help
  328. The size of L1 Icache lines, if known at compile time.
  329. config SYS_CACHE_SIZE_AUTO
  330. def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
  331. SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
  332. help
  333. Select this (or let it be auto-selected by not defining any cache
  334. sizes) in order to allow U-Boot to automatically detect the sizes
  335. of caches at runtime. This has a small cost in code size & runtime
  336. so if you know the cache configuration for your system at compile
  337. time it would be beneficial to configure it.
  338. config MIPS_L1_CACHE_SHIFT_4
  339. bool
  340. config MIPS_L1_CACHE_SHIFT_5
  341. bool
  342. config MIPS_L1_CACHE_SHIFT_6
  343. bool
  344. config MIPS_L1_CACHE_SHIFT_7
  345. bool
  346. config MIPS_L1_CACHE_SHIFT
  347. int
  348. default "7" if MIPS_L1_CACHE_SHIFT_7
  349. default "6" if MIPS_L1_CACHE_SHIFT_6
  350. default "5" if MIPS_L1_CACHE_SHIFT_5
  351. default "4" if MIPS_L1_CACHE_SHIFT_4
  352. default "5"
  353. config MIPS_L2_CACHE
  354. bool
  355. help
  356. Select this if your system includes an L2 cache and you want U-Boot
  357. to initialise & maintain it.
  358. config DYNAMIC_IO_PORT_BASE
  359. bool
  360. config MIPS_CM
  361. bool
  362. help
  363. Select this if your system contains a MIPS Coherence Manager and you
  364. wish U-Boot to configure it or make use of it to retrieve system
  365. information such as cache configuration.
  366. config MIPS_INSERT_BOOT_CONFIG
  367. bool
  368. default n
  369. help
  370. Enable this to insert some board-specific boot configuration in
  371. the U-Boot binary at offset 0x10.
  372. config MIPS_BOOT_CONFIG_WORD0
  373. hex
  374. depends on MIPS_INSERT_BOOT_CONFIG
  375. default 0x420 if TARGET_MALTA
  376. default 0x0
  377. help
  378. Value which is inserted as boot config word 0.
  379. config MIPS_BOOT_CONFIG_WORD1
  380. hex
  381. depends on MIPS_INSERT_BOOT_CONFIG
  382. default 0x0
  383. help
  384. Value which is inserted as boot config word 1.
  385. endif
  386. endmenu