README.x86 47 KB

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  1. # SPDX-License-Identifier: GPL-2.0+
  2. #
  3. # Copyright (C) 2014, Simon Glass <sjg@chromium.org>
  4. # Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
  5. U-Boot on x86
  6. =============
  7. This document describes the information about U-Boot running on x86 targets,
  8. including supported boards, build instructions, todo list, etc.
  9. Status
  10. ------
  11. U-Boot supports running as a coreboot [1] payload on x86. So far only Link
  12. (Chromebook Pixel) and QEMU [2] x86 targets have been tested, but it should
  13. work with minimal adjustments on other x86 boards since coreboot deals with
  14. most of the low-level details.
  15. U-Boot is a main bootloader on Intel Edison board.
  16. U-Boot also supports booting directly from x86 reset vector, without coreboot.
  17. In this case, known as bare mode, from the fact that it runs on the
  18. 'bare metal', U-Boot acts like a BIOS replacement. The following platforms
  19. are supported:
  20. - Bayley Bay CRB
  21. - Cherry Hill CRB
  22. - Congatec QEVAL 2.0 & conga-QA3/E3845
  23. - Cougar Canyon 2 CRB
  24. - Crown Bay CRB
  25. - Galileo
  26. - Link (Chromebook Pixel)
  27. - Minnowboard MAX
  28. - Samus (Chromebook Pixel 2015)
  29. - QEMU x86 (32-bit & 64-bit)
  30. As for loading an OS, U-Boot supports directly booting a 32-bit or 64-bit
  31. Linux kernel as part of a FIT image. It also supports a compressed zImage.
  32. U-Boot supports loading an x86 VxWorks kernel. Please check README.vxworks
  33. for more details.
  34. Build Instructions for U-Boot as coreboot payload
  35. -------------------------------------------------
  36. Building U-Boot as a coreboot payload is just like building U-Boot for targets
  37. on other architectures, like below:
  38. $ make coreboot_defconfig
  39. $ make all
  40. Build Instructions for U-Boot as main bootloader
  41. ------------------------------------------------
  42. Intel Edison instructions:
  43. Simple you can build U-Boot and obtain u-boot.bin
  44. $ make edison_defconfig
  45. $ make all
  46. Build Instructions for U-Boot as BIOS replacement (bare mode)
  47. -------------------------------------------------------------
  48. Building a ROM version of U-Boot (hereafter referred to as u-boot.rom) is a
  49. little bit tricky, as generally it requires several binary blobs which are not
  50. shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is
  51. not turned on by default in the U-Boot source tree. Firstly, you need turn it
  52. on by enabling the ROM build either via an environment variable
  53. $ export BUILD_ROM=y
  54. or via configuration
  55. CONFIG_BUILD_ROM=y
  56. Both tell the Makefile to build u-boot.rom as a target.
  57. ---
  58. Chromebook Link specific instructions for bare mode:
  59. First, you need the following binary blobs:
  60. * descriptor.bin - Intel flash descriptor
  61. * me.bin - Intel Management Engine
  62. * mrc.bin - Memory Reference Code, which sets up SDRAM
  63. * video ROM - sets up the display
  64. You can get these binary blobs by:
  65. $ git clone http://review.coreboot.org/p/blobs.git
  66. $ cd blobs
  67. Find the following files:
  68. * ./mainboard/google/link/descriptor.bin
  69. * ./mainboard/google/link/me.bin
  70. * ./northbridge/intel/sandybridge/systemagent-r6.bin
  71. The 3rd one should be renamed to mrc.bin.
  72. As for the video ROM, you can get it here [3] and rename it to vga.bin.
  73. Make sure all these binary blobs are put in the board directory.
  74. Now you can build U-Boot and obtain u-boot.rom:
  75. $ make chromebook_link_defconfig
  76. $ make all
  77. ---
  78. Chromebook Samus (2015 Pixel) instructions for bare mode:
  79. First, you need the following binary blobs:
  80. * descriptor.bin - Intel flash descriptor
  81. * me.bin - Intel Management Engine
  82. * mrc.bin - Memory Reference Code, which sets up SDRAM
  83. * refcode.elf - Additional Reference code
  84. * vga.bin - video ROM, which sets up the display
  85. If you have a samus you can obtain them from your flash, for example, in
  86. developer mode on the Chromebook (use Ctrl-Alt-F2 to obtain a terminal and
  87. log in as 'root'):
  88. cd /tmp
  89. flashrom -w samus.bin
  90. scp samus.bin username@ip_address:/path/to/somewhere
  91. If not see the coreboot tree [4] where you can use:
  92. bash crosfirmware.sh samus
  93. to get the image. There is also an 'extract_blobs.sh' scripts that you can use
  94. on the 'coreboot-Google_Samus.*' file to short-circuit some of the below.
  95. Then 'ifdtool -x samus.bin' on your development machine will produce:
  96. flashregion_0_flashdescriptor.bin
  97. flashregion_1_bios.bin
  98. flashregion_2_intel_me.bin
  99. Rename flashregion_0_flashdescriptor.bin to descriptor.bin
  100. Rename flashregion_2_intel_me.bin to me.bin
  101. You can ignore flashregion_1_bios.bin - it is not used.
  102. To get the rest, use 'cbfstool samus.bin print':
  103. samus.bin: 8192 kB, bootblocksize 2864, romsize 8388608, offset 0x700000
  104. alignment: 64 bytes, architecture: x86
  105. Name Offset Type Size
  106. cmos_layout.bin 0x700000 cmos_layout 1164
  107. pci8086,0406.rom 0x7004c0 optionrom 65536
  108. spd.bin 0x710500 (unknown) 4096
  109. cpu_microcode_blob.bin 0x711540 microcode 70720
  110. fallback/romstage 0x722a00 stage 54210
  111. fallback/ramstage 0x72fe00 stage 96382
  112. config 0x7476c0 raw 6075
  113. fallback/vboot 0x748ec0 stage 15980
  114. fallback/refcode 0x74cd80 stage 75578
  115. fallback/payload 0x75f500 payload 62878
  116. u-boot.dtb 0x76eb00 (unknown) 5318
  117. (empty) 0x770000 null 196504
  118. mrc.bin 0x79ffc0 (unknown) 222876
  119. (empty) 0x7d66c0 null 167320
  120. You can extract what you need:
  121. cbfstool samus.bin extract -n pci8086,0406.rom -f vga.bin
  122. cbfstool samus.bin extract -n fallback/refcode -f refcode.rmod
  123. cbfstool samus.bin extract -n mrc.bin -f mrc.bin
  124. cbfstool samus.bin extract -n fallback/refcode -f refcode.bin -U
  125. Note that the -U flag is only supported by the latest cbfstool. It unpacks
  126. and decompresses the stage to produce a coreboot rmodule. This is a simple
  127. representation of an ELF file. You need the patch "Support decoding a stage
  128. with compression".
  129. Put all 5 files into board/google/chromebook_samus.
  130. Now you can build U-Boot and obtain u-boot.rom:
  131. $ make chromebook_link_defconfig
  132. $ make all
  133. If you are using em100, then this command will flash write -Boot:
  134. em100 -s -d filename.rom -c W25Q64CV -r
  135. ---
  136. Intel Crown Bay specific instructions for bare mode:
  137. U-Boot support of Intel Crown Bay board [4] relies on a binary blob called
  138. Firmware Support Package [5] to perform all the necessary initialization steps
  139. as documented in the BIOS Writer Guide, including initialization of the CPU,
  140. memory controller, chipset and certain bus interfaces.
  141. Download the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T,
  142. install it on your host and locate the FSP binary blob. Note this platform
  143. also requires a Chipset Micro Code (CMC) state machine binary to be present in
  144. the SPI flash where u-boot.rom resides, and this CMC binary blob can be found
  145. in this FSP package too.
  146. * ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd
  147. * ./Microcode/C0_22211.BIN
  148. Rename the first one to fsp.bin and second one to cmc.bin and put them in the
  149. board directory.
  150. Note the FSP release version 001 has a bug which could cause random endless
  151. loop during the FspInit call. This bug was published by Intel although Intel
  152. did not describe any details. We need manually apply the patch to the FSP
  153. binary using any hex editor (eg: bvi). Go to the offset 0x1fcd8 of the FSP
  154. binary, change the following five bytes values from orginally E8 42 FF FF FF
  155. to B8 00 80 0B 00.
  156. As for the video ROM, you need manually extract it from the Intel provided
  157. BIOS for Crown Bay here [6], using the AMI MMTool [7]. Check PCI option ROM
  158. ID 8086:4108, extract and save it as vga.bin in the board directory.
  159. Now you can build U-Boot and obtain u-boot.rom
  160. $ make crownbay_defconfig
  161. $ make all
  162. ---
  163. Intel Cougar Canyon 2 specific instructions for bare mode:
  164. This uses Intel FSP for 3rd generation Intel Core and Intel Celeron processors
  165. with mobile Intel HM76 and QM77 chipsets platform. Download it from Intel FSP
  166. website and put the .fd file (CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013.fd at the
  167. time of writing) in the board directory and rename it to fsp.bin.
  168. Now build U-Boot and obtain u-boot.rom
  169. $ make cougarcanyon2_defconfig
  170. $ make all
  171. The board has two 8MB SPI flashes mounted, which are called SPI-0 and SPI-1 in
  172. the board manual. The SPI-0 flash should have flash descriptor plus ME firmware
  173. and SPI-1 flash is used to store U-Boot. For convenience, the complete 8MB SPI-0
  174. flash image is included in the FSP package (named Rom00_8M_MB_PPT.bin). Program
  175. this image to the SPI-0 flash according to the board manual just once and we are
  176. all set. For programming U-Boot we just need to program SPI-1 flash. Since the
  177. default u-boot.rom image for this board is set to 2MB, it should be programmed
  178. to the last 2MB of the 8MB chip, address range [600000, 7FFFFF].
  179. ---
  180. Intel Bay Trail based board instructions for bare mode:
  181. This uses as FSP as with Crown Bay, except it is for the Atom E3800 series.
  182. Two boards that use this configuration are Bayley Bay and Minnowboard MAX.
  183. Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at
  184. the time of writing). Put it in the corresponding board directory and rename
  185. it to fsp.bin.
  186. Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same
  187. board directory as vga.bin.
  188. You still need two more binary blobs. For Bayley Bay, they can be extracted
  189. from the sample SPI image provided in the FSP (SPI.bin at the time of writing).
  190. $ ./tools/ifdtool -x BayleyBay/SPI.bin
  191. $ cp flashregion_0_flashdescriptor.bin board/intel/bayleybay/descriptor.bin
  192. $ cp flashregion_2_intel_me.bin board/intel/bayleybay/me.bin
  193. For Minnowboard MAX, we can reuse the same ME firmware above, but for flash
  194. descriptor, we need get that somewhere else, as the one above does not seem to
  195. work, probably because it is not designed for the Minnowboard MAX. Now download
  196. the original firmware image for this board from:
  197. http://firmware.intel.com/sites/default/files/2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip
  198. Unzip it:
  199. $ unzip 2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip
  200. Use ifdtool in the U-Boot tools directory to extract the images from that
  201. file, for example:
  202. $ ./tools/ifdtool -x MNW2MAX1.X64.0073.R02.1409160934.bin
  203. This will provide the descriptor file - copy this into the correct place:
  204. $ cp flashregion_0_flashdescriptor.bin board/intel/minnowmax/descriptor.bin
  205. Now you can build U-Boot and obtain u-boot.rom
  206. Note: below are examples/information for Minnowboard MAX.
  207. $ make minnowmax_defconfig
  208. $ make all
  209. Checksums are as follows (but note that newer versions will invalidate this):
  210. $ md5sum -b board/intel/minnowmax/*.bin
  211. ffda9a3b94df5b74323afb328d51e6b4 board/intel/minnowmax/descriptor.bin
  212. 69f65b9a580246291d20d08cbef9d7c5 board/intel/minnowmax/fsp.bin
  213. 894a97d371544ec21de9c3e8e1716c4b board/intel/minnowmax/me.bin
  214. a2588537da387da592a27219d56e9962 board/intel/minnowmax/vga.bin
  215. The ROM image is broken up into these parts:
  216. Offset Description Controlling config
  217. ------------------------------------------------------------
  218. 000000 descriptor.bin Hard-coded to 0 in ifdtool
  219. 001000 me.bin Set by the descriptor
  220. 500000 <spare>
  221. 6ef000 Environment CONFIG_ENV_OFFSET
  222. 6f0000 MRC cache CONFIG_ENABLE_MRC_CACHE
  223. 700000 u-boot-dtb.bin CONFIG_SYS_TEXT_BASE
  224. 7b0000 vga.bin CONFIG_VGA_BIOS_ADDR
  225. 7c0000 fsp.bin CONFIG_FSP_ADDR
  226. 7f8000 <spare> (depends on size of fsp.bin)
  227. 7ff800 U-Boot 16-bit boot CONFIG_SYS_X86_START16
  228. Overall ROM image size is controlled by CONFIG_ROM_SIZE.
  229. Note that the debug version of the FSP is bigger in size. If this version
  230. is used, CONFIG_FSP_ADDR needs to be configured to 0xfffb0000 instead of
  231. the default value 0xfffc0000.
  232. ---
  233. Intel Cherry Hill specific instructions for bare mode:
  234. This uses Intel FSP for Braswell platform. Download it from Intel FSP website,
  235. put the .fd file to the board directory and rename it to fsp.bin.
  236. Extract descriptor.bin and me.bin from the original BIOS on the board using
  237. ifdtool and put them to the board directory as well.
  238. Note the FSP package for Braswell does not ship a traditional legacy VGA BIOS
  239. image for the integrated graphics device. Instead a new binary called Video
  240. BIOS Table (VBT) is shipped. Put it to the board directory and rename it to
  241. vbt.bin if you want graphics support in U-Boot.
  242. Now you can build U-Boot and obtain u-boot.rom
  243. $ make cherryhill_defconfig
  244. $ make all
  245. An important note for programming u-boot.rom to the on-board SPI flash is that
  246. you need make sure the SPI flash's 'quad enable' bit in its status register
  247. matches the settings in the descriptor.bin, otherwise the board won't boot.
  248. For the on-board SPI flash MX25U6435F, this can be done by writing 0x40 to the
  249. status register by DediProg in: Config > Modify Status Register > Write Status
  250. Register(s) > Register1 Value(Hex). This is is a one-time change. Once set, it
  251. persists in SPI flash part regardless of the u-boot.rom image burned.
  252. ---
  253. Intel Galileo instructions for bare mode:
  254. Only one binary blob is needed for Remote Management Unit (RMU) within Intel
  255. Quark SoC. Not like FSP, U-Boot does not call into the binary. The binary is
  256. needed by the Quark SoC itself.
  257. You can get the binary blob from Quark Board Support Package from Intel website:
  258. * ./QuarkSocPkg/QuarkNorthCluster/Binary/QuarkMicrocode/RMU.bin
  259. Rename the file and put it to the board directory by:
  260. $ cp RMU.bin board/intel/galileo/rmu.bin
  261. Now you can build U-Boot and obtain u-boot.rom
  262. $ make galileo_defconfig
  263. $ make all
  264. ---
  265. QEMU x86 target instructions for bare mode:
  266. To build u-boot.rom for QEMU x86 targets, just simply run
  267. $ make qemu-x86_defconfig (for 32-bit)
  268. or
  269. $ make qemu-x86_64_defconfig (for 64-bit)
  270. $ make all
  271. Note this default configuration will build a U-Boot for the QEMU x86 i440FX
  272. board. To build a U-Boot against QEMU x86 Q35 board, you can change the build
  273. configuration during the 'make menuconfig' process like below:
  274. Device Tree Control --->
  275. ...
  276. (qemu-x86_q35) Default Device Tree for DT control
  277. Test with coreboot
  278. ------------------
  279. For testing U-Boot as the coreboot payload, there are things that need be paid
  280. attention to. coreboot supports loading an ELF executable and a 32-bit plain
  281. binary, as well as other supported payloads. With the default configuration,
  282. U-Boot is set up to use a separate Device Tree Blob (dtb). As of today, the
  283. generated u-boot-dtb.bin needs to be packaged by the cbfstool utility (a tool
  284. provided by coreboot) manually as coreboot's 'make menuconfig' does not provide
  285. this capability yet. The command is as follows:
  286. # in the coreboot root directory
  287. $ ./build/util/cbfstool/cbfstool build/coreboot.rom add-flat-binary \
  288. -f u-boot-dtb.bin -n fallback/payload -c lzma -l 0x1110000 -e 0x1110000
  289. Make sure 0x1110000 matches CONFIG_SYS_TEXT_BASE, which is the symbol address
  290. of _x86boot_start (in arch/x86/cpu/start.S).
  291. If you want to use ELF as the coreboot payload, change U-Boot configuration to
  292. use CONFIG_OF_EMBED instead of CONFIG_OF_SEPARATE.
  293. To enable video you must enable these options in coreboot:
  294. - Set framebuffer graphics resolution (1280x1024 32k-color (1:5:5))
  295. - Keep VESA framebuffer
  296. At present it seems that for Minnowboard Max, coreboot does not pass through
  297. the video information correctly (it always says the resolution is 0x0). This
  298. works correctly for link though.
  299. Test with QEMU for bare mode
  300. ----------------------------
  301. QEMU is a fancy emulator that can enable us to test U-Boot without access to
  302. a real x86 board. Please make sure your QEMU version is 2.3.0 or above test
  303. U-Boot. To launch QEMU with u-boot.rom, call QEMU as follows:
  304. $ qemu-system-i386 -nographic -bios path/to/u-boot.rom
  305. This will instantiate an emulated x86 board with i440FX and PIIX chipset. QEMU
  306. also supports emulating an x86 board with Q35 and ICH9 based chipset, which is
  307. also supported by U-Boot. To instantiate such a machine, call QEMU with:
  308. $ qemu-system-i386 -nographic -bios path/to/u-boot.rom -M q35
  309. Note by default QEMU instantiated boards only have 128 MiB system memory. But
  310. it is enough to have U-Boot boot and function correctly. You can increase the
  311. system memory by pass '-m' parameter to QEMU if you want more memory:
  312. $ qemu-system-i386 -nographic -bios path/to/u-boot.rom -m 1024
  313. This creates a board with 1 GiB system memory. Currently U-Boot for QEMU only
  314. supports 3 GiB maximum system memory and reserves the last 1 GiB address space
  315. for PCI device memory-mapped I/O and other stuff, so the maximum value of '-m'
  316. would be 3072.
  317. QEMU emulates a graphic card which U-Boot supports. Removing '-nographic' will
  318. show QEMU's VGA console window. Note this will disable QEMU's serial output.
  319. If you want to check both consoles, use '-serial stdio'.
  320. Multicore is also supported by QEMU via '-smp n' where n is the number of cores
  321. to instantiate. Note, the maximum supported CPU number in QEMU is 255.
  322. The fw_cfg interface in QEMU also provides information about kernel data,
  323. initrd, command-line arguments and more. U-Boot supports directly accessing
  324. these informtion from fw_cfg interface, which saves the time of loading them
  325. from hard disk or network again, through emulated devices. To use it , simply
  326. providing them in QEMU command line:
  327. $ qemu-system-i386 -nographic -bios path/to/u-boot.rom -m 1024 -kernel /path/to/bzImage
  328. -append 'root=/dev/ram console=ttyS0' -initrd /path/to/initrd -smp 8
  329. Note: -initrd and -smp are both optional
  330. Then start QEMU, in U-Boot command line use the following U-Boot command to
  331. setup kernel:
  332. => qfw
  333. qfw - QEMU firmware interface
  334. Usage:
  335. qfw <command>
  336. - list : print firmware(s) currently loaded
  337. - cpus : print online cpu number
  338. - load <kernel addr> <initrd addr> : load kernel and initrd (if any) and setup for zboot
  339. => qfw load
  340. loading kernel to address 01000000 size 5d9d30 initrd 04000000 size 1b1ab50
  341. Here the kernel (bzImage) is loaded to 01000000 and initrd is to 04000000. Then,
  342. 'zboot' can be used to boot the kernel:
  343. => zboot 01000000 - 04000000 1b1ab50
  344. To run 64-bit U-Boot, qemu-system-x86_64 should be used instead, e.g.:
  345. $ qemu-system-x86_64 -nographic -bios path/to/u-boot.rom
  346. A specific CPU can be specified via the '-cpu' parameter but please make
  347. sure the specified CPU supports 64-bit like '-cpu core2duo'. Conversely
  348. '-cpu pentium' won't work for obvious reasons that the processor only
  349. supports 32-bit.
  350. Note 64-bit support is very preliminary at this point. Lots of features
  351. are missing in the 64-bit world. One notable feature is the VGA console
  352. support which is currently missing, so that you must specify '-nographic'
  353. to get 64-bit U-Boot up and running.
  354. Updating U-Boot on Edison
  355. -------------------------
  356. By default Intel Edison boards are shipped with preinstalled heavily
  357. patched U-Boot v2014.04. Though it supports DFU which we may be able to
  358. use.
  359. 1. Prepare u-boot.bin as described in chapter above. You still need one
  360. more step (if and only if you have original U-Boot), i.e. run the
  361. following command:
  362. $ truncate -s %4096 u-boot.bin
  363. 2. Run your board and interrupt booting to U-Boot console. In the console
  364. call:
  365. => run do_force_flash_os
  366. 3. Wait for few seconds, it will prepare environment variable and runs
  367. DFU. Run DFU command from the host system:
  368. $ dfu-util -v -d 8087:0a99 --alt u-boot0 -D u-boot.bin
  369. 4. Return to U-Boot console and following hint. i.e. push Ctrl+C, and
  370. reset the board:
  371. => reset
  372. CPU Microcode
  373. -------------
  374. Modern CPUs usually require a special bit stream called microcode [8] to be
  375. loaded on the processor after power up in order to function properly. U-Boot
  376. has already integrated these as hex dumps in the source tree.
  377. SMP Support
  378. -----------
  379. On a multicore system, U-Boot is executed on the bootstrap processor (BSP).
  380. Additional application processors (AP) can be brought up by U-Boot. In order to
  381. have an SMP kernel to discover all of the available processors, U-Boot needs to
  382. prepare configuration tables which contain the multi-CPUs information before
  383. loading the OS kernel. Currently U-Boot supports generating two types of tables
  384. for SMP, called Simple Firmware Interface (SFI) [9] and Multi-Processor (MP)
  385. [10] tables. The writing of these two tables are controlled by two Kconfig
  386. options GENERATE_SFI_TABLE and GENERATE_MP_TABLE.
  387. Driver Model
  388. ------------
  389. x86 has been converted to use driver model for serial, GPIO, SPI, SPI flash,
  390. keyboard, real-time clock, USB. Video is in progress.
  391. Device Tree
  392. -----------
  393. x86 uses device tree to configure the board thus requires CONFIG_OF_CONTROL to
  394. be turned on. Not every device on the board is configured via device tree, but
  395. more and more devices will be added as time goes by. Check out the directory
  396. arch/x86/dts/ for these device tree source files.
  397. Useful Commands
  398. ---------------
  399. In keeping with the U-Boot philosophy of providing functions to check and
  400. adjust internal settings, there are several x86-specific commands that may be
  401. useful:
  402. fsp - Display information about Intel Firmware Support Package (FSP).
  403. This is only available on platforms which use FSP, mostly Atom.
  404. iod - Display I/O memory
  405. iow - Write I/O memory
  406. mtrr - List and set the Memory Type Range Registers (MTRR). These are used to
  407. tell the CPU whether memory is cacheable and if so the cache write
  408. mode to use. U-Boot sets up some reasonable values but you can
  409. adjust then with this command.
  410. Booting Ubuntu
  411. --------------
  412. As an example of how to set up your boot flow with U-Boot, here are
  413. instructions for starting Ubuntu from U-Boot. These instructions have been
  414. tested on Minnowboard MAX with a SATA drive but are equally applicable on
  415. other platforms and other media. There are really only four steps and it's a
  416. very simple script, but a more detailed explanation is provided here for
  417. completeness.
  418. Note: It is possible to set up U-Boot to boot automatically using syslinux.
  419. It could also use the grub.cfg file (/efi/ubuntu/grub.cfg) to obtain the
  420. GUID. If you figure these out, please post patches to this README.
  421. Firstly, you will need Ubuntu installed on an available disk. It should be
  422. possible to make U-Boot start a USB start-up disk but for now let's assume
  423. that you used another boot loader to install Ubuntu.
  424. Use the U-Boot command line to find the UUID of the partition you want to
  425. boot. For example our disk is SCSI device 0:
  426. => part list scsi 0
  427. Partition Map for SCSI device 0 -- Partition Type: EFI
  428. Part Start LBA End LBA Name
  429. Attributes
  430. Type GUID
  431. Partition GUID
  432. 1 0x00000800 0x001007ff ""
  433. attrs: 0x0000000000000000
  434. type: c12a7328-f81f-11d2-ba4b-00a0c93ec93b
  435. guid: 9d02e8e4-4d59-408f-a9b0-fd497bc9291c
  436. 2 0x00100800 0x037d8fff ""
  437. attrs: 0x0000000000000000
  438. type: 0fc63daf-8483-4772-8e79-3d69d8477de4
  439. guid: 965c59ee-1822-4326-90d2-b02446050059
  440. 3 0x037d9000 0x03ba27ff ""
  441. attrs: 0x0000000000000000
  442. type: 0657fd6d-a4ab-43c4-84e5-0933c84b4f4f
  443. guid: 2c4282bd-1e82-4bcf-a5ff-51dedbf39f17
  444. =>
  445. This shows that your SCSI disk has three partitions. The really long hex
  446. strings are called Globally Unique Identifiers (GUIDs). You can look up the
  447. 'type' ones here [11]. On this disk the first partition is for EFI and is in
  448. VFAT format (DOS/Windows):
  449. => fatls scsi 0:1
  450. efi/
  451. 0 file(s), 1 dir(s)
  452. Partition 2 is 'Linux filesystem data' so that will be our root disk. It is
  453. in ext2 format:
  454. => ext2ls scsi 0:2
  455. <DIR> 4096 .
  456. <DIR> 4096 ..
  457. <DIR> 16384 lost+found
  458. <DIR> 4096 boot
  459. <DIR> 12288 etc
  460. <DIR> 4096 media
  461. <DIR> 4096 bin
  462. <DIR> 4096 dev
  463. <DIR> 4096 home
  464. <DIR> 4096 lib
  465. <DIR> 4096 lib64
  466. <DIR> 4096 mnt
  467. <DIR> 4096 opt
  468. <DIR> 4096 proc
  469. <DIR> 4096 root
  470. <DIR> 4096 run
  471. <DIR> 12288 sbin
  472. <DIR> 4096 srv
  473. <DIR> 4096 sys
  474. <DIR> 4096 tmp
  475. <DIR> 4096 usr
  476. <DIR> 4096 var
  477. <SYM> 33 initrd.img
  478. <SYM> 30 vmlinuz
  479. <DIR> 4096 cdrom
  480. <SYM> 33 initrd.img.old
  481. =>
  482. and if you look in the /boot directory you will see the kernel:
  483. => ext2ls scsi 0:2 /boot
  484. <DIR> 4096 .
  485. <DIR> 4096 ..
  486. <DIR> 4096 efi
  487. <DIR> 4096 grub
  488. 3381262 System.map-3.13.0-32-generic
  489. 1162712 abi-3.13.0-32-generic
  490. 165611 config-3.13.0-32-generic
  491. 176500 memtest86+.bin
  492. 178176 memtest86+.elf
  493. 178680 memtest86+_multiboot.bin
  494. 5798112 vmlinuz-3.13.0-32-generic
  495. 165762 config-3.13.0-58-generic
  496. 1165129 abi-3.13.0-58-generic
  497. 5823136 vmlinuz-3.13.0-58-generic
  498. 19215259 initrd.img-3.13.0-58-generic
  499. 3391763 System.map-3.13.0-58-generic
  500. 5825048 vmlinuz-3.13.0-58-generic.efi.signed
  501. 28304443 initrd.img-3.13.0-32-generic
  502. =>
  503. The 'vmlinuz' files contain a packaged Linux kernel. The format is a kind of
  504. self-extracting compressed file mixed with some 'setup' configuration data.
  505. Despite its size (uncompressed it is >10MB) this only includes a basic set of
  506. device drivers, enough to boot on most hardware types.
  507. The 'initrd' files contain a RAM disk. This is something that can be loaded
  508. into RAM and will appear to Linux like a disk. Ubuntu uses this to hold lots
  509. of drivers for whatever hardware you might have. It is loaded before the
  510. real root disk is accessed.
  511. The numbers after the end of each file are the version. Here it is Linux
  512. version 3.13. You can find the source code for this in the Linux tree with
  513. the tag v3.13. The '.0' allows for additional Linux releases to fix problems,
  514. but normally this is not needed. The '-58' is used by Ubuntu. Each time they
  515. release a new kernel they increment this number. New Ubuntu versions might
  516. include kernel patches to fix reported bugs. Stable kernels can exist for
  517. some years so this number can get quite high.
  518. The '.efi.signed' kernel is signed for EFI's secure boot. U-Boot has its own
  519. secure boot mechanism - see [12] [13] and cannot read .efi files at present.
  520. To boot Ubuntu from U-Boot the steps are as follows:
  521. 1. Set up the boot arguments. Use the GUID for the partition you want to
  522. boot:
  523. => setenv bootargs root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro
  524. Here root= tells Linux the location of its root disk. The disk is specified
  525. by its GUID, using '/dev/disk/by-partuuid/', a Linux path to a 'directory'
  526. containing all the GUIDs Linux has found. When it starts up, there will be a
  527. file in that directory with this name in it. It is also possible to use a
  528. device name here, see later.
  529. 2. Load the kernel. Since it is an ext2/4 filesystem we can do:
  530. => ext2load scsi 0:2 03000000 /boot/vmlinuz-3.13.0-58-generic
  531. The address 30000000 is arbitrary, but there seem to be problems with using
  532. small addresses (sometimes Linux cannot find the ramdisk). This is 48MB into
  533. the start of RAM (which is at 0 on x86).
  534. 3. Load the ramdisk (to 64MB):
  535. => ext2load scsi 0:2 04000000 /boot/initrd.img-3.13.0-58-generic
  536. 4. Start up the kernel. We need to know the size of the ramdisk, but can use
  537. a variable for that. U-Boot sets 'filesize' to the size of the last file it
  538. loaded.
  539. => zboot 03000000 0 04000000 ${filesize}
  540. Type 'help zboot' if you want to see what the arguments are. U-Boot on x86 is
  541. quite verbose when it boots a kernel. You should see these messages from
  542. U-Boot:
  543. Valid Boot Flag
  544. Setup Size = 0x00004400
  545. Magic signature found
  546. Using boot protocol version 2.0c
  547. Linux kernel version 3.13.0-58-generic (buildd@allspice) #97-Ubuntu SMP Wed Jul 8 02:56:15 UTC 2015
  548. Building boot_params at 0x00090000
  549. Loading bzImage at address 100000 (5805728 bytes)
  550. Magic signature found
  551. Initial RAM disk at linear address 0x04000000, size 19215259 bytes
  552. Kernel command line: "root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro"
  553. Starting kernel ...
  554. U-Boot prints out some bootstage timing. This is more useful if you put the
  555. above commands into a script since then it will be faster.
  556. Timer summary in microseconds:
  557. Mark Elapsed Stage
  558. 0 0 reset
  559. 241,535 241,535 board_init_r
  560. 2,421,611 2,180,076 id=64
  561. 2,421,790 179 id=65
  562. 2,428,215 6,425 main_loop
  563. 48,860,584 46,432,369 start_kernel
  564. Accumulated time:
  565. 240,329 ahci
  566. 1,422,704 vesa display
  567. Now the kernel actually starts: (if you want to examine kernel boot up message
  568. on the serial console, append "console=ttyS0,115200" to the kernel command line)
  569. [ 0.000000] Initializing cgroup subsys cpuset
  570. [ 0.000000] Initializing cgroup subsys cpu
  571. [ 0.000000] Initializing cgroup subsys cpuacct
  572. [ 0.000000] Linux version 3.13.0-58-generic (buildd@allspice) (gcc version 4.8.2 (Ubuntu 4.8.2-19ubuntu1) ) #97-Ubuntu SMP Wed Jul 8 02:56:15 UTC 2015 (Ubuntu 3.13.0-58.97-generic 3.13.11-ckt22)
  573. [ 0.000000] Command line: root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro console=ttyS0,115200
  574. It continues for a long time. Along the way you will see it pick up your
  575. ramdisk:
  576. [ 0.000000] RAMDISK: [mem 0x04000000-0x05253fff]
  577. ...
  578. [ 0.788540] Trying to unpack rootfs image as initramfs...
  579. [ 1.540111] Freeing initrd memory: 18768K (ffff880004000000 - ffff880005254000)
  580. ...
  581. Later it actually starts using it:
  582. Begin: Running /scripts/local-premount ... done.
  583. You should also see your boot disk turn up:
  584. [ 4.357243] scsi 1:0:0:0: Direct-Access ATA ADATA SP310 5.2 PQ: 0 ANSI: 5
  585. [ 4.366860] sd 1:0:0:0: [sda] 62533296 512-byte logical blocks: (32.0 GB/29.8 GiB)
  586. [ 4.375677] sd 1:0:0:0: Attached scsi generic sg0 type 0
  587. [ 4.381859] sd 1:0:0:0: [sda] Write Protect is off
  588. [ 4.387452] sd 1:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
  589. [ 4.399535] sda: sda1 sda2 sda3
  590. Linux has found the three partitions (sda1-3). Mercifully it doesn't print out
  591. the GUIDs. In step 1 above we could have used:
  592. setenv bootargs root=/dev/sda2 ro
  593. instead of the GUID. However if you add another drive to your board the
  594. numbering may change whereas the GUIDs will not. So if your boot partition
  595. becomes sdb2, it will still boot. For embedded systems where you just want to
  596. boot the first disk, you have that option.
  597. The last thing you will see on the console is mention of plymouth (which
  598. displays the Ubuntu start-up screen) and a lot of 'Starting' messages:
  599. * Starting Mount filesystems on boot [ OK ]
  600. After a pause you should see a login screen on your display and you are done.
  601. If you want to put this in a script you can use something like this:
  602. setenv bootargs root=UUID=b2aaf743-0418-4d90-94cc-3e6108d7d968 ro
  603. setenv boot zboot 03000000 0 04000000 \${filesize}
  604. setenv bootcmd "ext2load scsi 0:2 03000000 /boot/vmlinuz-3.13.0-58-generic; ext2load scsi 0:2 04000000 /boot/initrd.img-3.13.0-58-generic; run boot"
  605. saveenv
  606. The \ is to tell the shell not to evaluate ${filesize} as part of the setenv
  607. command.
  608. You can also bake this behaviour into your build by hard-coding the
  609. environment variables if you add this to minnowmax.h:
  610. #undef CONFIG_BOOTCOMMAND
  611. #define CONFIG_BOOTCOMMAND \
  612. "ext2load scsi 0:2 03000000 /boot/vmlinuz-3.13.0-58-generic; " \
  613. "ext2load scsi 0:2 04000000 /boot/initrd.img-3.13.0-58-generic; " \
  614. "run boot"
  615. #undef CONFIG_EXTRA_ENV_SETTINGS
  616. #define CONFIG_EXTRA_ENV_SETTINGS "boot=zboot 03000000 0 04000000 ${filesize}"
  617. and change CONFIG_BOOTARGS value in configs/minnowmax_defconfig to:
  618. CONFIG_BOOTARGS="root=/dev/sda2 ro"
  619. Test with SeaBIOS
  620. -----------------
  621. SeaBIOS [14] is an open source implementation of a 16-bit x86 BIOS. It can run
  622. in an emulator or natively on x86 hardware with the use of U-Boot. With its
  623. help, we can boot some OSes that require 16-bit BIOS services like Windows/DOS.
  624. As U-Boot, we have to manually create a table where SeaBIOS gets various system
  625. information (eg: E820) from. The table unfortunately has to follow the coreboot
  626. table format as SeaBIOS currently supports booting as a coreboot payload.
  627. To support loading SeaBIOS, U-Boot should be built with CONFIG_SEABIOS on.
  628. Booting SeaBIOS is done via U-Boot's bootelf command, like below:
  629. => tftp bios.bin.elf;bootelf
  630. Using e1000#0 device
  631. TFTP from server 10.10.0.100; our IP address is 10.10.0.108
  632. ...
  633. Bytes transferred = 122124 (1dd0c hex)
  634. ## Starting application at 0x000ff06e ...
  635. SeaBIOS (version rel-1.9.0)
  636. ...
  637. bios.bin.elf is the SeaBIOS image built from SeaBIOS source tree.
  638. Make sure it is built as follows:
  639. $ make menuconfig
  640. Inside the "General Features" menu, select "Build for coreboot" as the
  641. "Build Target". Inside the "Debugging" menu, turn on "Serial port debugging"
  642. so that we can see something as soon as SeaBIOS boots. Leave other options
  643. as in their default state. Then,
  644. $ make
  645. ...
  646. Total size: 121888 Fixed: 66496 Free: 9184 (used 93.0% of 128KiB rom)
  647. Creating out/bios.bin.elf
  648. Currently this is tested on QEMU x86 target with U-Boot chain-loading SeaBIOS
  649. to install/boot a Windows XP OS (below for example command to install Windows).
  650. # Create a 10G disk.img as the virtual hard disk
  651. $ qemu-img create -f qcow2 disk.img 10G
  652. # Install a Windows XP OS from an ISO image 'winxp.iso'
  653. $ qemu-system-i386 -serial stdio -bios u-boot.rom -hda disk.img -cdrom winxp.iso -smp 2 -m 512
  654. # Boot a Windows XP OS installed on the virutal hard disk
  655. $ qemu-system-i386 -serial stdio -bios u-boot.rom -hda disk.img -smp 2 -m 512
  656. This is also tested on Intel Crown Bay board with a PCIe graphics card, booting
  657. SeaBIOS then chain-loading a GRUB on a USB drive, then Linux kernel finally.
  658. If you are using Intel Integrated Graphics Device (IGD) as the primary display
  659. device on your board, SeaBIOS needs to be patched manually to get its VGA ROM
  660. loaded and run by SeaBIOS. SeaBIOS locates VGA ROM via the PCI expansion ROM
  661. register, but IGD device does not have its VGA ROM mapped by this register.
  662. Its VGA ROM is packaged as part of u-boot.rom at a configurable flash address
  663. which is unknown to SeaBIOS. An example patch is needed for SeaBIOS below:
  664. diff --git a/src/optionroms.c b/src/optionroms.c
  665. index 65f7fe0..c7b6f5e 100644
  666. --- a/src/optionroms.c
  667. +++ b/src/optionroms.c
  668. @@ -324,6 +324,8 @@ init_pcirom(struct pci_device *pci, int isvga, u64 *sources)
  669. rom = deploy_romfile(file);
  670. else if (RunPCIroms > 1 || (RunPCIroms == 1 && isvga))
  671. rom = map_pcirom(pci);
  672. + if (pci->bdf == pci_to_bdf(0, 2, 0))
  673. + rom = (struct rom_header *)0xfff90000;
  674. if (! rom)
  675. // No ROM present.
  676. return;
  677. Note: the patch above expects IGD device is at PCI b.d.f 0.2.0 and its VGA ROM
  678. is at 0xfff90000 which corresponds to CONFIG_VGA_BIOS_ADDR on Minnowboard MAX.
  679. Change these two accordingly if this is not the case on your board.
  680. Development Flow
  681. ----------------
  682. These notes are for those who want to port U-Boot to a new x86 platform.
  683. Since x86 CPUs boot from SPI flash, a SPI flash emulator is a good investment.
  684. The Dediprog em100 can be used on Linux. The em100 tool is available here:
  685. http://review.coreboot.org/p/em100.git
  686. On Minnowboard Max the following command line can be used:
  687. sudo em100 -s -p LOW -d u-boot.rom -c W25Q64DW -r
  688. A suitable clip for connecting over the SPI flash chip is here:
  689. http://www.dediprog.com/pd/programmer-accessories/EM-TC-8
  690. This allows you to override the SPI flash contents for development purposes.
  691. Typically you can write to the em100 in around 1200ms, considerably faster
  692. than programming the real flash device each time. The only important
  693. limitation of the em100 is that it only supports SPI bus speeds up to 20MHz.
  694. This means that images must be set to boot with that speed. This is an
  695. Intel-specific feature - e.g. tools/ifttool has an option to set the SPI
  696. speed in the SPI descriptor region.
  697. If your chip/board uses an Intel Firmware Support Package (FSP) it is fairly
  698. easy to fit it in. You can follow the Minnowboard Max implementation, for
  699. example. Hopefully you will just need to create new files similar to those
  700. in arch/x86/cpu/baytrail which provide Bay Trail support.
  701. If you are not using an FSP you have more freedom and more responsibility.
  702. The ivybridge support works this way, although it still uses a ROM for
  703. graphics and still has binary blobs containing Intel code. You should aim to
  704. support all important peripherals on your platform including video and storage.
  705. Use the device tree for configuration where possible.
  706. For the microcode you can create a suitable device tree file using the
  707. microcode tool:
  708. ./tools/microcode-tool -d microcode.dat -m <model> create
  709. or if you only have header files and not the full Intel microcode.dat database:
  710. ./tools/microcode-tool -H BAY_TRAIL_FSP_KIT/Microcode/M0130673322.h \
  711. -H BAY_TRAIL_FSP_KIT/Microcode/M0130679901.h \
  712. -m all create
  713. These are written to arch/x86/dts/microcode/ by default.
  714. Note that it is possible to just add the micrcode for your CPU if you know its
  715. model. U-Boot prints this information when it starts
  716. CPU: x86_64, vendor Intel, device 30673h
  717. so here we can use the M0130673322 file.
  718. If you platform can display POST codes on two little 7-segment displays on
  719. the board, then you can use post_code() calls from C or assembler to monitor
  720. boot progress. This can be good for debugging.
  721. If not, you can try to get serial working as early as possible. The early
  722. debug serial port may be useful here. See setup_internal_uart() for an example.
  723. During the U-Boot porting, one of the important steps is to write correct PIRQ
  724. routing information in the board device tree. Without it, device drivers in the
  725. Linux kernel won't function correctly due to interrupt is not working. Please
  726. refer to U-Boot doc [15] for the device tree bindings of Intel interrupt router.
  727. Here we have more details on the intel,pirq-routing property below.
  728. intel,pirq-routing = <
  729. PCI_BDF(0, 2, 0) INTA PIRQA
  730. ...
  731. >;
  732. As you see each entry has 3 cells. For the first one, we need describe all pci
  733. devices mounted on the board. For SoC devices, normally there is a chapter on
  734. the chipset datasheet which lists all the available PCI devices. For example on
  735. Bay Trail, this is chapter 4.3 (PCI configuration space). For the second one, we
  736. can get the interrupt pin either from datasheet or hardware via U-Boot shell.
  737. The reliable source is the hardware as sometimes chipset datasheet is not 100%
  738. up-to-date. Type 'pci header' plus the device's pci bus/device/function number
  739. from U-Boot shell below.
  740. => pci header 0.1e.1
  741. vendor ID = 0x8086
  742. device ID = 0x0f08
  743. ...
  744. interrupt line = 0x09
  745. interrupt pin = 0x04
  746. ...
  747. It shows this PCI device is using INTD pin as it reports 4 in the interrupt pin
  748. register. Repeat this until you get interrupt pins for all the devices. The last
  749. cell is the PIRQ line which a particular interrupt pin is mapped to. On Intel
  750. chipset, the power-up default mapping is INTA/B/C/D maps to PIRQA/B/C/D. This
  751. can be changed by registers in LPC bridge. So far Intel FSP does not touch those
  752. registers so we can write down the PIRQ according to the default mapping rule.
  753. Once we get the PIRQ routing information in the device tree, the interrupt
  754. allocation and assignment will be done by U-Boot automatically. Now you can
  755. enable CONFIG_GENERATE_PIRQ_TABLE for testing Linux kernel using i8259 PIC and
  756. CONFIG_GENERATE_MP_TABLE for testing Linux kernel using local APIC and I/O APIC.
  757. This script might be useful. If you feed it the output of 'pci long' from
  758. U-Boot then it will generate a device tree fragment with the interrupt
  759. configuration for each device (note it needs gawk 4.0.0):
  760. $ cat console_output |awk '/PCI/ {device=$4} /interrupt line/ {line=$4} \
  761. /interrupt pin/ {pin = $4; if (pin != "0x00" && pin != "0xff") \
  762. {patsplit(device, bdf, "[0-9a-f]+"); \
  763. printf "PCI_BDF(%d, %d, %d) INT%c PIRQ%c\n", strtonum("0x" bdf[1]), \
  764. strtonum("0x" bdf[2]), bdf[3], strtonum(pin) + 64, 64 + strtonum(pin)}}'
  765. Example output:
  766. PCI_BDF(0, 2, 0) INTA PIRQA
  767. PCI_BDF(0, 3, 0) INTA PIRQA
  768. ...
  769. Porting Hints
  770. -------------
  771. Quark-specific considerations:
  772. To port U-Boot to other boards based on the Intel Quark SoC, a few things need
  773. to be taken care of. The first important part is the Memory Reference Code (MRC)
  774. parameters. Quark MRC supports memory-down configuration only. All these MRC
  775. parameters are supplied via the board device tree. To get started, first copy
  776. the MRC section of arch/x86/dts/galileo.dts to your board's device tree, then
  777. change these values by consulting board manuals or your hardware vendor.
  778. Available MRC parameter values are listed in include/dt-bindings/mrc/quark.h.
  779. The other tricky part is with PCIe. Quark SoC integrates two PCIe root ports,
  780. but by default they are held in reset after power on. In U-Boot, PCIe
  781. initialization is properly handled as per Quark's firmware writer guide.
  782. In your board support codes, you need provide two routines to aid PCIe
  783. initialization, which are board_assert_perst() and board_deassert_perst().
  784. The two routines need implement a board-specific mechanism to assert/deassert
  785. PCIe PERST# pin. Care must be taken that in those routines that any APIs that
  786. may trigger PCI enumeration process are strictly forbidden, as any access to
  787. PCIe root port's configuration registers will cause system hang while it is
  788. held in reset. For more details, check how they are implemented by the Intel
  789. Galileo board support codes in board/intel/galileo/galileo.c.
  790. coreboot:
  791. See scripts/coreboot.sed which can assist with porting coreboot code into
  792. U-Boot drivers. It will not resolve all build errors, but will perform common
  793. transformations. Remember to add attribution to coreboot for new files added
  794. to U-Boot. This should go at the top of each file and list the coreboot
  795. filename where the code originated.
  796. Debugging ACPI issues with Windows:
  797. Windows might cache system information and only detect ACPI changes if you
  798. modify the ACPI table versions. So tweak them liberally when debugging ACPI
  799. issues with Windows.
  800. ACPI Support Status
  801. -------------------
  802. Advanced Configuration and Power Interface (ACPI) [16] aims to establish
  803. industry-standard interfaces enabling OS-directed configuration, power
  804. management, and thermal management of mobile, desktop, and server platforms.
  805. Linux can boot without ACPI with "acpi=off" command line parameter, but
  806. with ACPI the kernel gains the capabilities to handle power management.
  807. For Windows, ACPI is a must-have firmware feature since Windows Vista.
  808. CONFIG_GENERATE_ACPI_TABLE is the config option to turn on ACPI support in
  809. U-Boot. This requires Intel ACPI compiler to be installed on your host to
  810. compile ACPI DSDT table written in ASL format to AML format. You can get
  811. the compiler via "apt-get install iasl" if you are on Ubuntu or download
  812. the source from [17] to compile one by yourself.
  813. Current ACPI support in U-Boot is basically complete. More optional features
  814. can be added in the future. The status as of today is:
  815. * Support generating RSDT, XSDT, FACS, FADT, MADT, MCFG tables.
  816. * Support one static DSDT table only, compiled by Intel ACPI compiler.
  817. * Support S0/S3/S4/S5, reboot and shutdown from OS.
  818. * Support booting a pre-installed Ubuntu distribution via 'zboot' command.
  819. * Support installing and booting Ubuntu 14.04 (or above) from U-Boot with
  820. the help of SeaBIOS using legacy interface (non-UEFI mode).
  821. * Support installing and booting Windows 8.1/10 from U-Boot with the help
  822. of SeaBIOS using legacy interface (non-UEFI mode).
  823. * Support ACPI interrupts with SCI only.
  824. Features that are optional:
  825. * Dynamic AML bytecodes insertion at run-time. We may need this to support
  826. SSDT table generation and DSDT fix up.
  827. * SMI support. Since U-Boot is a modern bootloader, we don't want to bring
  828. those legacy stuff into U-Boot. ACPI spec allows a system that does not
  829. support SMI (a legacy-free system).
  830. ACPI was initially enabled on BayTrail based boards. Testing was done by booting
  831. a pre-installed Ubuntu 14.04 from a SATA drive. Installing Ubuntu 14.04 and
  832. Windows 8.1/10 to a SATA drive and booting from there is also tested. Most
  833. devices seem to work correctly and the board can respond a reboot/shutdown
  834. command from the OS.
  835. For other platform boards, ACPI support status can be checked by examining their
  836. board defconfig files to see if CONFIG_GENERATE_ACPI_TABLE is set to y.
  837. The S3 sleeping state is a low wake latency sleeping state defined by ACPI
  838. spec where all system context is lost except system memory. To test S3 resume
  839. with a Linux kernel, simply run "echo mem > /sys/power/state" and kernel will
  840. put the board to S3 state where the power is off. So when the power button is
  841. pressed again, U-Boot runs as it does in cold boot and detects the sleeping
  842. state via ACPI register to see if it is S3, if yes it means we are waking up.
  843. U-Boot is responsible for restoring the machine state as it is before sleep.
  844. When everything is done, U-Boot finds out the wakeup vector provided by OSes
  845. and jump there. To determine whether ACPI S3 resume is supported, check to
  846. see if CONFIG_HAVE_ACPI_RESUME is set for that specific board.
  847. Note for testing S3 resume with Windows, correct graphics driver must be
  848. installed for your platform, otherwise you won't find "Sleep" option in
  849. the "Power" submenu from the Windows start menu.
  850. EFI Support
  851. -----------
  852. U-Boot supports booting as a 32-bit or 64-bit EFI payload, e.g. with UEFI.
  853. This is enabled with CONFIG_EFI_STUB to boot from both 32-bit and 64-bit
  854. UEFI BIOS. U-Boot can also run as an EFI application, with CONFIG_EFI_APP.
  855. The CONFIG_EFI_LOADER option, where U-Boot provides an EFI environment to
  856. the kernel (i.e. replaces UEFI completely but provides the same EFI run-time
  857. services) is supported too. For example, we can even use 'bootefi' command
  858. to load a 'u-boot-payload.efi', see below test logs on QEMU.
  859. => load ide 0 3000000 u-boot-payload.efi
  860. 489787 bytes read in 138 ms (3.4 MiB/s)
  861. => bootefi 3000000
  862. Scanning disk ide.blk#0...
  863. Found 2 disks
  864. WARNING: booting without device tree
  865. ## Starting EFI application at 03000000 ...
  866. U-Boot EFI Payload
  867. U-Boot 2018.07-rc2 (Jun 23 2018 - 17:12:58 +0800)
  868. CPU: x86_64, vendor AMD, device 663h
  869. DRAM: 2 GiB
  870. MMC:
  871. Video: 1024x768x32
  872. Model: EFI x86 Payload
  873. Net: e1000: 52:54:00:12:34:56
  874. Warning: e1000#0 using MAC address from ROM
  875. eth0: e1000#0
  876. No controllers found
  877. Hit any key to stop autoboot: 0
  878. See README.u-boot_on_efi and README.uefi for details of EFI support in U-Boot.
  879. TODO List
  880. ---------
  881. - Audio
  882. - Chrome OS verified boot
  883. References
  884. ----------
  885. [1] http://www.coreboot.org
  886. [2] http://www.qemu.org
  887. [3] http://www.coreboot.org/~stepan/pci8086,0166.rom
  888. [4] http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html
  889. [5] http://www.intel.com/fsp
  890. [6] http://www.intel.com/content/www/us/en/secure/intelligent-systems/privileged/e6xx-35-b1-cmc22211.html
  891. [7] http://www.ami.com/products/bios-uefi-tools-and-utilities/bios-uefi-utilities/
  892. [8] http://en.wikipedia.org/wiki/Microcode
  893. [9] http://simplefirmware.org
  894. [10] http://www.intel.com/design/archives/processors/pro/docs/242016.htm
  895. [11] https://en.wikipedia.org/wiki/GUID_Partition_Table
  896. [12] http://events.linuxfoundation.org/sites/events/files/slides/chromeos_and_diy_vboot_0.pdf
  897. [13] http://events.linuxfoundation.org/sites/events/files/slides/elce-2014.pdf
  898. [14] http://www.seabios.org/SeaBIOS
  899. [15] doc/device-tree-bindings/misc/intel,irq-router.txt
  900. [16] http://www.acpi.info
  901. [17] https://www.acpica.org/downloads