README.b4860qds 14 KB

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  1. Overview
  2. --------
  3. The B4860QDS is a Freescale reference board that hosts the B4860 SoC (and variants).
  4. B4860 Overview
  5. -------------
  6. The B4860 QorIQ Qonverge device is a Freescale high-end, multicore SoC based on
  7. StarCore and Power Architecture® cores. It targets the broadband wireless
  8. infrastructure and builds upon the proven success of the existing multicore
  9. DSPs and Power CPUs. It is designed to bolster the rapidly changing and
  10. expanding wireless markets, such as 3GLTE (FDD and TDD), LTE-Advanced, and UMTS.
  11. The B4860 is a highly-integrated StarCore and Power Architecture processor that
  12. contains:
  13. . Six fully-programmable StarCore SC3900 FVP subsystems, divided into three
  14. clusters-each core runs up to 1.2 GHz, with an architecture highly optimized for
  15. wireless base station applications
  16. . Four dual-thread e6500 Power Architecture processors organized in one cluster-each
  17. core runs up to 1.8 GHz
  18. . Two DDR3/3L controllers for high-speed, industry-standard memory interface each
  19. runs at up to 1866.67 MHz
  20. . MAPLE-B3 hardware acceleration-for forward error correction schemes including
  21. Turbo or Viterbi decoding, Turbo encoding and rate matching, MIMO MMSE
  22. equalization scheme, matrix operations, CRC insertion and check, DFT/iDFT and
  23. FFT/iFFT calculations, PUSCH/PDSCH acceleration, and UMTS chip rate
  24. acceleration
  25. . CoreNet fabric that fully supports coherency using MESI protocol between the
  26. e6500 cores, SC3900 FVP cores, memories and external interfaces.
  27. CoreNet fabric interconnect runs at 667 MHz and supports coherent and
  28. non-coherent out of order transactions with prioritization and bandwidth
  29. allocation amongst CoreNet endpoints.
  30. . Data Path Acceleration Architecture, which includes the following:
  31. . Frame Manager (FMan), which supports in-line packet parsing and general
  32. classification to enable policing and QoS-based packet distribution
  33. . Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading
  34. of queue management, task management, load distribution, flow ordering, buffer
  35. management, and allocation tasks from the cores
  36. . Security engine (SEC 5.3)-crypto-acceleration for protocols such as IPsec,
  37. SSL, and 802.16
  38. . RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and
  39. outbound). Supports types 5, 6 (outbound only)
  40. . Large internal cache memory with snooping and stashing capabilities for
  41. bandwidth saving and high utilization of processor elements. The 9856-Kbyte
  42. internal memory space includes the following:
  43. . 32 Kbyte L1 ICache per e6500/SC3900 core
  44. . 32 Kbyte L1 DCache per e6500/SC3900 core
  45. . 2048 Kbyte unified L2 cache for each SC3900 FVP cluster
  46. . 2048 Kbyte unified L2 cache for the e6500 cluster
  47. . Two 512 Kbyte shared L3 CoreNet platform caches (CPC)
  48. . Sixteen 10-GHz SerDes lanes serving:
  49. . Two Serial RapidIO interfaces.
  50. - Each supports up to 4 lanes and a total of up to 8 lanes
  51. . Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue-less
  52. antenna connection
  53. . Two 10-Gbit Ethernet controllers (10GEC)
  54. . Six 1G/2.5-Gbit Ethernet controllers for network communications
  55. . PCI Express controller
  56. . Debug (Aurora)
  57. . Two OCeaN DMAs
  58. . Various system peripherals
  59. . 182 32-bit timers
  60. B4860QDS Overview
  61. ------------------
  62. - DDRC1: Ten separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s, ECC, 4 GB
  63. of memory in two ranks of 2 GB.
  64. - DDRC2: Five separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s, ECC, 2 GB
  65. of memory. Single rank.
  66. - SerDes 1 multiplexing: Two Vitesse (transmit and receive path) cross-point 16x16 switch
  67. VSC3316
  68. - SerDes 2 multiplexing: Two Vitesse (transmit and receive path) cross-point 8x8 switch VSC3308
  69. - USB 2.0 ULPI PHY USB3315 by SMSC supports USB port in host mode.
  70. B4860 UART port is available over USB-to-UART translator USB2SER or over RS232 flat cable.
  71. - A Vitesse dual SGMII phy VSC8662 links the B4860 SGMII lines to 2xRJ-45 copper connectors
  72. for Stand-alone mode and to the 1000Base-X over AMC MicroTCA connector ports 0 and 2 for
  73. AMC mode.
  74. - The B4860 configuration may be loaded from nine bits coded reset configuration reset source. The
  75. RCW source is set by appropriate DIP-switches:
  76. - 16-bit NOR Flash / PROMJet
  77. - QIXIS 8-bit NOR Flash Emulator
  78. - 8-bit NAND Flash
  79. - 24-bit SPI Flash
  80. - Long address I2C EEPROM
  81. - Available debug interfaces are:
  82. - On-board eCWTAP controller with ETH and USB I/F
  83. - JTAG/COP 16-pin header for any external TAP controller
  84. - External JTAG source over AMC to support B2B configuration
  85. - 70-pin Aurora debug connector
  86. - QIXIS (FPGA) logic:
  87. - 2 KB internal memory space including
  88. - IDT840NT4 clock synthesizer provides B4860 essential clocks : SYSCLK, DDRCLK1,2 and
  89. RTCCLK.
  90. - Two 8T49N222A SerDes ref clock devices support two SerDes port clock frequency - total four
  91. refclk, including CPRI clock scheme.
  92. B4420 Personality
  93. --------------------
  94. B4420 Personality
  95. --------------------
  96. B4420 is a reduced personality of B4860 with less core/clusters(both SC3900 and e6500), less DDR
  97. controllers, less serdes lanes, less SGMII interfaces and reduced target frequencies.
  98. Key differences between B4860 and B4420
  99. ----------------------------------------
  100. B4420 has:
  101. 1. Less e6500 cores: 1 cluster with 2 e6500 cores
  102. 2. Less SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster.
  103. 3. Single DDRC
  104. 4. 2X 4 lane serdes
  105. 5. 3 SGMII interfaces
  106. 6. no sRIO
  107. 7. no 10G
  108. B4860QDS Default Settings
  109. -------------------------
  110. Switch Settings
  111. ----------------
  112. SW1 OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0]
  113. SW2 ON ON ON ON ON ON OFF OFF
  114. SW3 OFF OFF OFF ON OFF OFF ON OFF
  115. SW5 OFF OFF OFF OFF OFF OFF ON ON
  116. Note: PCIe slots modes: All the PCIe devices work as Root Complex.
  117. Note: Boot location: NOR flash.
  118. SysClk/Core(e6500)/CCB/DDR/FMan/DDRCLK/StarCore/CPRI-Maple/eTVPE-Maple/ULB-Maple
  119. 66MHz/1.6GHz/667MHz/1.6GHz data rate/667MHz/133MHz/1200MHz/500MHz/800MHz/667MHz
  120. a) NAND boot
  121. SW1 [1.1] = 0
  122. SW2 [1.1] = 1
  123. SW3 [1:4] = 0001
  124. b) NOR boot
  125. SW1 [1.1] = 1
  126. SW2 [1.1] = 0
  127. SW3 [1:4] = 1000.
  128. B4420QDS Default Settings
  129. -------------------------
  130. Switch Settings
  131. ----------------
  132. SW1 OFF[0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0]
  133. SW2 ON OFF ON OFF ON ON OFF OFF
  134. SW3 OFF OFF OFF ON OFF OFF ON OFF
  135. SW5 OFF OFF OFF OFF OFF OFF ON ON
  136. Note: PCIe slots modes: All the PCIe devices work as Root Complex.
  137. Note: Boot location: NOR flash.
  138. SysClk/Core(e6500)/CCB/DDR/FMan/DDRCLK/StarCore/CPRI-Maple/eTVPE-Maple/ULB-Maple
  139. 66MHz/1.6GHz/667MHz/1.6GHz data rate/667MHz/133MHz/1200MHz/500MHz/800MHz/667MHz
  140. a) NAND boot
  141. SW1 [1.1] = 0
  142. SW2 [1.1] = 1
  143. SW3 [1:4] = 0001
  144. b) NOR boot
  145. SW1 [1.1] = 1
  146. SW2 [1.1] = 0
  147. SW3 [1:4] = 1000.
  148. Memory map on B4860QDS
  149. ----------------------
  150. The addresses in brackets are physical addresses.
  151. Start Address End Address Description Size
  152. 0xF_FFDF_1000 0xF_FFFF_FFFF Free 2 MB
  153. 0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4 KB
  154. 0xF_FF81_0000 0xF_FFDE_FFFF Free 5 MB
  155. 0xF_FF80_0000 0xF_FF80_FFFF IFC NAND Flash 64 KB
  156. 0xF_FF00_0000 0xF_FF7F_FFFF Free 8 MB
  157. 0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16 MB
  158. 0xF_F801_0000 0xF_FDFF_FFFF Free 95 MB
  159. 0xF_F800_0000 0xF_F800_FFFF PCIe I/O Space 64 KB
  160. 0xF_F600_0000 0xF_F7FF_FFFF QMAN s/w portal 32 MB
  161. 0xF_F400_0000 0xF_F5FF_FFFF BMAN s/w portal 32 MB
  162. 0xF_F000_0000 0xF_F3FF_FFFF Free 64 MB
  163. 0xF_E800_0000 0xF_EFFF_FFFF IFC NOR Flash 128 MB
  164. 0xF_E000_0000 0xF_E7FF_FFFF Promjet 128 MB
  165. 0xF_A0C0_0000 0xF_DFFF_FFFF Free 1012 MB
  166. 0xF_A000_0000 0xF_A0BF_FFFF MAPLE0/1/2 12 MB
  167. 0xF_0040_0000 0xF_9FFF_FFFF Free 12 GB
  168. 0xF_0000_0000 0xF_01FF_FFFF DCSR 32 MB
  169. 0xC_4000_0000 0xE_FFFF_FFFF Free 11 GB
  170. 0xC_3000_0000 0xC_3FFF_FFFF sRIO-2 I/O 256 MB
  171. 0xC_2000_0000 0xC_2FFF_FFFF sRIO-1 I/O 256 MB
  172. 0xC_0000_0000 0xC_1FFF_FFFF PCIe Mem Space 512 MB
  173. 0x1_0000_0000 0xB_FFFF_FFFF Free 44 GB
  174. 0x0_8000_0000 0x0_FFFF_FFFF DDRC1 2 GB
  175. 0x0_0000_0000 0x0_7FFF_FFFF DDRC2 2 GB
  176. Memory map on B4420QDS
  177. ----------------------
  178. The addresses in brackets are physical addresses.
  179. Start Address End Address Description Size
  180. 0xF_FFDF_1000 0xF_FFFF_FFFF Free 2 MB
  181. 0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4 KB
  182. 0xF_FF81_0000 0xF_FFDE_FFFF Free 5 MB
  183. 0xF_FF80_0000 0xF_FF80_FFFF IFC NAND Flash 64 KB
  184. 0xF_FF00_0000 0xF_FF7F_FFFF Free 8 MB
  185. 0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16 MB
  186. 0xF_F801_0000 0xF_FDFF_FFFF Free 95 MB
  187. 0xF_F800_0000 0xF_F800_FFFF PCIe I/O Space 64 KB
  188. 0xF_F600_0000 0xF_F7FF_FFFF QMAN s/w portal 32 MB
  189. 0xF_F400_0000 0xF_F5FF_FFFF BMAN s/w portal 32 MB
  190. 0xF_F000_0000 0xF_F3FF_FFFF Free 64 MB
  191. 0xF_E800_0000 0xF_EFFF_FFFF IFC NOR Flash 128 MB
  192. 0xF_E000_0000 0xF_E7FF_FFFF Promjet 128 MB
  193. 0xF_A0C0_0000 0xF_DFFF_FFFF Free 1012 MB
  194. 0xF_A000_0000 0xF_A0BF_FFFF MAPLE0/1/2 12 MB
  195. 0xF_0040_0000 0xF_9FFF_FFFF Free 12 GB
  196. 0xF_0000_0000 0xF_01FF_FFFF DCSR 32 MB
  197. 0xC_4000_0000 0xE_FFFF_FFFF Free 11 GB
  198. 0xC_3000_0000 0xC_3FFF_FFFF sRIO-2 I/O 256 MB
  199. 0xC_2000_0000 0xC_2FFF_FFFF sRIO-1 I/O 256 MB
  200. 0xC_0000_0000 0xC_1FFF_FFFF PCIe Mem Space 512 MB
  201. 0x1_0000_0000 0xB_FFFF_FFFF Free 44 GB
  202. 0x0_0000_0000 0x0_FFFF_FFFF DDRC1 4 GB
  203. NOR Flash memory Map on B4860 and B4420QDS
  204. ------------------------------------------
  205. Start End Definition Size
  206. 0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB
  207. 0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB
  208. 0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
  209. 0xEF300000 0xEFEFFFFF rootfs (alternate bank) 12MB
  210. 0xEE800000 0xEE8FFFFF device tree (alternate bank) 1MB
  211. 0xEE020000 0xEE6FFFFF Linux.uImage (alternate bank) 6MB+896KB
  212. 0xEE000000 0xEE01FFFF RCW (alternate bank) 128KB
  213. 0xEDF40000 0xEDFFFFFF U-Boot (alternate bank) 768KB
  214. 0xEDF20000 0xEDF3FFFF U-Boot env (alternate bank) 128KB
  215. 0xEDF00000 0xEDF1FFFF FMAN ucode (alternate bank) 128KB
  216. 0xED300000 0xEDEFFFFF rootfs (current bank) 12MB
  217. 0xEC800000 0xEC8FFFFF device tree (current bank) 1MB
  218. 0xEC020000 0xEC6FFFFF Linux.uImage (current bank) 6MB+896KB
  219. 0xEC000000 0xEC01FFFF RCW (current bank) 128KB
  220. Various Software configurations/environment variables/commands
  221. --------------------------------------------------------------
  222. The below commands apply to both B4860QDS and B4420QDS.
  223. 1. U-Boot environment variable hwconfig
  224. The default hwconfig is:
  225. hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1:
  226. dr_mode=host,phy_type=ulpi
  227. Note: For USB gadget set "dr_mode=peripheral"
  228. 2. FMAN Ucode versions
  229. fsl_fman_ucode_B4860_106_3_6.bin
  230. 3. Switching to alternate bank
  231. Commands for switching to alternate bank.
  232. 1. To change from vbank0 to vbank2
  233. => qixis_reset altbank (it will boot using vbank2)
  234. 2.To change from vbank2 to vbank0
  235. => qixis reset (it will boot using vbank0)
  236. 4. To change personality of board
  237. For changing personality from B4860 to B4420
  238. 1)Boot from vbank0
  239. 2)Flash vbank2 with b4420 rcw and U-Boot
  240. 3)Give following commands to uboot prompt
  241. => mw.b ffdf0040 0x30;
  242. => mw.b ffdf0010 0x00;
  243. => mw.b ffdf0062 0x02;
  244. => mw.b ffdf0050 0x02;
  245. => mw.b ffdf0010 0x30;
  246. => reset
  247. Note: Power off cycle will lead to default switch settings.
  248. Note: 0xffdf0000 is the address of the QIXIS FPGA.
  249. 5. Switching between NOR and NAND boot(RCW src changed from NOR <-> NAND)
  250. To change from NOR to NAND boot give following command on uboot prompt
  251. => mw.b ffdf0040 0x30
  252. => mw.b ffdf0010 0x00
  253. => mw.b 0xffdf0050 0x08
  254. => mw.b 0xffdf0060 0x82
  255. => mw.b ffdf0061 0x00
  256. => mw.b ffdf0010 0x30
  257. => reset
  258. To change from NAND to NOR boot give following command on uboot prompt:
  259. => mw.b ffdf0040 0x30
  260. => mw.b ffdf0010 0x00
  261. => mw.b 0xffdf0050 0x00(for vbank0) or (mw.b 0xffdf0050 0x02 for vbank2)
  262. => mw.b 0xffdf0060 0x12
  263. => mw.b ffdf0061 0x01
  264. => mw.b ffdf0010 0x30
  265. => reset
  266. Note: Power off cycle will lead to default switch settings.
  267. Note: 0xffdf0000 is the address of the QIXIS FPGA.
  268. 6. Ethernet interfaces for B4860QDS
  269. Serdes protocosl tested:
  270. 0x2a, 0x8d (serdes1, serdes2) [DEFAULT]
  271. 0x2a, 0xb2 (serdes1, serdes2)
  272. When using [DEFAULT] RCW, which including 2 * 1G SGMII on board and 2 * 1G
  273. SGMII on SGMII riser card.
  274. Under U-Boot these network interfaces are recognized as:
  275. FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 and FM1@DTSEC6.
  276. On Linux the interfaces are renamed as:
  277. . eth2 -> fm1-gb2
  278. . eth3 -> fm1-gb3
  279. . eth4 -> fm1-gb4
  280. . eth5 -> fm1-gb5
  281. 7. RCW and Ethernet interfaces for B4420QDS
  282. Serdes protocosl tested:
  283. 0x18, 0x9e (serdes1, serdes2)
  284. Under U-Boot these network interfaces are recognized as:
  285. FM1@DTSEC3, FM1@DTSEC4 and e1000#0.
  286. On Linux the interfaces are renamed as:
  287. . eth2 -> fm1-gb2
  288. . eth3 -> fm1-gb3
  289. NAND boot with 2 Stage boot loader
  290. ----------------------------------
  291. PBL initialise the internal SRAM and copy SPL(160KB) in SRAM.
  292. SPL further initialise DDR using SPD and environment variables and copy
  293. U-Boot(768 KB) from flash to DDR.
  294. Finally SPL transer control to U-Boot for futher booting.
  295. SPL has following features:
  296. - Executes within 256K
  297. - No relocation required
  298. Run time view of SPL framework during boot :-
  299. -----------------------------------------------
  300. Area | Address |
  301. -----------------------------------------------
  302. Secure boot | 0xFFFC0000 (32KB) |
  303. headers | |
  304. -----------------------------------------------
  305. GD, BD | 0xFFFC8000 (4KB) |
  306. -----------------------------------------------
  307. ENV | 0xFFFC9000 (8KB) |
  308. -----------------------------------------------
  309. HEAP | 0xFFFCB000 (30KB) |
  310. -----------------------------------------------
  311. STACK | 0xFFFD8000 (22KB) |
  312. -----------------------------------------------
  313. U-Boot SPL | 0xFFFD8000 (160KB) |
  314. -----------------------------------------------
  315. NAND Flash memory Map on B4860 and B4420QDS
  316. ------------------------------------------
  317. Start End Definition Size
  318. 0x000000 0x0FFFFF U-Boot 1MB
  319. 0x140000 0x15FFFF U-Boot env 128KB
  320. 0x1A0000 0x1BFFFF FMAN Ucode 128KB