README.NDS32 1.6 KB

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  1. NDS32 is a new high-performance 32-bit RISC microprocessor core.
  2. http://www.andestech.com/
  3. AndeStar ISA
  4. ============
  5. AndeStar is a patent-pending 16-bit/32-bit mixed-length instruction set to
  6. achieve optimal system performance, code density, and power efficiency.
  7. It contains the following features:
  8. - Intermixable 32-bit and 16-bit instruction sets without the need for
  9. mode switch.
  10. - 16-bit instructions as a frequently used subset of 32-bit instructions.
  11. - RISC-style register-based instruction set.
  12. - 32 32-bit General Purpose Registers (GPR).
  13. - Upto 1024 User Special Registers (USR) for existing and extension
  14. instructions.
  15. - Rich load/store instructions for...
  16. - Single memory access with base address update.
  17. - Multiple aligned and unaligned memory accesses for memory copy and stack
  18. operations.
  19. - Data prefetch to improve data cache performance.
  20. - Non-bus locking synchronization instructions.
  21. - PC relative jump and PC read instructions for efficient position independent
  22. code.
  23. - Multiply-add and multiple-sub with 64-bit accumulator.
  24. - Instruction for efficient power management.
  25. - Bi-endian support.
  26. - Three instruction extension space for application acceleration:
  27. - Performance extension.
  28. - Andes future extensions (for floating-point, multimedia, etc.)
  29. - Customer extensions.
  30. AndesCore CPU
  31. =============
  32. Andes Technology has 4 families of CPU cores: N12, N10, N9, N8.
  33. For details about N12 CPU family, please check doc/README.N1213.
  34. The NDS32 ports of u-boot, the Linux kernel, the GNU toolchain and
  35. other associated software are actively supported by Andes Technology Corporation.