README.N1213 1.4 KB

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  1. N1213 is a configurable hard/soft core of NDS32's N12 CPU family.
  2. Features
  3. ========
  4. CPU Core
  5. - 16-/32-bit mixable instruction format.
  6. - 32 general-purpose 32-bit registers.
  7. - 8-stage pipeline.
  8. - Dynamic branch prediction.
  9. - 32/64/128/256 BTB.
  10. - Return address stack (RAS).
  11. - Vector interrupts for internal/external.
  12. interrupt controller with 6 hardware interrupt signals.
  13. - 3 HW-level nested interruptions.
  14. - User and super-user mode support.
  15. - Memory-mapped I/O.
  16. - Address space up to 4GB.
  17. Memory Management Unit
  18. - TLB
  19. - 4/8-entry fully associative iTLB/dTLB.
  20. - 32/64/128-entry 4-way set-associati.ve main TLB.
  21. - TLB locking support
  22. - Optional hardware page table walker.
  23. - Two groups of page size support.
  24. - 4KB & 1MB.
  25. - 8KB & 1MB.
  26. Memory Subsystem
  27. - I & D cache.
  28. - Virtually indexed and physically tagged.
  29. - Cache size: 8KB/16KB/32KB/64KB.
  30. - Cache line size: 16B/32B.
  31. - Set associativity: 2-way, 4-way or direct-mapped.
  32. - Cache locking support.
  33. - I & D local memory (LM).
  34. - Size: 4KB to 1MB.
  35. - Bank numbers: 1 or 2.
  36. - Optional 1D/2D DMA engine.
  37. - Internal or external to CPU core.
  38. Bus Interface
  39. - Synchronous/Asynchronous AHB bus: 0, 1 or 2 ports.
  40. - Synchronous High speed memory port.
  41. (HSMP): 0, 1 or 2 ports.
  42. Debug
  43. - JTAG debug interface.
  44. - Embedded debug module (EDM).
  45. - Optional embedded program tracer interface.
  46. Miscellaneous
  47. - Programmable data endian control.
  48. - Performance monitoring mechanism.