README.AX25 1.2 KB

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  1. AX25 is Andes CPU IP to adopt RISC-V architecture.
  2. Features
  3. ========
  4. CPU Core
  5. - 5-stage in-order execution pipeline
  6. - Hardware Multiplier
  7. - radix-2/radix-4/radix-16/radix-256/fast
  8. - Hardware Divider
  9. - Optional branch prediction
  10. - Machine mode and optional user mode
  11. - Optional performance monitoring
  12. ISA
  13. - RV64I base integer instructions
  14. - RVC for 16-bit compressed instructions
  15. - RVM for multiplication and division instructions
  16. Memory subsystem
  17. - I & D local memory
  18. - Size: 4KB to 16MB
  19. - Memory subsyetem soft-error protection
  20. - Protection scheme: parity-checking or error-checking-and-correction (ECC)
  21. - Automatic hardware error correction
  22. Bus
  23. - Interface Protocol
  24. - Synchronous AHB (32-bit/64-bit data-width), or
  25. - Synchronous AXI4 (64-bit data-width)
  26. Power management
  27. - Wait for interrupt (WFI) mode
  28. Debug
  29. - Configurable number of breakpoints: 2/4/8
  30. - External Debug Module
  31. - AHB slave port
  32. - External JTAG debug transport module
  33. Platform Level Interrupt Controller (PLIC)
  34. - AHB slave port
  35. - Configurable number of interrupts: 1-1023
  36. - Configurable number of interrupt priorities: 3/7/15/63/127/255
  37. - Configurable number of targets: 1-16
  38. - Preempted interrupt priority stack