cdns3-starfive.c 8.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /**
  3. * cdns-starfive.c - Cadence USB Controller
  4. *
  5. * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
  6. * Author: yanhong <yanhong.wang@starfivetech.com>
  7. */
  8. #include <asm/io.h>
  9. #include <common.h>
  10. #include <clk.h>
  11. #include <dm.h>
  12. #include <dm/device_compat.h>
  13. #include <linux/usb/otg.h>
  14. #include <reset.h>
  15. #include <regmap.h>
  16. #include <syscon.h>
  17. #include "core.h"
  18. #define USB_STRAP_HOST (2 << 0x10)
  19. #define USB_STRAP_DEVICE (4 << 0X10)
  20. #define USB_STRAP_MASK 0x70000
  21. #define USB_SUSPENDM_HOST (1 << 0x13)
  22. #define USB_SUSPENDM_DEVICE (0 << 0x13)
  23. #define USB_SUSPENDM_MASK 0x80000
  24. #define USB_SUSPENDM_BYPS_SHIFT 0x14
  25. #define USB_SUSPENDM_BYPS_MASK 0x100000
  26. #define USB_REFCLK_MODE_SHIFT 0x17
  27. #define USB_REFCLK_MODE_MASK 0x800000
  28. #define USB_PLL_EN_SHIFT 0x16
  29. #define USB_PLL_EN_MASK 0x400000
  30. #define USB_PDRSTN_SPLIT_SHIFT 0x11
  31. #define USB_PDRSTN_SPLIT_MASK 0x20000
  32. #define PCIE_CKREF_SRC_SHIFT 0x12
  33. #define PCIE_CKREF_SRC_MASK 0xC0000
  34. #define PCIE_CLK_SEL_SHIFT 0x14
  35. #define PCIE_CLK_SEL_MASK 0x300000
  36. #define PCIE_PHY_MODE_SHIFT 0x14
  37. #define PCIE_PHY_MODE_MASK 0x300000
  38. #define PCIE_USB3_BUS_WIDTH_SHIFT 0x2
  39. #define PCIE_USB3_BUS_WIDTH_MASK 0xC
  40. #define PCIE_USB3_RATE_SHIFT 0x5
  41. #define PCIE_USB3_RATE_MASK 0x60
  42. #define PCIE_USB3_RX_STANDBY_SHIFT 0x7
  43. #define PCIE_USB3_RX_STANDBY_MASK 0x80
  44. #define PCIE_USB3_PHY_ENABLE_SHIFT 0x4
  45. #define PCIE_USB3_PHY_ENABLE_MASK 0x10
  46. #define PCIE_USB3_PHY_PLL_CTL_OFF (0x1f * 4)
  47. #define USB_125M_CLK_RATE 125000000
  48. #define USB3_PHY_RES_INDEX 0
  49. #define USB2_PHY_RES_INDEX 1
  50. #define USB_LS_KEEPALIVE_OFF 0x4
  51. #define USB_LS_KEEPALIVE_ENABLE 4
  52. struct cdns_starfive {
  53. struct udevice *dev;
  54. struct clk_bulk clks;
  55. struct reset_ctl_bulk resets;
  56. struct regmap *stg_map;
  57. struct regmap *sys_map;
  58. struct clk usb_125m_clk;
  59. void __iomem *phy3_base;
  60. void __iomem *phy2_base;
  61. u32 sys_offset;
  62. u32 stg_offset_4;
  63. u32 stg_offset_196;
  64. u32 stg_offset_328;
  65. u32 stg_offset_500;
  66. u32 usb2_only;
  67. enum usb_dr_mode mode;
  68. };
  69. static int cdns_mode_init(struct cdns_starfive *data)
  70. {
  71. enum usb_dr_mode mode;
  72. int ret;
  73. /* Init usb 2.0 utmi phy */
  74. regmap_update_bits(data->stg_map, data->stg_offset_4,
  75. USB_SUSPENDM_BYPS_MASK, BIT(USB_SUSPENDM_BYPS_SHIFT));
  76. regmap_update_bits(data->stg_map, data->stg_offset_4,
  77. USB_PLL_EN_MASK, BIT(USB_PLL_EN_SHIFT));
  78. regmap_update_bits(data->stg_map, data->stg_offset_4,
  79. USB_REFCLK_MODE_MASK, BIT(USB_REFCLK_MODE_SHIFT));
  80. if (data->usb2_only) {
  81. /* Disconnect usb 3.0 phy mode */
  82. regmap_update_bits(data->sys_map, data->sys_offset,
  83. USB_PDRSTN_SPLIT_MASK, BIT(USB_PDRSTN_SPLIT_SHIFT));
  84. } else {
  85. /* Config usb 3.0 pipe phy */
  86. regmap_update_bits(data->stg_map, data->stg_offset_196,
  87. PCIE_CKREF_SRC_MASK, (0<<PCIE_CKREF_SRC_SHIFT));
  88. regmap_update_bits(data->stg_map, data->stg_offset_196,
  89. PCIE_CLK_SEL_MASK, (0<<PCIE_CLK_SEL_SHIFT));
  90. regmap_update_bits(data->stg_map, data->stg_offset_328,
  91. PCIE_PHY_MODE_MASK, BIT(PCIE_PHY_MODE_SHIFT));
  92. regmap_update_bits(data->stg_map, data->stg_offset_500,
  93. PCIE_USB3_BUS_WIDTH_MASK, (0 << PCIE_USB3_BUS_WIDTH_SHIFT));
  94. regmap_update_bits(data->stg_map, data->stg_offset_500,
  95. PCIE_USB3_RATE_MASK, (0 << PCIE_USB3_RATE_SHIFT));
  96. regmap_update_bits(data->stg_map, data->stg_offset_500,
  97. PCIE_USB3_RX_STANDBY_MASK, (0 << PCIE_USB3_RX_STANDBY_SHIFT));
  98. regmap_update_bits(data->stg_map, data->stg_offset_500,
  99. PCIE_USB3_PHY_ENABLE_MASK, BIT(PCIE_USB3_PHY_ENABLE_SHIFT));
  100. /* Connect usb 3.0 phy mode */
  101. regmap_update_bits(data->sys_map, data->sys_offset,
  102. USB_PDRSTN_SPLIT_MASK, (0 << USB_PDRSTN_SPLIT_SHIFT));
  103. }
  104. mode = usb_get_dr_mode(dev_read_first_subnode(data->dev));
  105. if (mode == USB_DR_MODE_UNKNOWN) {
  106. ret = ofnode_read_u32(dev_read_first_subnode(data->dev), "dr_num_mode" , &mode);
  107. if (ret)
  108. return ret;
  109. }
  110. data->mode = mode;
  111. switch (mode) {
  112. case USB_DR_MODE_HOST:
  113. regmap_update_bits(data->stg_map,
  114. data->stg_offset_4,
  115. USB_STRAP_MASK,
  116. USB_STRAP_HOST);
  117. regmap_update_bits(data->stg_map,
  118. data->stg_offset_4,
  119. USB_SUSPENDM_MASK,
  120. USB_SUSPENDM_HOST);
  121. break;
  122. case USB_DR_MODE_PERIPHERAL:
  123. regmap_update_bits(data->stg_map, data->stg_offset_4,
  124. USB_STRAP_MASK, USB_STRAP_DEVICE);
  125. regmap_update_bits(data->stg_map, data->stg_offset_4,
  126. USB_SUSPENDM_MASK, USB_SUSPENDM_DEVICE);
  127. break;
  128. case USB_DR_MODE_UNKNOWN:
  129. case USB_DR_MODE_OTG:
  130. default:
  131. break;
  132. }
  133. return 0;
  134. }
  135. static int cdns_clk_rst_init(struct cdns_starfive *data)
  136. {
  137. int ret;
  138. ret = clk_get_by_name(data->dev, "125m", &data->usb_125m_clk);
  139. if (ret)
  140. goto exit;
  141. ret = clk_get_bulk(data->dev, &data->clks);
  142. if (ret)
  143. goto err_125m_clk;
  144. ret = reset_get_bulk(data->dev, &data->resets);
  145. if (ret)
  146. goto err_clk;
  147. /* Needs to set the USB_125M clock explicitly,
  148. * since it's divided from pll0 clock, and the pll0 clock
  149. * changes per the cpu frequency.
  150. */
  151. ret = clk_set_rate(&data->usb_125m_clk, USB_125M_CLK_RATE);
  152. if (!ret)
  153. goto err_en_clk;
  154. ret = clk_enable_bulk(&data->clks);
  155. if (ret)
  156. goto err_en_clk;
  157. ret = reset_deassert_bulk(&data->resets);
  158. if (ret)
  159. goto err_reset;
  160. return 0;
  161. err_reset:
  162. clk_disable_bulk(&data->clks);
  163. err_en_clk:
  164. reset_release_bulk(&data->resets);
  165. err_clk:
  166. clk_release_bulk(&data->clks);
  167. err_125m_clk:
  168. clk_free(&data->usb_125m_clk);
  169. exit:
  170. return ret;
  171. }
  172. static void cdns_starfive_set_phy(struct cdns_starfive *data)
  173. {
  174. unsigned int val;
  175. void __iomem *addr;
  176. if (data->mode != USB_DR_MODE_PERIPHERAL) {
  177. /* Enable the LS speed keep-alive signal */
  178. addr = data->phy2_base + USB_LS_KEEPALIVE_OFF;
  179. val = readl(addr);
  180. val |= BIT(USB_LS_KEEPALIVE_ENABLE);
  181. writel(val, addr);
  182. }
  183. if (!data->usb2_only) {
  184. addr = data->phy3_base + PCIE_USB3_PHY_PLL_CTL_OFF;
  185. /* Configuare spread-spectrum mode: down-spread-spectrum */
  186. writel(BIT(4), addr);
  187. }
  188. }
  189. int cdns3_starfive_bind(struct udevice *parent)
  190. {
  191. enum usb_dr_mode dr_mode;
  192. struct udevice *dev;
  193. const char *driver;
  194. const char *name;
  195. ofnode node;
  196. int ret;
  197. node = ofnode_by_compatible(dev_ofnode(parent), "cdns,usb3");
  198. if (!ofnode_valid(node)) {
  199. printf("%s: failed to get usb node\n",
  200. __func__);
  201. goto fail;
  202. }
  203. dr_mode = usb_get_dr_mode(node);
  204. if (dr_mode != USB_DR_MODE_UNKNOWN)
  205. return cdns3_bind(parent);
  206. name = ofnode_get_name(node);
  207. #if defined(CONFIG_SPL_USB_HOST) || \
  208. (!defined(CONFIG_SPL_BUILD) && defined(CONFIG_USB_HOST))
  209. ret = device_bind_driver_to_node(parent, "cdns-usb3-host", name, node, &dev);
  210. if (ret) {
  211. printf("%s: not able to bind usb host mode\n",
  212. __func__);
  213. goto fail;
  214. }
  215. #endif
  216. #if CONFIG_IS_ENABLED(DM_USB_GADGET)
  217. ret = device_bind_driver_to_node(parent, "cdns-usb3-peripheral", name, node, &dev);
  218. if (ret) {
  219. printf("%s: not able to bind usb device mode\n",
  220. __func__);
  221. goto fail;
  222. }
  223. #endif
  224. fail:
  225. /* do not return an error: failing to bind would hang the board */
  226. return 0;
  227. }
  228. static int cdns_starfive_probe(struct udevice *dev)
  229. {
  230. struct cdns_starfive *data = dev_get_plat(dev);
  231. struct ofnode_phandle_args args;
  232. int ret;
  233. data->dev = dev;
  234. data->phy3_base = (void *)dev_read_addr_index(dev, USB3_PHY_RES_INDEX);
  235. if (data->phy3_base == (void __iomem *)FDT_ADDR_T_NONE) {
  236. dev_err(dev, "Missing phy 3.0 reg base\n");
  237. return -EINVAL;
  238. }
  239. data->phy2_base = (void *)dev_read_addr_index(dev, USB2_PHY_RES_INDEX);
  240. if (data->phy2_base == (void __iomem *)FDT_ADDR_T_NONE) {
  241. dev_err(dev, "Missing phy 2.0 reg base");
  242. return -EINVAL;
  243. }
  244. ret = dev_read_u32(dev, "starfive,usb2-only", &data->usb2_only);
  245. if (ret)
  246. return ret;
  247. ret = dev_read_phandle_with_args(dev, "starfive,stg-syscon", NULL, 4, 0, &args);
  248. if (ret)
  249. return ret;
  250. data->stg_map = syscon_node_to_regmap(args.node);
  251. if (IS_ERR(data->stg_map))
  252. return PTR_ERR(data->stg_map);
  253. data->stg_offset_4 = args.args[0];
  254. data->stg_offset_196 = args.args[1];
  255. data->stg_offset_328 = args.args[2];
  256. data->stg_offset_500 = args.args[3];
  257. ret = dev_read_phandle_with_args(dev, "starfive,sys-syscon", NULL, 1, 0, &args);
  258. if (ret)
  259. return ret;
  260. data->sys_map = syscon_node_to_regmap(args.node);
  261. if (IS_ERR(data->sys_map))
  262. return PTR_ERR(data->sys_map);
  263. data->sys_offset = args.args[0];
  264. cdns_mode_init(data);
  265. ret = cdns_clk_rst_init(data);
  266. if (ret < 0) {
  267. pr_err("Failed to init usb clk reset: %d\n", ret);
  268. return ret;
  269. }
  270. cdns_starfive_set_phy(data);
  271. return ret;
  272. }
  273. static int cdns_starfive_remove(struct udevice *dev)
  274. {
  275. struct cdns_starfive *data = dev_get_plat(dev);
  276. clk_release_bulk(&data->clks);
  277. reset_assert_bulk(&data->resets);
  278. clk_free(&data->usb_125m_clk);
  279. return 0;
  280. }
  281. static const struct udevice_id cdns_starfive_of_match[] = {
  282. { .compatible = "starfive,jh7110-cdns3", },
  283. {},
  284. };
  285. U_BOOT_DRIVER(cdns_starfive) = {
  286. .name = "cdns-starfive",
  287. .id = UCLASS_NOP,
  288. .of_match = cdns_starfive_of_match,
  289. .bind = cdns3_starfive_bind,
  290. .probe = cdns_starfive_probe,
  291. .remove = cdns_starfive_remove,
  292. .plat_auto = sizeof(struct cdns_starfive),
  293. };