ddr_spd.h 16 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341
  1. /*
  2. * Copyright 2008 Freescale Semiconductor, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * Version 2 as published by the Free Software Foundation.
  7. */
  8. #ifndef _DDR_SPD_H_
  9. #define _DDR_SPD_H_
  10. /*
  11. * Format from "JEDEC Standard No. 21-C,
  12. * Appendix D: Rev 1.0: SPD's for DDR SDRAM
  13. */
  14. typedef struct ddr1_spd_eeprom_s {
  15. unsigned char info_size; /* 0 # bytes written into serial memory */
  16. unsigned char chip_size; /* 1 Total # bytes of SPD memory device */
  17. unsigned char mem_type; /* 2 Fundamental memory type */
  18. unsigned char nrow_addr; /* 3 # of Row Addresses on this assembly */
  19. unsigned char ncol_addr; /* 4 # of Column Addrs on this assembly */
  20. unsigned char nrows; /* 5 Number of DIMM Banks */
  21. unsigned char dataw_lsb; /* 6 Data Width of this assembly */
  22. unsigned char dataw_msb; /* 7 ... Data Width continuation */
  23. unsigned char voltage; /* 8 Voltage intf std of this assembly */
  24. unsigned char clk_cycle; /* 9 SDRAM Cycle time @ CL=X */
  25. unsigned char clk_access; /* 10 SDRAM Access from Clk @ CL=X (tAC) */
  26. unsigned char config; /* 11 DIMM Configuration type */
  27. unsigned char refresh; /* 12 Refresh Rate/Type */
  28. unsigned char primw; /* 13 Primary SDRAM Width */
  29. unsigned char ecw; /* 14 Error Checking SDRAM width */
  30. unsigned char min_delay; /* 15 for Back to Back Random Address */
  31. unsigned char burstl; /* 16 Burst Lengths Supported */
  32. unsigned char nbanks; /* 17 # of Banks on SDRAM Device */
  33. unsigned char cas_lat; /* 18 CAS# Latencies Supported */
  34. unsigned char cs_lat; /* 19 CS# Latency */
  35. unsigned char write_lat; /* 20 Write Latency (aka Write Recovery) */
  36. unsigned char mod_attr; /* 21 SDRAM Module Attributes */
  37. unsigned char dev_attr; /* 22 SDRAM Device Attributes */
  38. unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time @ CL=X-0.5 */
  39. unsigned char clk_access2; /* 24 SDRAM Access from
  40. Clk @ CL=X-0.5 (tAC) */
  41. unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time @ CL=X-1 */
  42. unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-1 (tAC) */
  43. unsigned char trp; /* 27 Min Row Precharge Time (tRP)*/
  44. unsigned char trrd; /* 28 Min Row Active to Row Active (tRRD) */
  45. unsigned char trcd; /* 29 Min RAS to CAS Delay (tRCD) */
  46. unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */
  47. unsigned char bank_dens; /* 31 Density of each bank on module */
  48. unsigned char ca_setup; /* 32 Addr + Cmd Setup Time Before Clk */
  49. unsigned char ca_hold; /* 33 Addr + Cmd Hold Time After Clk */
  50. unsigned char data_setup; /* 34 Data Input Setup Time Before Strobe */
  51. unsigned char data_hold; /* 35 Data Input Hold Time After Strobe */
  52. unsigned char res_36_40[5];/* 36-40 reserved for VCSDRAM */
  53. unsigned char trc; /* 41 Min Active to Auto refresh time tRC */
  54. unsigned char trfc; /* 42 Min Auto to Active period tRFC */
  55. unsigned char tckmax; /* 43 Max device cycle time tCKmax */
  56. unsigned char tdqsq; /* 44 Max DQS to DQ skew (tDQSQ max) */
  57. unsigned char tqhs; /* 45 Max Read DataHold skew (tQHS) */
  58. unsigned char res_46; /* 46 Reserved */
  59. unsigned char dimm_height; /* 47 DDR SDRAM DIMM Height */
  60. unsigned char res_48_61[14]; /* 48-61 Reserved */
  61. unsigned char spd_rev; /* 62 SPD Data Revision Code */
  62. unsigned char cksum; /* 63 Checksum for bytes 0-62 */
  63. unsigned char mid[8]; /* 64-71 Mfr's JEDEC ID code per JEP-106 */
  64. unsigned char mloc; /* 72 Manufacturing Location */
  65. unsigned char mpart[18]; /* 73 Manufacturer's Part Number */
  66. unsigned char rev[2]; /* 91 Revision Code */
  67. unsigned char mdate[2]; /* 93 Manufacturing Date */
  68. unsigned char sernum[4]; /* 95 Assembly Serial Number */
  69. unsigned char mspec[27]; /* 99-127 Manufacturer Specific Data */
  70. } ddr1_spd_eeprom_t;
  71. /*
  72. * Format from "JEDEC Appendix X: Serial Presence Detects for DDR2 SDRAM",
  73. * SPD Revision 1.2
  74. */
  75. typedef struct ddr2_spd_eeprom_s {
  76. unsigned char info_size; /* 0 # bytes written into serial memory */
  77. unsigned char chip_size; /* 1 Total # bytes of SPD memory device */
  78. unsigned char mem_type; /* 2 Fundamental memory type */
  79. unsigned char nrow_addr; /* 3 # of Row Addresses on this assembly */
  80. unsigned char ncol_addr; /* 4 # of Column Addrs on this assembly */
  81. unsigned char mod_ranks; /* 5 Number of DIMM Ranks */
  82. unsigned char dataw; /* 6 Module Data Width */
  83. unsigned char res_7; /* 7 Reserved */
  84. unsigned char voltage; /* 8 Voltage intf std of this assembly */
  85. unsigned char clk_cycle; /* 9 SDRAM Cycle time @ CL=X */
  86. unsigned char clk_access; /* 10 SDRAM Access from Clk @ CL=X (tAC) */
  87. unsigned char config; /* 11 DIMM Configuration type */
  88. unsigned char refresh; /* 12 Refresh Rate/Type */
  89. unsigned char primw; /* 13 Primary SDRAM Width */
  90. unsigned char ecw; /* 14 Error Checking SDRAM width */
  91. unsigned char res_15; /* 15 Reserved */
  92. unsigned char burstl; /* 16 Burst Lengths Supported */
  93. unsigned char nbanks; /* 17 # of Banks on Each SDRAM Device */
  94. unsigned char cas_lat; /* 18 CAS# Latencies Supported */
  95. unsigned char mech_char; /* 19 DIMM Mechanical Characteristics */
  96. unsigned char dimm_type; /* 20 DIMM type information */
  97. unsigned char mod_attr; /* 21 SDRAM Module Attributes */
  98. unsigned char dev_attr; /* 22 SDRAM Device Attributes */
  99. unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time @ CL=X-1 */
  100. unsigned char clk_access2; /* 24 SDRAM Access from Clk @ CL=X-1 (tAC) */
  101. unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time @ CL=X-2 */
  102. unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-2 (tAC) */
  103. unsigned char trp; /* 27 Min Row Precharge Time (tRP)*/
  104. unsigned char trrd; /* 28 Min Row Active to Row Active (tRRD) */
  105. unsigned char trcd; /* 29 Min RAS to CAS Delay (tRCD) */
  106. unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */
  107. unsigned char rank_dens; /* 31 Density of each rank on module */
  108. unsigned char ca_setup; /* 32 Addr+Cmd Setup Time Before Clk (tIS) */
  109. unsigned char ca_hold; /* 33 Addr+Cmd Hold Time After Clk (tIH) */
  110. unsigned char data_setup; /* 34 Data Input Setup Time
  111. Before Strobe (tDS) */
  112. unsigned char data_hold; /* 35 Data Input Hold Time
  113. After Strobe (tDH) */
  114. unsigned char twr; /* 36 Write Recovery time tWR */
  115. unsigned char twtr; /* 37 Int write to read delay tWTR */
  116. unsigned char trtp; /* 38 Int read to precharge delay tRTP */
  117. unsigned char mem_probe; /* 39 Mem analysis probe characteristics */
  118. unsigned char trctrfc_ext; /* 40 Extensions to trc and trfc */
  119. unsigned char trc; /* 41 Min Active to Auto refresh time tRC */
  120. unsigned char trfc; /* 42 Min Auto to Active period tRFC */
  121. unsigned char tckmax; /* 43 Max device cycle time tCKmax */
  122. unsigned char tdqsq; /* 44 Max DQS to DQ skew (tDQSQ max) */
  123. unsigned char tqhs; /* 45 Max Read DataHold skew (tQHS) */
  124. unsigned char pll_relock; /* 46 PLL Relock time */
  125. unsigned char Tcasemax; /* 47 Tcasemax */
  126. unsigned char psiTAdram; /* 48 Thermal Resistance of DRAM Package from
  127. Top (Case) to Ambient (Psi T-A DRAM) */
  128. unsigned char dt0_mode; /* 49 DRAM Case Temperature Rise from Ambient
  129. due to Activate-Precharge/Mode Bits
  130. (DT0/Mode Bits) */
  131. unsigned char dt2n_dt2q; /* 50 DRAM Case Temperature Rise from Ambient
  132. due to Precharge/Quiet Standby
  133. (DT2N/DT2Q) */
  134. unsigned char dt2p; /* 51 DRAM Case Temperature Rise from Ambient
  135. due to Precharge Power-Down (DT2P) */
  136. unsigned char dt3n; /* 52 DRAM Case Temperature Rise from Ambient
  137. due to Active Standby (DT3N) */
  138. unsigned char dt3pfast; /* 53 DRAM Case Temperature Rise from Ambient
  139. due to Active Power-Down with
  140. Fast PDN Exit (DT3Pfast) */
  141. unsigned char dt3pslow; /* 54 DRAM Case Temperature Rise from Ambient
  142. due to Active Power-Down with Slow
  143. PDN Exit (DT3Pslow) */
  144. unsigned char dt4r_dt4r4w; /* 55 DRAM Case Temperature Rise from Ambient
  145. due to Page Open Burst Read/DT4R4W
  146. Mode Bit (DT4R/DT4R4W Mode Bit) */
  147. unsigned char dt5b; /* 56 DRAM Case Temperature Rise from Ambient
  148. due to Burst Refresh (DT5B) */
  149. unsigned char dt7; /* 57 DRAM Case Temperature Rise from Ambient
  150. due to Bank Interleave Reads with
  151. Auto-Precharge (DT7) */
  152. unsigned char psiTApll; /* 58 Thermal Resistance of PLL Package form
  153. Top (Case) to Ambient (Psi T-A PLL) */
  154. unsigned char psiTAreg; /* 59 Thermal Reisitance of Register Package
  155. from Top (Case) to Ambient
  156. (Psi T-A Register) */
  157. unsigned char dtpllactive; /* 60 PLL Case Temperature Rise from Ambient
  158. due to PLL Active (DT PLL Active) */
  159. unsigned char dtregact; /* 61 Register Case Temperature Rise from
  160. Ambient due to Register Active/Mode Bit
  161. (DT Register Active/Mode Bit) */
  162. unsigned char spd_rev; /* 62 SPD Data Revision Code */
  163. unsigned char cksum; /* 63 Checksum for bytes 0-62 */
  164. unsigned char mid[8]; /* 64 Mfr's JEDEC ID code per JEP-106 */
  165. unsigned char mloc; /* 72 Manufacturing Location */
  166. unsigned char mpart[18]; /* 73 Manufacturer's Part Number */
  167. unsigned char rev[2]; /* 91 Revision Code */
  168. unsigned char mdate[2]; /* 93 Manufacturing Date */
  169. unsigned char sernum[4]; /* 95 Assembly Serial Number */
  170. unsigned char mspec[27]; /* 99-127 Manufacturer Specific Data */
  171. } ddr2_spd_eeprom_t;
  172. typedef struct ddr3_spd_eeprom_s {
  173. /* General Section: Bytes 0-59 */
  174. unsigned char info_size_crc; /* 0 # bytes written into serial memory,
  175. CRC coverage */
  176. unsigned char spd_rev; /* 1 Total # bytes of SPD mem device */
  177. unsigned char mem_type; /* 2 Key Byte / Fundamental mem type */
  178. unsigned char module_type; /* 3 Key Byte / Module Type */
  179. unsigned char density_banks; /* 4 SDRAM Density and Banks */
  180. unsigned char addressing; /* 5 SDRAM Addressing */
  181. unsigned char module_vdd; /* 6 Module nominal voltage, VDD */
  182. unsigned char organization; /* 7 Module Organization */
  183. unsigned char bus_width; /* 8 Module Memory Bus Width */
  184. unsigned char ftb_div; /* 9 Fine Timebase (FTB)
  185. Dividend / Divisor */
  186. unsigned char mtb_dividend; /* 10 Medium Timebase (MTB) Dividend */
  187. unsigned char mtb_divisor; /* 11 Medium Timebase (MTB) Divisor */
  188. unsigned char tCK_min; /* 12 SDRAM Minimum Cycle Time */
  189. unsigned char res_13; /* 13 Reserved */
  190. unsigned char caslat_lsb; /* 14 CAS Latencies Supported,
  191. Least Significant Byte */
  192. unsigned char caslat_msb; /* 15 CAS Latencies Supported,
  193. Most Significant Byte */
  194. unsigned char tAA_min; /* 16 Min CAS Latency Time */
  195. unsigned char tWR_min; /* 17 Min Write REcovery Time */
  196. unsigned char tRCD_min; /* 18 Min RAS# to CAS# Delay Time */
  197. unsigned char tRRD_min; /* 19 Min Row Active to
  198. Row Active Delay Time */
  199. unsigned char tRP_min; /* 20 Min Row Precharge Delay Time */
  200. unsigned char tRAS_tRC_ext; /* 21 Upper Nibbles for tRAS and tRC */
  201. unsigned char tRAS_min_lsb; /* 22 Min Active to Precharge
  202. Delay Time */
  203. unsigned char tRC_min_lsb; /* 23 Min Active to Active/Refresh
  204. Delay Time, LSB */
  205. unsigned char tRFC_min_lsb; /* 24 Min Refresh Recovery Delay Time */
  206. unsigned char tRFC_min_msb; /* 25 Min Refresh Recovery Delay Time */
  207. unsigned char tWTR_min; /* 26 Min Internal Write to
  208. Read Command Delay Time */
  209. unsigned char tRTP_min; /* 27 Min Internal Read to Precharge
  210. Command Delay Time */
  211. unsigned char tFAW_msb; /* 28 Upper Nibble for tFAW */
  212. unsigned char tFAW_min; /* 29 Min Four Activate Window
  213. Delay Time*/
  214. unsigned char opt_features; /* 30 SDRAM Optional Features */
  215. unsigned char therm_ref_opt; /* 31 SDRAM Thermal and Refresh Opts */
  216. unsigned char therm_sensor; /* 32 Module Thermal Sensor */
  217. unsigned char device_type; /* 33 SDRAM device type */
  218. int8_t fine_tCK_min; /* 34 Fine offset for tCKmin */
  219. int8_t fine_tAA_min; /* 35 Fine offset for tAAmin */
  220. int8_t fine_tRCD_min; /* 36 Fine offset for tRCDmin */
  221. int8_t fine_tRP_min; /* 37 Fine offset for tRPmin */
  222. int8_t fine_tRC_min; /* 38 Fine offset for tRCmin */
  223. unsigned char res_39_59[21]; /* 39-59 Reserved, General Section */
  224. /* Module-Specific Section: Bytes 60-116 */
  225. union {
  226. struct {
  227. /* 60 (Unbuffered) Module Nominal Height */
  228. unsigned char mod_height;
  229. /* 61 (Unbuffered) Module Maximum Thickness */
  230. unsigned char mod_thickness;
  231. /* 62 (Unbuffered) Reference Raw Card Used */
  232. unsigned char ref_raw_card;
  233. /* 63 (Unbuffered) Address Mapping from
  234. Edge Connector to DRAM */
  235. unsigned char addr_mapping;
  236. /* 64-116 (Unbuffered) Reserved */
  237. unsigned char res_64_116[53];
  238. } unbuffered;
  239. struct {
  240. /* 60 (Registered) Module Nominal Height */
  241. unsigned char mod_height;
  242. /* 61 (Registered) Module Maximum Thickness */
  243. unsigned char mod_thickness;
  244. /* 62 (Registered) Reference Raw Card Used */
  245. unsigned char ref_raw_card;
  246. /* 63 DIMM Module Attributes */
  247. unsigned char modu_attr;
  248. /* 64 RDIMM Thermal Heat Spreader Solution */
  249. unsigned char thermal;
  250. /* 65 Register Manufacturer ID Code, Least Significant Byte */
  251. unsigned char reg_id_lo;
  252. /* 66 Register Manufacturer ID Code, Most Significant Byte */
  253. unsigned char reg_id_hi;
  254. /* 67 Register Revision Number */
  255. unsigned char reg_rev;
  256. /* 68 Register Type */
  257. unsigned char reg_type;
  258. /* 69-76 RC1,3,5...15 (MS Nibble) / RC0,2,4...14 (LS Nibble) */
  259. unsigned char rcw[8];
  260. } registered;
  261. unsigned char uc[57]; /* 60-116 Module-Specific Section */
  262. } mod_section;
  263. /* Unique Module ID: Bytes 117-125 */
  264. unsigned char mmid_lsb; /* 117 Module MfgID Code LSB - JEP-106 */
  265. unsigned char mmid_msb; /* 118 Module MfgID Code MSB - JEP-106 */
  266. unsigned char mloc; /* 119 Mfg Location */
  267. unsigned char mdate[2]; /* 120-121 Mfg Date */
  268. unsigned char sernum[4]; /* 122-125 Module Serial Number */
  269. /* CRC: Bytes 126-127 */
  270. unsigned char crc[2]; /* 126-127 SPD CRC */
  271. /* Other Manufacturer Fields and User Space: Bytes 128-255 */
  272. unsigned char mpart[18]; /* 128-145 Mfg's Module Part Number */
  273. unsigned char mrev[2]; /* 146-147 Module Revision Code */
  274. unsigned char dmid_lsb; /* 148 DRAM MfgID Code LSB - JEP-106 */
  275. unsigned char dmid_msb; /* 149 DRAM MfgID Code MSB - JEP-106 */
  276. unsigned char msd[26]; /* 150-175 Mfg's Specific Data */
  277. unsigned char cust[80]; /* 176-255 Open for Customer Use */
  278. } ddr3_spd_eeprom_t;
  279. extern unsigned int ddr1_spd_check(const ddr1_spd_eeprom_t *spd);
  280. extern void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd);
  281. extern unsigned int ddr2_spd_check(const ddr2_spd_eeprom_t *spd);
  282. extern void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd);
  283. extern unsigned int ddr3_spd_check(const ddr3_spd_eeprom_t *spd);
  284. /*
  285. * Byte 2 Fundamental Memory Types.
  286. */
  287. #define SPD_MEMTYPE_FPM (0x01)
  288. #define SPD_MEMTYPE_EDO (0x02)
  289. #define SPD_MEMTYPE_PIPE_NIBBLE (0x03)
  290. #define SPD_MEMTYPE_SDRAM (0x04)
  291. #define SPD_MEMTYPE_ROM (0x05)
  292. #define SPD_MEMTYPE_SGRAM (0x06)
  293. #define SPD_MEMTYPE_DDR (0x07)
  294. #define SPD_MEMTYPE_DDR2 (0x08)
  295. #define SPD_MEMTYPE_DDR2_FBDIMM (0x09)
  296. #define SPD_MEMTYPE_DDR2_FBDIMM_PROBE (0x0A)
  297. #define SPD_MEMTYPE_DDR3 (0x0B)
  298. /* DIMM Type for DDR2 SPD (according to v1.3) */
  299. #define DDR2_SPD_DIMMTYPE_UNDEFINED (0x00)
  300. #define DDR2_SPD_DIMMTYPE_RDIMM (0x01)
  301. #define DDR2_SPD_DIMMTYPE_UDIMM (0x02)
  302. #define DDR2_SPD_DIMMTYPE_SO_DIMM (0x04)
  303. #define DDR2_SPD_DIMMTYPE_72B_SO_CDIMM (0x06)
  304. #define DDR2_SPD_DIMMTYPE_72B_SO_RDIMM (0x07)
  305. #define DDR2_SPD_DIMMTYPE_MICRO_DIMM (0x08)
  306. #define DDR2_SPD_DIMMTYPE_MINI_RDIMM (0x10)
  307. #define DDR2_SPD_DIMMTYPE_MINI_UDIMM (0x20)
  308. /* Byte 3 Key Byte / Module Type for DDR3 SPD */
  309. #define DDR3_SPD_MODULETYPE_MASK (0x0f)
  310. #define DDR3_SPD_MODULETYPE_RDIMM (0x01)
  311. #define DDR3_SPD_MODULETYPE_UDIMM (0x02)
  312. #define DDR3_SPD_MODULETYPE_SO_DIMM (0x03)
  313. #define DDR3_SPD_MODULETYPE_MICRO_DIMM (0x04)
  314. #define DDR3_SPD_MODULETYPE_MINI_RDIMM (0x05)
  315. #define DDR3_SPD_MODULETYPE_MINI_UDIMM (0x06)
  316. #define DDR3_SPD_MODULETYPE_MINI_CDIMM (0x07)
  317. #define DDR3_SPD_MODULETYPE_72B_SO_UDIMM (0x08)
  318. #define DDR3_SPD_MODULETYPE_72B_SO_RDIMM (0x09)
  319. #define DDR3_SPD_MODULETYPE_72B_SO_CDIMM (0x0A)
  320. #define DDR3_SPD_MODULETYPE_LRDIMM (0x0B)
  321. #define DDR3_SPD_MODULETYPE_16B_SO_DIMM (0x0C)
  322. #define DDR3_SPD_MODULETYPE_32B_SO_DIMM (0x0D)
  323. #endif /* _DDR_SPD_H_ */